Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-5 in the reply filed on February 23rd, 2026, are acknowledged. Claims 1-2 have been amended. Claims 6-10 have been withdrawn from consideration. Claims 1-10 are pending.
Action on merits of claims 1-5 as follows.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2007/0080456, hereinafter as Chang ‘456) in view of Zhao (US 2001/0015497, hereinafter as Zhao ‘497) and further in view of Kim (US 6,268,568, hereinafter as Kim ‘568).
Regarding Claim 1, Chang ‘456 teaches a ball grid array, formed on a printed circuit board (420; [0033]), comprising:
an inner row region (Fig. 4, (Z3); [0033]) including a plurality of first solder balls (405; [0028] and [0033]) that are arranged by a first ball pitch (S3; [0034]), and an outer row region (Fig. 4, (Z2); [0033]) being disposed to surround the inner row region, wherein the outer row region includes a plurality of second solder balls that are arranged by a second ball pitch (S2), and wherein the second ball pitch (S2) is smaller than the first ball pitch (S3) (see para. [0034]).
Chang ‘456 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the plurality of first solder balls respectively correspond to a plurality of vias”.
Zhao ‘497 teaches the plurality of first solder balls (Fig. 1, (40); [0026]) respectively correspond to a plurality of vias (Fig. 1, (32); [0024]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Chang ‘456 by having the plurality of first solder balls respectively correspond to a plurality of vias for the purpose of providing appropriate electrical connections intermediate integrated circuitry and external circuitry (see para. [0024]) as suggested by Zhao ‘497.
Chang ‘456 and Zhao ‘497 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first ball pitch is within a range from 187.5% to 200% of an outer diameter of any one of the plurality of vias”.
Kim ‘568 teaches the first ball pitch is within a range of 1.27/0.8=158.72% to 1.27/0.632=200.94% which overlaps the claim range of 187.5% to 200% of an outer diameter of any one of the plurality of vias (see Figs. 5A and 5B; col. 9, lines 60-65).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Chang ‘456 and Zhao ‘497 by having the first ball pitch is within a range from 187.5% to 200% of an outer diameter of any one of the plurality of vias for the purpose of providing a higher operational reliability and having higher density assembled packages (see col. 10, lines 1-6) as suggested by Kim ‘568.
Further, it has been held to be within the general skill of a worker in the art to select the first ball pitch is within a range from 187.5% to 200% of an outer diameter of any one of the plurality of vias on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
PNG
media_image1.png
18
19
media_image1.png
Greyscale
A person of ordinary skills in the art is motivated to select the first ball pitch is within a range from 187.5% to 200% of an outer diameter of any one of the plurality of vias when this improves the performance of the ball-grid array integrated circuit package.
PNG
media_image2.png
356
352
media_image2.png
Greyscale
Fig. 4a (Chang ‘456)
Regarding Claim 2, Chang ‘456 teaches the distance between two adjacent ones of the plurality of first solder balls (S3) is defined as a trace width.
Regarding Claim 3, Zhao ‘497 teaches the first ball pitch is 1 mm or less (see para. [0005]) which overlaps the claim range of 0.8 mm or 0.75 mm.
Regarding Claim 4, Chang ‘456 teaches the second ball pitch (S2) is smaller than the first ball pitch (S3) (see para. [0034]).
Zhao ‘497 teaches the ball pitch is 1 mm or less (see para. [0005]) which overlaps the claim range of 0.65 mm.
Regarding Claim 5, Chang ‘456 teaches the inner row region (Z3) is one region of the ball grid array (405) adjacent to a center of the printed circuit board (420; [0033]), and the outer row region is another region of the ball grid array (405) adjacent to edges of the printed circuit board (420; [0033]).
Zhao ‘497 teaches a printed circuit board (PCB) (see para. [0021]).
Response to Arguments
Applicant’s arguments with respect to claims 1-5, filed on February 23rd, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893
Prosecution Insights