DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 11, and 20 have been amended.
Claims 21 and 22 have been added.
Claims 1-5, 7, and 9-22 have been examined.
The drawing objections in the previous Office Action have been addressed and are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 17, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9-16, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2018/0189642 by Boesch et al. (hereinafter referred to as “Boesch”) in view of US Publication No. 2018/0157465 by Bittner et al. (previously cited and hereinafter referred to as “Bittner”) in view of US Publication No. 2018/0218518 by Yan et al. (previously cited and hereinafter referred to as “Yan”).
Regarding claims 1, 11, and 20, taking claim 1 as representative, Boesch discloses:
an apparatus comprising: a processing element (PE) for neural network computations, the PE comprising (Boesch discloses, at Figure 6A, an accelerator, i.e., a processing element, for neural network computations.):
a first input register configured to store a first Xin element, wherein the first Xin element is part of an input data set … (Boesch discloses, at ¶ [0237], a feature buffer for storing multiple input values. As disclosed at a ¶ [0233], the buffer can be implemented as registers.);
a second input register configured to store a second Xin element… (Boesch discloses, at ¶ [0237], a feature buffer for storing multiple input values. As disclosed at a ¶ [0233], the buffer can be implemented as registers.);
a weight register configured to store a weight value (Boesch discloses, at ¶ [0236], a kernel buffer for storing kernel data, i.e., weight values. As disclosed at a ¶ [0233], the buffer can be implemented as registers.);
a first multiplier configured to receive the first Xin element from the first input register and the weight value from the weight register, and to multiply the first Xin element with the weight value to generate a first multiplication result during a particular clock cycle (Boesch discloses, at ¶ [0236], a plurality of multiply and accumulate units, which discloses a first and second multiplier to multiply feature and kernel data to generate a first multiplication result during a particular clock cycle.); and
a second multiplier configured to receive the second Xin element from the second input register and the weight value from the weight register, and to multiply the second Xin element with the weight value to generate a second multiplication result during the particular clock cycle, such that the PE is configured to use a single weight value from the weight register … (Boesch discloses, at ¶ [0236], a plurality of multiply and accumulate units, which discloses a first and second multiplier to multiply feature and kernel data. Boesch also discloses, at ¶ [0150] et seq., performing multiple operations concurrently during a particular cycle.).
Boesch does not explicitly disclose the aforementioned input data set is for a given row of a systolic array, the aforementioned second Xin element is a sequential element to the first for the given row, and the aforementioned single weight value is applied simultaneously to distinct inputs of both multipliers.
However, in the same field of endeavor (e.g., neural network processing) Bittner discloses:
sequential input to given rows of a systolic array (Bittner discloses, at Figure 3B and related description, taking sequential values as input to a particular row of systolic array.).
It would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify Boesch to include systolic arrays, as disclosed by Bittner, in order to improve performance by increasing efficiency of parallel operations.
Also in the same field of endeavor (e.g., neural network processing) Yan discloses:
applying a single weight value simultaneously to the inputs of multiple multipliers during a single cycle (Yan discloses, at ¶ [0046], the single weight value W1 is simultaneously multiplied by several input values A1-A6. This discloses the single weight value being applied simultaneously to distinct inputs of two multipliers.).
It would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify Boesch to include simultaneously using a single weight value in multiple computations, as disclosed by Yan, in order to improve performance by increasing efficiency with regard to data movement.
Regarding claims 2 and 12, taking claim 2 as representative, Boesch discloses the elements of claim 1, as discussed above. Boesch also discloses:
wherein the PE further comprises: a first adder configured to receive the first multiplication result and generate a first Yout element based on the first multiplication result (Boesch discloses, at ¶ [0237], an adder tree, which discloses first and second adders, that receives products from the MACs and sums the products with incoming data from other accelerators.); and
a second adder configured to receive the second multiplication result and generate a second Yout element based on the second multiplication result (Boesch discloses, at ¶ [0237], an adder tree, which discloses first and second adders, that receives products from the MACs and sums the products with incoming data from other accelerators.).
Regarding claims 3 and 13, taking claim 3 as representative, Boesch discloses the elements of claim 2, as discussed above. Boesch also discloses:
the first adder is further configured to receive a first Yin element and to generate the first Yout element by adding the first Yin element with the first multiplication result (Boesch discloses, at ¶ [0237], an adder tree, which discloses first and second adders, that receives products from the MACs and sums the products with incoming data from other accelerators.); and
the second adder is further configured to receive a second Yin element and to generate the second Yout element by adding the second Yin element with the second multiplication result (Boesch discloses, at ¶ [0237], an adder tree, which discloses first and second adders, that receives products from the MACs and sums the products with incoming data from other accelerators.).
Regarding claim 4, Boesch discloses the elements of claim 3, as discussed above. Boesch does not explicitly disclose the first multiplier and the first adder form a first fused multiplier adder (FMA); and the second multiplier and the second adder form a second FMA.
However, it would have been obvious to modify Boesch such that the disclosed multipliers and adders are utilized as a fused multiplier adder because doing so merely involves combining the disclosed elements in a predictable fashion. Whether to utilized FMA or not is an obvious design choice within the skill of a person having ordinary skill in the art. For example, Boesch indicates that the disclosed components can be combined in any suitable manner. See Boesch, ¶ [0329].
Regarding claims 5 and 14, taking claim 5 as representative, Boesch discloses the elements of claim 3, as discussed above. Boesch also discloses:
wherein the PE further comprises: a first input port to receive the first Yin element (Boesch discloses, at ¶ [0231], an interface to receive the incoming data.).
Boesch does not explicitly disclose a second input port to receive the second Yin element. However, it would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify Boesch to include a second port because doing so is merely duplicating parts. Whether to stream data through a single port or multiple ports is an obvious design choice involving well-known tradeoffs, such as size versus speed.
Regarding claims 7 and 16, taking claim 7 as representative, Boesch discloses the elements of claim 1, as discussed above. Boesch also discloses:
wherein the PE further comprises: a first input port to receive the first Xin element (Boesch discloses, at ¶ [0232], an interface to input kernel data.).
Boesch does not explicitly disclose a second input port to receive the second Xin element. However, it would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify Boesch to include a second port because doing so is merely duplicating parts. Whether to stream data through a single port or multiple ports is an obvious design choice involving well-known tradeoffs, such as size versus speed.
Regarding claims 9 and 18, taking claim 9 as representative, Boesch discloses the elements of claim 1, as discussed above. Boesch also discloses:
wherein the first Xin element and the second Xin element are values having … bits (Boesch discloses, at ¶ [0237], input values. It is inherent that an input value has a bit size.).
Boesch does not explicitly disclose the number of bits of the inputs is fewer than the number of bits of the first multiplication result and the second multiplication result. However, it would have been obvious to a person having ordinary skill in the art prior to the time of invention to modify Boesch such that the inputs of a multiplication have fewer bits than the product because it is impossible to represent the full range of possible products otherwise and imposing such size limitations would decrease the utility of the system.
Regarding claims 10 and 19, taking claim 10 as representative, Boesch discloses the elements of claim 9, as discussed above. Boesch also discloses:
wherein the first Xin element and the second Xin element are … values and the first multiplication result and the second multiplication result are … values (Boesch discloses, at ¶ [0237], input values and result values. It is inherent that the values each have a bit size.).
Boesch does not explicitly disclose the input size is 8-bit and result size is16-bit. However, it would have been obvious to a person having ordinary skill in the art prior to the time of invention to modify Boesch such that the respective sizes are 8-bits and 16-bits because these are two of the most commonly used sizes to represent data and Boesch discloses both 8-bit and 16-bit values. See, e.g., ¶ [0287].
Regarding claim 15, Boesch discloses the elements of claim 13, as discussed above. Boesch also discloses:
outputting the first Yout element via a first output port of the PE… (Boesch discloses, at ¶ [0231], an interface to output data.).
Boesch does not explicitly disclose outputting the second Yout element via a second output port of the PE. However, it would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify Boesch to include a second port because doing so is merely duplicating parts. Whether to stream data through a single port or multiple ports is an obvious design choice involving well-known tradeoffs, such as size versus speed.
Regarding claims 21 and 22, taking claim 21 as representative, Boesch discloses the elements of claim 1, as discussed above. Boesch also discloses:
Boesch does not explicitly disclose wherein the first Xin element and the second Xin element are sequential elements from an input data set.
However, in the same field of endeavor (e.g., neural network processing) Yan discloses:
multiplying sequential inputs (Yan discloses, at ¶ [0046], multiplied sequential input values A1-A6.).
It would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify Boesch to include multiplying sequential inputs, as disclosed by Yan, in order to improve performance by increasing efficiency with regard to data movement.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Boesch in view of Bittner in view of Yan in view of US Publication No. 2018/0032859 by Park et al. (hereinafter referred to as “Park”).
Regarding claim 17, Boesch discloses the elements of claim 11, as discussed above. Boesch does not explicitly disclose outputting the first Xin element as a first Xout element at a first output port of the PE; and outputting the second Xin element as a second Xout element at a second output port of the PE..
However, in the same field of endeavor (e.g., neural network processing) Park discloses:
a first output port to output the first Xin element as a first Xout element (Park discloses, at Figure 8, transferring input data to another PE.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Boesch to include transferring input data to another PE, as taught by Park, in order to improve performance by increasing data reuse. See Park, ¶ [0009].
It would have been obvious prior to the time of invention to a person having ordinary skill in the art to modify the combination of Boesch and Park to include a second output port to output the second Xin element as a second Xout element because doing so is merely duplicating parts. Whether to stream data through a single port or multiple ports is an obvious design choice involving well-known tradeoffs, such as size versus speed.
Response to Arguments
On page 7 of the response filed February 17, 2021 (“response”), the Applicant argues that the drawing objections are overcome because claims 9 and 10 are cancelled.
The claim listing does not show claims 9 and 10 as cancelled. Nevertheless, the Examiner has withdrawn the drawing objections based on further consideration. The Examiner has proceeded as though claims 9 and 10 are still pending. If it is the Applicant’s intention to cancel the claims, please reflect the cancellation in any subsequent claim listings.
On pages 10-11 of the response the Applicant argues, “The Examiner asserts that Boesch's disclosure of reusing feature maps data for multiple MACs teaches the claimed limitation of a PE configured to use "a single weight value from the weight register ... applied simultaneously to distinct inputs". Applicant respectfully traverses this rejection. There is a fundamental technical distinction between feature reuse (taught by Boesch) and weight reuse (recited in the amended claims). In convolutional neural networks (CNNs), an operation typically involves multiplying inputs (features) by weights (kernels). With respect to feature reuse (Boesch), paragraph [0236] of Boesch states: "The overlapping, column based calculation of the MAC operations allows an acceptably optimal reuse of the feature maps data for multiple MACs". When a feature (input pixel) is reused across multiple MACs, it is typically multiplied by different weights (different kernels) to generate different output channels. With respect to weight reuse (Applicant's invention), the amended claims recite using a "single weight value" applied simultaneously to "distinct inputs" (e.g., XIN1 and XIN2). This is the inverse of Boesch. Applicant's PE holds a weight stationary and broadcasts it to multiple multipliers operating on different features. If Boesch is reusing a single feature map across multiple MACs as stated in paragraph [0236], those MACs must be applying different kernel values to that single feature to produce valid convolution results. Therefore, Boesch does not teach using a single weight value for multiple operations. Instead, it teaches using a single input value for multiple operations. Structural Evidence in Boesch Contradicts the Rejection The hardware architecture disclosed in Boesch provides structural evidence that it does not share a single weight register across multiple multipliers as claimed. FIG. 6B of Boesch clearly labels the connection between the "Kernel Buffer" (616) and the "36 x 16x16BIT MACs" (620) with the text: "36 READ PORTS". Furthermore, paragraph [0237] confirms: "A register based kernel buffer provides a plurality (e.g., up to 36 read ports)...". If Boesch were configured to share a single weight value across multiple multipliers (e.g., sharing 1 weight between 2 distinct inputs as claimed), the hardware would not require a 1:1 ratio of read ports to MAC units. The specific provision of 36 separate read ports for 36 MAC units indicates that Boesch is designed to fetch a unique weight value for every MAC operation in a given clock cycle. This architecture supports "feature reuse" (broadcasting one feature to 36 MACs, each reading a different weight from one of the 36 ports), but it structurally precludes the efficient "weight reuse" claimed by Applicant, where a single weight register feeds multiple multipliers.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive in part. The Examiner agrees that feature reuse and weight reuse are not the same. Systems can use one or the other or both. Doing so generally improves performance by reducing bandwidth and power consumption associated with unnecessary data movement.
As noted by the Applicant, Boesch explicitly discloses feature (input) reuse. See, e.g., ¶ [0151]. The Examiner concedes that it is less clear that Boesch also discloses reusing weights as recited in Applicant’s amended claims, i.e., one weight value is simultaneously fed to two multipliers that simultaneously multiply the weight value by sequential input values. Accordingly, new grounds of rejection are presented above.
Yan discloses both input and weight reuse. At ¶ [0036], Yan discloses inputs are held in a set of PEs for multiple cycles. This discloses input (feature) reuse. Yan also discloses, at ¶ [0046], that in a given cycle the same weight W1 value is multiplied by each of a set of sequential input values A1-A6. This discloses weight reuse, i.e., the same weight value is used for multiple concurrent multiplications. Then in the next cycle, new weight values are loaded and multiplied with the previously loaded input. The Examiner maintains that the combination of references teaches all limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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