DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan (US 20240329539).
Tan is directed to methods of improving dry development performing of metal-containing resists. Tan discloses this method can be applied as a post apply bake (PAB) or a post exposure bake (PEB). (Para, 0030-0031). Tan discloses EUV lithography makes use of EUV resists that are patterned to form masks for use in etching underlying layers. (Para, 0024). Tan discloses EUV resists may be polymer-based chemically amplified resists (CARs) produced by liquid-based spin-on techniques and as an alternative directly photopatternable metal oxide-containing films may be used. (Para, 0024). Tan discloses such films may be produced by spin-on techniques or dry vapor-deposited. (Para, 0024). Tan discloses the metal oxide-containing film can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum ambient providing sub-30 nm patterning resolution. (Para, 0024). Tan discloses Generally, the patterning involves exposure of the EUV resist with EUV radiation to form a photo pattern in the resist, followed by development to remove a portion of the resist according to the photo pattern to form the mask. (Para, 0024). These disclosures teach and/or suggest the limitation of claim 5.
Tan discloses in the case of post-application processing (e.g., PAB), a thermal process with control of one or more of temperature, gas ambient (e.g., using one or more of the gases described herein), pressure, and moisture can be used after deposition and before exposure to change the composition of unexposed metal and/or metal oxide-containing photoresist. (Para, 0031). Tan discloses the change can increase the EUV sensitivity of the material and thus lower dose to size and line edge roughness can be achieved after exposure and dry development. (Para, 0031). Tan also discloses the PAB and/or PEB treatments may be conducted with gas ambient flow in the range of 100-10,000 sccm. (Para, 0038). Tan discloses in these or other embodiments, the moisture content in the ambient environment may be controlled between about a few percent up to 100% (e.g., in some cases between about 20%-50%). (Para, 0038). These disclosures teach and/or suggest the limitation of claims 6-8 and 16-17 and contemplate the limitation of claims 10.
Tan discloses a first embodiment for a post apply bake (PAB). Tan discloses a method 100 involves, at block 101, providing in a process chamber a metal-containing photoresist on a substrate layer of a semiconductor substrate. (Para, 0040; Fig.1). This disclosure teaches and/or suggests the limitation of claim 1, ‘ A manufacturing method of a semiconductor element, the manufacturing method comprising: providing a photoresist on a wafer…’ This disclosure also teaches and/or suggests the limitation of claim 19, ‘A manufacturing method of a semiconductor element, the manufacturing method comprising: providing a photoresist on a wafer…’ Tan discloses then next at block 103, the metal-containing photoresist is treated to modify material properties of the metal-containing photoresist such that etch selectivity in a subsequent post-exposure dry development process is increased. (Para, 0040; Fig.1). Tan discloses the treatment may result in increased cross-linking in the metal-containing photoresist. (Para, 0040; Fig.1).
Tan discloses in some embodiments, the treatment may involve a thermal process with control of temperature, gas ambient, and/or moisture. (Para, 0041). Tan also discloses the apparatus for heat treating the metal-containing EUV photoresist includes a process chamber comprising a substrate support, where the substrate support is configured to support a semiconductor substrate comprising a substrate layer and a metal-containing EUV photoresist positioned over the substrate layer, a process gas source connected with the process chamber and associated gas-flow control hardware, a substrate thermal control hardware, and a controller. (Para, 0010). These disclosures and the disclosures of Tan as discussed above teach and/or suggest the limitation of claims 11-14 and 18. These disclosures and the disclosures of Tan as discussed above, also teach and/or suggest the limitation of claim 19, ‘A manufacturing method of a semiconductor element, the manufacturing method comprising: … wherein, in the performing of the first bake process, a sum of the first flow rate of the first gas and the second flow rate of the second gas supplied to the bake chamber is reduced to be less than a predetermined reference flow rate, and a gas inside the bake chamber is not exhausted.’
Tan discloses the controller is configured with instructions for performing the following operations: expose the metal-containing EUV photoresist to a first elevated temperature in an oxygen-containing environment in the process chamber, and expose the metal-containing EUV photoresist to a second elevated temperature in an inert gas environment, wherein the second elevated temperature is greater than the first elevated temperature. (Para, 0010). These disclosures teach and/or suggest the limitation of claim 3.
Tan discloses the gas ambient may include a reactive gas species such as air, water (H2O), hydrogen (H2), oxygen (O2), ozone (O3), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), carbonyl sulfide (COS), sulfur dioxide (SO2), chlorine (Cl2), ammonia (NH3), nitrous oxide (N2O), nitric oxide (NO), methane (CH4), methylamine (CH3NH2), dimethylamine ((CH3)2NH), trimethylamine (N(CH3)3), ethylamine (CH3CH2NH2), diethylamine ((CH3CH2)2NH), triethylamine (N(CH2CH3)3), pyridine (C5H5N), alcohols (CnH2n+1OH, including but not limited to methanol, ethanol, propanol, and butanol), acetyl acetone (CH3COCH2COCH3), formic acid (HCOOH), oxalyl chloride ((COCl)2), carboxylic acids (CnH2n+1COOH), and other small molecule amines (NR1R2R3, where each of R1, R2, and R3 is independently selected from hydrogen, hydroxyl, aliphatic, haloaliphatic, haloheteroaliphatic, heteroaliphatic, aromatic, aliphatic-aromatic, heteroaliphatic-aromatic, or any combinations thereof), etc. (Para, 0041). Tan discloses substituted forms of any of these reactive gases may also be used and in some cases, the substrate may be exposed to two or more reactive gases during a treatment operation. (Para, 0041). Tan discloses in embodiments where a reactive gas is used to treat the photoresist, the reactive gas may interact with the photoresist via oxidation, coordination, or acid/base chemistry. (Para, 0042). These disclosures teach and/or suggest the limitation of claim 1, ‘A manufacturing method of a semiconductor element: …supplying a first gas, containing oxygen, at a first flow rate to a bake chamber such that oxygen solubility of the photoresist becomes saturated…’ Moreover, these disclosures teach and/or suggest the limitation of claim 19, ‘ A manufacturing method of a semiconductor element, the manufacturing method comprising: … supplying a first gas, containing oxygen, at a first flow rate to a bake chamber…’
Tan discloses in various embodiments, the gas ambient may include an inert gas such as nitrogen (N2), argon (Ar), helium (He), neon (Ne), krypton (Kr), xenon (Xe), etc. (Para, 0043). This disclosure teaches and/or suggests the limitation of claim 1, ‘A manufacturing method of semiconductor element: …and supplying a second gas, which is oxygen-free, at a second flow rate to the bake chamber…’ This disclosure also teaches and/or suggests the limitation of claim 19, ‘A manufacturing method of a semiconductor element, the manufacturing method comprising: …and supplying a second gas, which is oxygen-free, at a second flow rate to the bake chamber…’ Tan discloses in some cases, the inert gas may be provided together with one or more of the reactive gases listed above. (Para, 0043). This disclosure teaches and/or suggest the limitation of claim 4. Tan discloses the embodiments described herein may include a reduction step, which may operate to reduce oxidized or over-oxidized areas of the photoresist. (Para, 0044). Tan explains, a reduction step may be particularly useful after a step that oxidizes the photoresist (or portions thereof) and this may involve exposing the substrate to a reducing atmosphere or an inert atmosphere. (Para, 0044). Tan discloses the reduction step may involve heating the substrate and/or exposing the substrate to plasma which may be generated from inert gas and/or reducing gas. (Para, 0044).
Tan discloses in various embodiments, the treatment may be applied after the photoresist 202a has been applied to the substrate 201, before the photoresist 202a is exposed to patterning radiation. (Para, 0045; Fig.2). Tan explains in one example where the treatment is a thermal treatment, the treatment may be referred to as a post-application bake (PAB). (Para, 0045). Tan further explains, the treatment alters the photoresist 202a to form a modified version of the photoresist 202b and as comparted to the photoresist 202a prior to treatment, the modified version of the photoresist 202b exhibits improved properties. (Para, 0045). Tan discloses the modified version of the photoresist 202b may be more sensitive to EUV radiation than the unmodified version of the photoresist 202a, and as a result of this increased EUV sensitivity, the modified version of the photoresist may exhibit lower dose to size during EUV exposure, and may provide lower line edge roughness after development. (Para, 0045). These disclosures teach and/or suggest the limitation of claim 1, ‘ A manufacturing method of a semiconductor element: …and performing a bake process on the wafer in the bake chamber.’ These disclosures also teach and/or suggest the limitiaotn of claim 19, ‘A manufacturing method of a semiconductor element, the manufacturing method comprising: …and performing a first bake process on the wafer in the bake chamber...’
Tan discloses in some embodiments, multiple treatments may be used with a first treatment may occur after photoresist deposition and prior to EUV exposure, and a second treatment may occur after EUV exposure and prior to development. (Para, 0050; Fig. 2-3). Tan also discloses that one or more of the processing conditions may be controlled as described herein during the first treatment and/or during the second treatment. (Para, 0050). These disclosures teach and/or suggest the limitations of claim 20.
Tan goes on to also discloses a PEB process. Tan discloses in the case of post-exposure processing (e.g., PEB), a thermal process with the control of one or more of temperature, gas atmosphere (e.g., using one or more of the gases described herein), pressure, and moisture can be used to change the composition of both unexposed and exposed photoresist. (Para, 0032). Tan explains, one or multiple processes may be applied to modify photoresist itself to increase dry development selectivity and this thermal and/or radical modification can increase the contrast between unexposed and exposed material and thus increase the selectivity of the subsequent dry development step. (Para, 0034). Tan discloses the resulting difference between the material properties of unexposed and exposed material can be tuned by adjusting one or more process conditions including temperature, gas flow, moisture, pressure, and/or RF power. (Para, 0034). Tan discloses the selectivity achieved for a given EUV dose with a 220° C. to 250° C. PEB thermal treatment in air at about 20% humidity for about 2 minutes can be made similar to that for about a 30% higher EUV dose with no such thermal treatment. (Para, 0039).
Tan discloses a photoresist on a substrate may undergo multiple PEB treatments or multiple steps in a PEB treatment process and the multiple bake steps may be performed at different temperatures and/or different chemistries. (Para, 0052). Tan discloses a first bake step may be performed at a moderately elevated bake temperature in an oxygen-rich environment and a second bake step may be performed at a highly elevated bake temperature greater than the moderately elevated bake temperature and in an inert environment. (Para, 0052). Tan discloses a moderately elevated bake temperature may be between about 150° C. and about 220° C. and the highly elevated bake temperature may be between about 220° C. and about 250° C. (Para, 0052). Tan discloses exposing a metal-containing photoresist to the first bake step and the second bake step in sequence, material contrast is improved for achieving higher etch selectivity during dry development. (Para, 0052).
Tan discloses at block 401 of the process 400, a substrate is provided in a process chamber, where the substrate is a semiconductor substrate having a metal-containing photoresist on a substrate layer of the semiconductor substrate. (Para, 0054). Tan discloses the metal-containing photoresist may be dry or wet deposited on the substrate layer. (Para, 0054). Tan also discloses the metal-containing photoresist may be provided as a positive tone or negative tone resist having EUV-exposed and EUV-unexposed regions after EUV exposure. (Para, 0054). Tan explains, after exposure and an optional PEB treatment, the metal-containing photoresist may undergo development to selectively remove portions (e.g., EUV-unexposed portions) of the metal-containing photoresist to form a patterned mask over the substrate layer. (Para, 0054). Tan also discloses in some implementations, the process 400 further includes exposing the metal-containing EUV photoresist to EUV radiation prior to providing the substrate in the process chamber in order to form the EUV-exposed regions and the EUV-unexposed regions. (Para, 0054). These disclosures and the disclosures of Tan as discussed above teach and/or suggest the limitation of claim 9, ‘ A manufacturing method of a semiconductor element, the manufacturing method comprising: performing an exposure process in which a wafer is exposed at an exposure amount of 55mJ to 60mJ… loading the wafer into the bake chamber after performing the exposure process…’
Tan discloses after photopatterning, the metal-containing photoresist is thermally treated or baked in a post-exposure bake (PEB) operation which creates greater chemical contrast for development. (Para, 0056). Tan explains that rather than performing a single bake operation, PEB treatment may proceed in a two-step or multi-step bake operation, where each step subjects the metal-containing photoresist to different treatment conditions such as: identity and concentration of ambient gases or mixtures proximate the substrate, moisture level, temperatures, pressures, etc. (Para, 0056). These disclosures teach and/or suggest the Tan discloses the metal-containing photoresist is exposed to a first elevated temperature in an oxygen-containing environment in the process chamber, which provides a low to medium temperature bake. (Para, 0057). Tan discloses the oxygen-containing environment may facilitate incorporation of oxygen into exposed portions of the metal-containing photoresist with higher oxygen concentration generally leads to higher oxygen incorporation. (Para, 0057). Tan discloses, the oxygen-containing environment includes oxygen (O2), ozone (O3), water (H2O), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), or combinations thereof. (Para, 0057). Tan discloses the presence of oxygen-containing species (e.g., O2, O3, etc.) generally leads to increased material contrast between exposed and unexposed portions of the metal-containing photoresist. (Para, 0059). These disclosures teach and/or suggest the limitation of claim 9, ‘ A manufacturing method of a semiconductor element, the manufacturing method comprising: …supplying a first gas, containing oxygen, at a first flow rate to a bake chamber…’ and the limitation of claim 15.
Tan discloses that moisture level in the process chamber can be tuned during exposure to the oxygen-containing environment to optimize PEB treatment. In some cases, increased moisture leads to line CD decrease or other adverse outcomes. (Para, 0062). Tan discloses that increased humidity levels suppress crosslinking in exposed portions of the metal-containing photoresist, thereby lowering material contrast. (Para, 0062). Tan explains, the moisture level in the process chamber is minimized and the process chamber is free or substantially free of moisture. (Para, 0062).
Tan discloses at block 405 of the process 400, the metal-containing photoresist is exposed to a second elevated temperature in an inert gas environment, where the second elevated temperature is greater than the first elevated temperature. (Para, 0066). Tan discloses exposure to the inert gas environment may occur in the same process chamber or a different process chamber than exposure to the oxygen-containing environment. (Para, 0066). Tan discloses the second elevated temperature provides a high temperature bake that provides sufficient thermal energy to promote crosslinking in the exposed portions of the metal-containing photoresist. (Para, 0066). Tan discloses in some implementations, the second elevated temperature is between about 220° C. and about 300° C., or between about 220° C. and about 250° C. (Para, 0066). Tan discloses the inert gas environment is free or substantially free of oxygen-containing species to avoid over-oxidation of unexposed portions of the metal-containing photoresist. (Para, 0066). Tan explains in some implementations, the inert gas environment includes nitrogen (N.sub.2), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), or combinations thereof. (Para, 0066). These disclosures teach and/or suggest the limitation of claim 9, ‘A manufacturing method of a semiconductor element, the manufacturing method comprising: … and supplying a second gas, which is oxygen-free, at a second flow rate to the bake chamber…’
Tan explains that overall, performing the sequence of the first bake followed by the second bake improves PEB treatment performance compared to a single bake operation. (Para, 0073). Tan discloses performing the first bake and the second bake improves etch contrast for improved etch selectivity between EUV-exposed portions and EUV-unexposed portions in a subsequent dry development process and can reduce line edge roughness and reduce dose to size in the subsequent dry development process. (Para, 0073). These disclosures teach and/or suggest the limitation of claim 9, ‘ A manufacturing method of a semiconductor element, the manufacturing method comprising: …and performing a development process on the wafer after performing the bake process.’
While the recitations of claims 1-20 are not exactly and/or identically disclosed by Tan, one of ordinary skill in the art would have a reasonable expectation to successfully form a pattern in a resist on a substrate, where the substrate and/or environment in which the substrate is contained is treated to increase etch contrast which results in improved pattern development, reduces the likelihood of forming residues in unexposed portions, reduces line edge roughness, and reduces defectivity so the developed pattern is formed more accurately and results in the formation of a patterning mask that can be used to fabricate a semiconductor device.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899