DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 18, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 16, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Device With Decreased RC Delay
Election/Restrictions
Applicant’s election without traverse of device embodiment 1 (Figs. 3, 38-39, Claims 1-20) in the reply filed on February 27, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the gate electrode structures" in line 1. There is insufficient antecedent basis for this limitation in the claim. For purpose of examination his will be interpreted as “the gate electrodes”
Allowable Subject Matter
Claims 1-18 and 20 are allowed. Note: Claim 19 would be allowable if rewritten to overcome the 112 rejection above.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Koh (US 2022/0093630), Yun (US 2019/0326319), Lee (US 2018/0247953), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-12 depend), a first division pattern extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction… wherein a first gate electrode among the gate electrodes is commonly connected to the first through via and the second through via.
Regarding Claim 13 (from which claims 14-16 depend), division patterns on the CSP, each of the division patterns extending through the gate electrode structure in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction… wherein a first gate electrode among the gate electrodes is commonly connected to the first through via and the second through via.
Regarding Claim 17 (from which claims 18-20 depend), division patterns on the third region of the substrate, each of the division patterns extending through the gate electrode structure in a third direction that substantially parallel to the upper surface of the substrate and that crosses the second direction… wherein a first gate electrode among the gate electrodes is commonly connected to the first through via and the second through via…
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Koh (US 2022/0093630) discloses (Figs. 29 and 31) a semiconductor device, comprising: a lower circuit pattern (142) on a substrate (100); a common source plate (CSP) (240) on the lower circuit pattern (142); a gate electrode structure (752/754/756) comprising gate electrodes (752-756) spaced apart from each other on the CSP in a first direction (D1) that is substantially perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction (D2) that is substantially parallel to the upper surface of the substrate; a first insulation pattern structure (600) on a portion of the CSP that is adjacent to the gate electrode structure in the second direction; a first division pattern (330) extending on the CSP in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction, the first division pattern extending through a portion of the gate electrode structure (330 extends through 752/754/756) that is adjacent to the first insulation pattern structure and separating the gate electrode structure in the second direction; a channel (410) extending through the gate electrode structure in the first direction, the channel being connected to the CSP (410 is connected to 240); a first through via (left 650) extending through the CSP and the gate electrode structure in the first direction, the first through via being electrically connected to the lower circuit pattern; and a second through via (right 650) extending through the CSP and the first insulation pattern structure in the first direction, the second through via being electrically connected to the lower circuit pattern. Koh does not disclose wherein a first gate electrode among the gate electrodes is commonly connected to the first through via and the second through via.
Yun (US 2019/0326319) discloses (Fig. 14) an insulation pattern 471 adjacent to gate structure St and through vias PCP connected to circuit TR. Yun does not disclose division patterns on the CSP, each of the division patterns extending through the gate electrode structure in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction… wherein a first gate electrode among the gate electrodes is commonly connected to the first through via and the second through via.
Lee (US 2018/0247953) discloses (Fig. 4) a lower circuit LS on a substrate 101, a CSP 141, a gate electrode structure CS, a first insulation pattern structure 187 adjacent to gate electrode structure CS, a channel CPL, first and second through vias 193B extending through the CSP 141 and connecting to LS. Lee does not disclose division patterns on the CSP, each of the division patterns extending through the gate electrode structure in a third direction that is substantially parallel to the upper surface of the substrate and that crosses the second direction… wherein a first gate electrode among the gate electrodes is commonly connected to the first through via and the second through via.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/G.G.R/Examiner, Art Unit 2812
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