DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application filed on 6/16/2023 and IDS filed on 6/16/2023 and 4/30/2024. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung et al. (US Patent Application Publication No. 2006/0277509 A1) in view of .Oh et al. (US Patent No. 10,867,091 B1).
As per claim 19, Fig. 12 illustrates the elements of the claims, wherein for each sampling window (150, 190, 160, 170, 180, 197, 198), the power calculation is based on the activity/events (i.e., transition activity log) from simulation data (see also paragraphs [0086][0095]) using power estimation model (see paragraph [0046], [0063]), wherein since Tung et al. is a computer-implemented method/system (see paragraph 0010), the computer readable medium having instructions to implemented this computer-implemented method/system in inherently included, being necessary to carry out the functionalities of the computer-implemented method/system as is known in the art of computer-aided design and analysis of circuits.. However, Tung et al. failed to teach that this power estimation model is generated using ML (machine learning). Such use of ML generated power estimation model is known in the art and is further taught by Oh et al. (see col. 5, line 7 to col. 6, line 67). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention to further incorporate the teachings of Oh et al. into the method/system of Tung et al. because such incorporation would allow for estimating power based on activity as taught by Tung et al. while benefiting from the improved, faster power analysis as fought by Oh et al. (see col. 2, lines 17-23).
As per claim 20, the analysis interface to allow a user to specify activity criteria and return the user power information for windows whose activity satisfy the specified parameters is further taught by Oh et al. (see col. 16, line 33 to col. 17, line 5; col. 19, lines 4-19; col. 18, lines 25-34)--i.e., activity criteria such as particular design to debug, time period for debugging; sampling rate).
Allowable Subject Matter
Claims 1-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
As per claims 1-9, the independent claims 1, from which the respective claims, depend, recites the method comprising a combination of inventive steps/operations dividing one or more RTL (register transfer level) simulation waveform files into a plurality of windows; processing the windows to generate activity and power data, and creating an ML (machine learning) penetrated power estimation model for the partition using the processed windows, which the prior arts made of record failed to teach or suggest as claimed. In particular, Zhu et al. (US Patent No. 8,108,194 B2) teach estimating power consumption of integrated circuit design using emulation data involving dividing each timing window into one or segments, determining power-activity values for the one or more segments, determining power-consumption values for the one or more segments based on the power-activity values, and determining relative power activity across the one or more segments based on the power-activity values and the power-consumption values (see abstract; Fig. 1); Oh et al. (US Patent No. 10,867,091 B1) teach optimizing power consumption of an integrated circuit design by dividing the IC design into N partitions which are supplied to the N computer systems to be trained in parallel using machine learning to reduce power consumption (see abstract; col. 2, lines 15-38); Stephens et al. (US Patent No. 12,560,505 B2) teach calculating gate level clock gating power cost functions based on gate-level activity data to derive clock gating metrics (see Fig. 3; abstract); Sundaresan et al. (US Patent No. 8,452,581 B2) teaches generating of power consumption model based on curve-fitting technique and one or more of a plurality of power consumption parameters (see abstract; Fig. 1); Tung et al. (20060277509 A1) teach analyzing power consumption involving using statistical model (see paragraph [0046]; Fig. 4). However, none of the prior arts made of record, alone or in combination teach or suggest the inventive steps/operations/instructions as claimed. Additionally, per claim 9, the “computer readable storage medium” is defined in Applicant’s specification to be “not a transitory, propagating signal per se”, limiting to patent eligible subject matter (see Applicant’s specification, paragraph [0084]). Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process and an article of manufacture; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
As per claims 10-18, the independent claim 10, from which the claims depend, recites the computer system comprising a combination of inventive operations comprising divide a data set of RTL (register transfer level) functional simulation data for a logical partition into n windows; generate activity and power data for each of the windows; and provide a first portion of the generated activity and power data to an ML (machine learning) training engine to create a power estimation model, as claimed, which the prior arts made of record, alone or in combination failed to teach or suggest. In particular, although, Zhu et al. (US Patent No. 8,108,194 B2) teach estimating power consumption of integrated circuit design using emulation data involving dividing each timing window into one or segments, determining power-activity values for the one or more segments, determining power-consumption values for the one or more segments based on the power-activity values, and determining relative power activity across the one or more segments based on the power-activity values and the power-consumption values (see abstract; Fig. 1), the power activity values are not used for machine learning training to generate a power estimation model as claimed; and although Oh et al. (US Patent No. 10,867,091 B1) teach optimizing power consumption of an integrated circuit design by dividing the IC design into N partitions which are supplied to the N computer systems to be trained in parallel using machine learning to reduce power consumption (see abstract; col. 2, lines 15-38), the machine learning is used to reduce power consumption and does not generate a power estimated model based on the activity and power data as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a machine, respectively; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 September 1, 2026
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