DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 03/17/2026 amendments of claims 1, 5, 9, 12 and 14-15 have been noted and entered.
The 03/17/2026 cancellation of claims 6-7 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 7-10, filed 03/17/2026, with respect to the rejection(s) of claim(s) 1-6 and 8-20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive in view of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Chen et al, US 20230260977 A1 (Chen) and Lee et al, US 20090305502 A1 (Lee).
New Grounds of Rejection
New grounds of rejection, prior art references Chen et al, US 20230260977 A1 (Chen) and Lee et al, US 20090305502 A1 (Lee) appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-5, 8 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Lee et al, US 20090305502 A1 (Lee).
Regarding claim 1; Chen teaches a semiconductor device (Chen: Annotated Fig (12) of Chen shared in this OA: 100) comprising:
a substrate (124) including a first surface (First Surface), on which an active area is formed (area containing 126), and a second surface (Second Surface) opposite to the first surface (First Surface);
an electronic element (126) formed on the active area (area containing 126);
a front wiring structure (130A) disposed on the first surface (First Surface) of the substrate (124) and connected to the electronic element (126);
a trench capacitor (128) filling at least a portion of a back trench (127) extending into the substrate (124) from the second surface (Second Surface) of the substrate (124);
a back wiring structure (130B) disposed on the second surface (Second Surface) of the substrate (124) and connected to the trench capacitor (128);
and a through-via (136) extending through the substrate (124) to connect the electronic element (126) and the back wiring structure (130B) to each other, wherein a width of the through-via decreases as the through-via extends in a direction from the front wiring structure toward the back wiring structure.
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Chen does not teach wherein a width of the through-via decreases as the through-via extends in a direction from the front wiring structure toward the back wiring structure.
However, Lee teaches wherein a width of the through-via (Lee: Annotated Fig (38) shared in this OA: 640) decreases as the through-via extends in a direction from the front wiring structure (Front wiring Structure (160)) toward the back wiring structure (650). Additionally, comparing elements (Fig(4): 140d) to (Fig (38): 640) in combination with paragraph [0004] of the specification of Lee illustrates that it is possible to construct a through via that tapers in either direction of processing.
Chen and Lee are considered analogous art. Thus it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Chen by constructing a through via that tapers from the front wiring structure to the back wiring structure as disclosed in Lee to make establishing an electrical connection between the via and the wiring structure easier leading to a more reliable device production process.
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Regarding claim 2; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 1.
Further, Chen teaches wherein a power voltage is applied to the electronic element via the back wiring structure (Chen: Annotated Fig (12) shared in this OA: 130B; [0041]: “… of interconnect structure 130B to provide a first voltage V1 to doped conductive region 128A and conductive layer 128E...”).
Regarding claim 3; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 2.
Further, Chen teaches wherein the power voltage is applied to the trench capacitor (Chen: Annotated Fig (12) shared in this OA: 128) via the back wiring structure (130B; [0041]).
Regarding claim 4; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 1.
Further, Chen teaches wherein the trench capacitor (Chen: Fig (1B): 128) includes a first electrode film (128E) and a second electrode film (128C) facing each other, and a capacitor dielectric film (128D) interposed between the first electrode film (128E) and the second electrode film (128D).
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Regarding claim 5; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 4.
Further, Chen teaches wherein one of the first electrode film (Chen: Fig (1B): 128E) or the second electrode film (128C) is electrically connected to the electronic element (Annotated Fig (12) shared in this OA: 126).
Regarding claim 8; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 1.
Further, Chen teaches wherein the through-via (Chen: Annotated Fig (12) shared in this OA: 136) connects the front wiring structure (130A) and the back wiring structure (130B) to each other.
Regarding claim 12; Chen teaches a semiconductor device (Chen: Annotated Fig (12) of Chen shared in this OA: 100) comprising:
a substrate (124) including a first surface (First Surface), on which an active area (area containing 126) is formed, and a second surface (Second Surface) opposite to the first surface (First Surface);
a first electronic element (126) formed on the active area (area containing 126);
a first through-via (136) extending through the substrate (124) to be connected to the first electronic element (126);
a trench capacitor (128) filling at least a portion of a back trench (127) extending into the substrate (124) from the second surface (Second Surface) of the substrate (124); and
a back wiring structure (130B) disposed on the second surface (Second Surface) of the substrate (124), wherein the back wiring structure (130B) connects the first through-via (136) and the trench capacitor (128) to each other, wherein a first power voltage ([0041]: “… of interconnect structure 130B to provide a first voltage V1 to doped conductive region 128A and conductive layer 128E...”) is applied to the first electronic element (126) and the trench capacitor (128) via the back wiring structure (130B), and a width of the first through-via decreases as the first through-via extends in a direction from the first surface of the substrate toward the back wiring structure.
Chen does not teach wherein a width of the through-via decreases as the through-via extends in a direction from the front wiring structure toward the back wiring structure.
However, Lee teaches wherein a width of the through-via (Lee: Annotated Fig (38) shared in this OA: 640) decreases as the through-via extends in a direction from the front wiring structure (Front wiring Structure (160)) toward the back wiring structure (650). Additionally, comparing elements (Fig(4): 140d) to (Fig (38): 640) in combination with paragraph [0004] of the specification of Lee illustrates that it is possible to construct a through via that tapers in either direction of processing.
Chen and Lee are considered analogous art. Thus it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Chen by constructing a through via that tapers from the front wiring structure to the back wiring structure as disclosed in Lee to make establishing an electrical connection between the via and the wiring structure easier leading to a more reliable device production process.
Regarding claim 13; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 12.
Further, Chen teaches wherein the trench capacitor (Chen: Fig (1B): 128) includes a first electrode film (128E) and a second electrode film (128C) facing each other, wherein the first power voltage is applied ([0041]) to the first electronic element (126) and the first electrode film (128E) via the back wiring structure (130B).
Regarding claim 14; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 13.
Further, Chen teaches further comprising: a second electronic element (Chen: Annotated Fig (12) shared in this OA: 126) formed on the active area (area on which 126 is formed); and a second through-via (136) extending through the substrate (124) and connected to the second electronic element (126), wherein the back wiring structure (130B) connects the first through-via (136) and the first electrode film (Fig (1B):128E) to each other and connects the second through-via (Annotated Fig (12) shared in this OA: 136) and the second electrode film (Fig (1B): 128C) to each other, wherein a second power voltage different from the first power voltage is applied to the second electronic element (126) and the second electrode film (128C) via the back wiring structure (130B).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Lee et al, US 20090305502 A1 (Lee) in further view of Xie et al, US 20230132353 A1 (Xie).
Regarding claim 9; Chen in view of Lee teaches all the limitations of the semiconductor device of claim 1.
However, Chen in view of Lee does not teach wherein the electronic element includes: an active pattern disposed on the active area; a gate structure intersecting the active pattern; and a source/drain area in the active pattern and disposed adjacent to a side surface of the gate structure, wherein the through-via is connected to the source/drain area.
Xie teaches wherein the electronic element (Xie: Figs (12)-(13): 123) includes: an active pattern disposed on the active area (area containing 123); a gate structure (131) intersecting the active pattern; and a source/drain area (Fig (15): S/D are under 143) in the active pattern and disposed adjacent to a side surface of the gate structure (Figs (12)-(13): 131), wherein the through-via (139) is connected to the source/drain area (Fig (15): S/D area under 143).
Chen in view of Lee and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person with ordinary skill in the art, to modify Chen in view of Lee by constructing the device with the structure details disclosed in Xie to facilitate establishing electrical connections to the different parts of the device making the device manufacturing process more efficient.
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Regarding claim 10; Chen in view of Lee teaches all the limitations of claim 9.
However, Chen in view of Lee does not teach further comprising a source/drain contact disposed on the side surface of the gate structure, wherein the source/drain contact connects the front wiring structure and the source/drain area to each other.
Xie teaches further comprising a source/drain contact (Xie: Fig (15): 143) disposed on the side surface of the gate structure (Fig (12): 131), wherein the source/drain contact (Fig (15): 143) connects the front wiring structure (143) and the source/drain area (S/D area under 143) to each other.
Chen in view of Lee and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person with ordinary skill in the art, to modify Chen in view of Lee by constructing the device with the structure details disclosed in Xie to facilitate establishing electrical connections to the different parts of the device making the device manufacturing process more efficient.
Regarding claim 11; Chen in view of Lee teaches all the limitations of claim 10.
However, Chen in view of Lee does not teach wherein the through-via is connected to the source/drain contact.
Xie teaches wherein the through-via (Xie: Fig (15): 139) is connected to the source/drain contact (143).
Chen in view of Lee and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person with ordinary skill in the art, to modify Chen in view of Lee by constructing the device such that the through-via is connected to the source/drain contact as disclosed in Xie to facilitate establishing electrical connections to the different parts of the device making the device manufacturing process more efficient.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Kishida, US 20130264655 A1 (Kishida) in further view of Lee et al, US 20090305502 A1 (Lee).
Regarding claim 15; Chen teaches a semiconductor device (Chen: Annotated Fig (12) shared in this OA: 100) comprising:
a substrate (124) including a first surface (First Surface), on which a first active area (area containing 126) and a second active area (second area containing 126) are formed, and a second surface (Second Surface) opposite to the first surface (First Surface);
a first electronic element (126) disposed on the first active area (area containing 126) and having a first conductivity type;
a second electronic element (126) disposed on the second active area (second area containing 126) and having a second conductivity type different from the first conductivity type;
a front wiring structure (130A) disposed on the first surface (First Surface) of the substrate (124), and connected to the first electronic element (126) and the second electronic element (126);
a first through-via (136) extending through the substrate (136) and connected to the first electronic element (126);
a second through-via (136) extending through the substrate (124) and connected to the second electronic element (126);
a trench capacitor (128) filling at least a portion of a back trench (127) extending into the substrate (124) from the second surface (Second Surface) of the substrate, wherein the trench capacitor (128) includes a first electrode film (Fig (1B): 128E) and a second electrode film (128C) facing each other; and
a back wiring structure (130B) disposed on the second surface (Second Surface) of the substrate (124), wherein the back wiring structure (130B) connects the first through-via (Annotated Fig (12) shared in this OA): 136) and the first electrode film (Fig (1B): 128E) to each other and connect the second through-via (Annotated Fig (12) shared in this OA): 136) and the second electrode film (Fig (1B): 128C) to each other, wherein a width of the first through-via decreases as the first through-via extends in a direction from the front wiring structure toward the back wiring structure.
Chen does not teach the first electronic element having a first conductivity type, and the second electronic element having a second conductivity type different from the first conductivity type.
However, Kishida teaches the first electronic element having a first conductivity type, and the second electronic element having a second conductivity type different from the first conductivity type (Kishida: [0016]: “… constituting a first transistor of a first conductivity type on the first active region…” and “…constituting a second transistor of a second conductivity type formed on the second active region…”, claim 10).
Chen and Kishida are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen by introducing the first and second conductivity type structures on the first and second active regions respectively as disclosed in Kishida to improve the connectivity of the different parts of the device leading to a more efficient device.
Chen in view of Kishida does not teach wherein a width of the through-via decreases as the through-via extends in a direction from the front wiring structure toward the back wiring structure.
However, Lee teaches wherein a width of the through-via (Lee: Annotated Fig (38) shared in this OA: 640) decreases as the through-via extends in a direction from the front wiring structure (Front wiring Structure (160)) toward the back wiring structure (650). Additionally, comparing elements (Fig(4): 140d) to (Fig (38): 640) in combination with paragraph [0004] of the specification of Lee illustrates that it is possible to construct a through via that tapers in either direction of processing.
Chen in view of Kishida and Lee are considered analogous art. Thus it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art to modify Chen in view of Kishida by constructing a through via that tapers from the front wiring structure to the back wiring structure as disclosed in Lee to make establishing an electrical connection between the via and the wiring structure easier leading to a more reliable device production process.
Regarding claim 16; Chen in view of Kishida in further view of Lee teaches all the limitations of the semiconductor device of claim 15.
Further, Chen teaches wherein a first power voltage is applied to the first electronic element (Chen: Annotated Fig (12) shared in this OA: 126) and the first electrode film (Fig (1B): 128E), and wherein a second power voltage different from the first power voltage ([0041]) is applied to the second electronic element (Chen: Annotated Fig (12) shared in this OA: 126) and the second electrode film (128C).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Kishida, US 20130264655 A1 (Kishida) in further view of Lee et al, US 20090305502 A1 (Lee) in further view of Xie et al, US 20230132353 A1 (Xie).
Regarding claim 17; Chen in view Kishida in further view of Lee teaches all the limitations of the semiconductor device of claim 15.
However, Chen in view of Kishida in further view of Lee does not teach wherein each of the first through-via and the second through-via includes a through-conductive film and a through-spacer at least partially surrounding a side surface of the through-conductive film.
Xie teaches wherein each of the first through-via (Xie: Fig (15): 139) and the second through-via (139) includes a through-conductive film and a through-spacer at least partially surrounding a side surface of the through-conductive film ([0033]).
Chen in view of Kishida in further view of Lee and Xie are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Kishida in further view of Lee by constructing the through vias such that they have a conductive spacer layer surrounding a core conductive layer as disclosed in Xie to prevent the core layer atoms from migrating through the semiconductor device layers causing electrical short circuits and contamination. Such a measure is bound to lead to a more reliable device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Kishida, US 20130264655 A1 (Kishida) in further view of Lee et al, US 20090305502 A1 (Lee) in further view of Hu et al, US 20220208958 A1 (Hu).
Regarding claim 18; Chen in view of Kishida in further view of Lee teaches all the limitations of the semiconductor device of claim 15.
However, Chen in view of Kishida in further view of Lee does not teach wherein a depth of the back trench is about 50% or greater of a thickness of the substrate.
Hu teaches wherein a depth of the back trench (Hu: Fig (1A): 102a or 102b) is about 50% or greater of a thickness of the substrate (100; [0023]: “…, a first depth D1 of each of the first trenches 102a and a second depth D2 of each of the second trenches 102b may be greater than half of a thickness of the substrate 100,…”).
Chen in view of Kishida in further view of Lee and Hu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Kishida in further view of Lee by making the depth of the trenches more than half the thickness of the substrate as disclosed in Hu to improve their capacitance and performance in the device leading to a more efficient and more reliable device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Kishida, US 20130264655 A1 (Kishida) in further view of Lee et al, US 20090305502 A1 (Lee) in further view of Cheng, US 20220037510 A1 (Cheng).
Regarding claim 20; Chen in view of Kishida in further view of Lee teach all the limitations of the semiconductor device of claim 15.
However, Chen in view of Kishida in further view of Lee does not teach wherein a width of each of the first through-via and the second through-via is in a range of about 10 nm to about 100 nm.
Cheng teaches wherein a width of each of the first through-via and the second through-via is in a range of about 10 nm to about 100 nm (Cheng: [0030]).
Chen in view of Kishida in further view of Lee and Cheng are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Kishida in further view of Lee by making the width of the vias in the range disclosed in Cheng to make the overlaying of the different components easier while reducing the size of the device which leads to a reduced cost of production and higher performance of the device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20230260977 A1 (Chen) in view of Kishida, US 20130264655 A1 (Kishida) in further view of Lee et al, US 20090305502 A1 (Lee) in further view of Hu et al, US 20220208958 A1 (Hu) in further view of Lin et al, US 20220367323 A1 (Lin).
Regarding claim 19; Chen in view of Kishida in further view of Lee in further view of Hu teach all the limitations of the semiconductor device of claim 18.
However, Chen in view of Kishida in further view of Lee in further view of Hu does not teach wherein the thickness of the substrate is in a range of about 150 nm to about 700 nm.
Lin teaches wherein the thickness of the substrate is in a range of about 150 nm to about 700 nm (Lin [0023]).
Chen in view of Kishida in further view of Lee in further view of Hu and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen in view of Kishida in further view of Lee in further view of Hu by using a substrate with a thickness of the range disclosed in Lin to ensure that there is enough space for constructing the needed elements of the circuit and thus leading to a more reliable device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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