Notice of Pre-AIA or AIA
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 and 12-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-3 each recite “a first [second] portion of the dielectric stack above [below] the active region,” respectively. There is no antecedent basis for “the dielectric stack above [below] the active device region.” Examiner is interpreting the claims to make reference to a first [second] portion of the dielectric stack, wherein the first [second] portions are above and below the active device region, respectively.
Claims 12-13 each contain analogous limitations as those described for claims 2-3 above. Claims 12-13 are rejected as indefinite for those same reasons.
Claims 13-14 and 16-18 each recite “the second monolithic crack stop.” Claims on which they depend provide basis for “ a second continuous crack stop” [emphasis added]. Examiner is interpreting the recited “second monolithic crack stop” to refer to the same limitation as the “second continuous crack stop”.
Claim 15 recites “the crack stop”, while no antecedent basis is provided in claim 11. It is unclear whether this refers to the first segmented crack stop or to the second continuous crack stop recited in claim 11. This level of indefiniteness is sufficient to preclude examination of claim 15, and as such claim 15 is not being treated on its merits in this office action.
Claim 18 additionally recites “the first dielectric stack”, while claim 11 gives basis to “a dielectric stack”. Examiner is interpreting the first dielectric stack to be the same limitation as the dielectric stack.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20220223625 (Chiang).
As to Claim 1, Chiang teaches a semiconductor device comprising:
a back end of line (BEOL) stack including
a dielectric stack (Fig 1A 140+108), and
an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures (Fig 1A shows transistors in active device region within dielectric stack); and
a crack stop that extends vertically through the active device region (114+142 vertically through active device region).
As to Claim 2, Chiang teaches the semiconductor device of claim 1, wherein the crack stop also extends vertically through a first portion of the dielectric stack above the active device region (142 in claimed portion).
As to Claim 3, Chiang teaches the semiconductor device according to claim 2, wherein the crack stop also extends through a second portion of the dielectric stack below the active device region (114 in claimed portion).
As to Claim 4, Chiang teaches the semiconductor device of claim 2, further comprising a substrate, the BEOL stack provided on the substrate, wherein the crack stop extends entirely though the dielectric stack and through at least a portion of the substrate (substrate 106 with 114 running through).
As to Claim 6, Chiang teaches the semiconductor device according to claim 1, wherein the crack stop comprises at least one material selected from the group consisting of copper, aluminum, tungsten, 2-(trimethylsilyl)ethoxycarbonyl (TEOC), and a dielectric material (114 may comprise copper ¶0035).
As to Claim 7, Chiang teaches the semiconductor device according to claim 1, wherein the crack stop includes a liner layer (liner layer 112).
As to Claim 8, Chiang teaches the semiconductor device according to claim 1, further comprising:
a substrate (106); and
a heat sink on a bottom side of the substrate (104 may reasonably be interpreted to be a heat sink),
wherein the crack stop extends entirely though the dielectric stack and the substrate to contact the heat sink (114 extends through stack and 106 contacting 104).
As to Claim 9, Chiang teaches the semiconductor device according to claim 1, further comprising an active prime region, wherein the crack stop surrounds the active prime region (Fig 1B shows crack stop structure surrounding active region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 10-14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang and US 20150325531 (Dyer).
As to Claim 5, Chiang teaches the semiconductor device of claim 1, but fails to explicitly teach a second crack stop that surrounds the first crack stop
Dyer teaches a similar structure as Chiang, explicitly having different geometric arrangements in which an outer crack stop surrounds an inner crack stop (Fig 17, inner/outer portions of 130)
All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
As to Claim 10, Chiang teaches the semiconductor device according to claim 1, but fails to explicitly teach a guard rail formed between the crack stop and the active prime region (Chiang explicitly teaches one crack stop, and also teaches the structure 114 may be considered a guard ring ¶0021).
Dyer teaches similar structure as Chiang, explicitly having different geometric arrangements in which a guard rail is between a crack stop and active prime region (Fig 17, inner/outer portions of 130.).
It would have been obvious, for the same reasons as those outlined in the claim 5 rejection, to combine the teachings of Chiang and Dyer.
As to Claim 11, Chiang teaches a semiconductor device comprising:
a back end of line (BEOL) stack including
a dielectric stack (Fig 1A 140+108),
an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures ((Fig 1A shows transistors in active device region within dielectric stack));
a crack stop that extends vertically through the active device region (114+142 vertically through active device region).
Chiang fails to explicitly teach two crack stops or details thereof.
Dyer teaches a similar structure as Chiang, explicitly having different geometric arrangements in which an outer crack stop surrounds an inner crack stop, explicitly:
a first segmented crack stop that surrounds an active prime region of the semiconductor device and that extends vertically through the active device region (inner portion of 130); and
a second continuous crack stop that surrounds the first segmented crack stop, and that extends through vertically through the active device region (outer portion of 130).
All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
As to Claim 12, the combination of Chiang and Dyer teach the semiconductor device of claim 11. Chiang teaches wherein the first segmented crack stop extends vertically through a first portion of the dielectric stack above the active device region. (142 in claimed portion). Dyer, as applied to claim 11, teaches the second continuous crack stop.
As to Claim 13, the combination of Chiang and Dyer teach the semiconductor device according to claim 12. Chiang further teaches wherein the first segmented crack stop and extends through a second portion of the dielectric stack below the active device region (114 in claimed portion).
Dyer, as applied to claim 11, teaches a second crack stop having the same disposition.
As to Claim 14, the combination of Chiang and Dyer teaches the semiconductor device of claim 12. Chiang teaches the device further comprising a substrate (106), the BEOL stack provided on the substrate (stack above 106), with a crack stop which extends entirely though the dielectric stack and through at least a portion of the substrate (114 extends through stack and 106).
Dyer, as applied to claim 12, teaches the second crack stop having the same disposition.
As to Claim 16, the combination of Chiang and Dyer teaches the semiconductor device according to claim 11. Chiang teaches wherein the crack stop comprises at least one material selected from the group consisting of copper, aluminum, tungsten, 2-(trimethylsilyl)ethoxycarbonyl (TEOC), and a dielectric material (114 may comprise copper ¶0035).
Dyer, as applied to claim 11, teaches a second crack stop having the same composition as the first.
As to Claim 17, the combination of Chiang and Dyer teaches the semiconductor device according to claim 11. Chiang teaches wherein the crack stop includes a liner layer (112).
Dyer, as applied to claim 11, teaches a second crack stop having a same liner as the first.
As to Claim 18, the combination of Chiang and Dyer teaches the semiconductor device according to claim 11. Chiang teaches the device further comprising:
a substrate (106); and
a heat sink on a bottom side of the substrate (104 may reasonably be interpreted to be a heat sink),
wherein the crack stop extends entirely though the first dielectric stack and the substrate to contact the heat sink (114 extends through stack and 106 contacting 104).
Dyer, as applied to claim 11, teaches a second crack stop having the same disposition as the first.
As to Claim 19, the combination of Chiang and Dyer teaches the semiconductor device according to claim 11. The structure may reasonably repeat over a chip, comprising plural active prime regions.
As to Claim 20, the combination of Chiang and Dyer teaches the semiconductor device according to claim 11. Chiang further teaches the structure may be considered to be a guard ring (¶0021).
Dyer, as applied to claim 11, teaches the additional crack stop structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern.
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/Corbyn D Mellinger/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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