DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined. Claims 10 and 13 have been withdrawn per the 2/13/2026 restriction election (see below).
Election/Restrictions
Claims 10 and 13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2/13/2026.
Applicant's election with traverse of claims 1-9, 11-12, and 14-20 in the reply filed on 2/13/2026 is acknowledged. The traversal is on the ground(s) that the species are usable together. This is not found persuasive because while it is alleged that the species are usable together, the argument appears to lack support as it is in fact specific features being usable together and not the species as a whole. The species presented rely on the features together to define them, as recited in the restriction/election requirement of 12/17/2025. Examiner can understand and agree with the features being usable together. However, Examiner notes that the features being usable together would create different species than those set forth in the restriction/election requirement.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/20/2023 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 14, and 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1, 14, and 20, they each state “a second horizontal direction different from the first horizontal direction”. This is indefinite as the phrase “a second horizontal direction different from the first horizontal direction” is unclear/undefined. For instance, “a second horizontal direction different from the first horizontal direction” under BRI can include any direction in the same plane so long as the directions are not parallel. In light of the specification and the drawings, the phrase “a second horizontal direction different from the first horizontal direction” will be interpreted to mean “a second horizontal direction orthogonal to the first horizontal direction”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2021/0296184 A1, hereafter Xie) in view of Tsai et al. (US 2022/0278211 A1, hereafter Tsai).
Regarding claim 1, Fig. 11 of Xie teaches a semiconductor device comprising:
a substrate (10, [0027]);
an active pattern (dielectric layer 12, [0027], will be referred to as the active pattern as the devices are formed atop it) disposed on the substrate (10) and extending in a first horizontal direction (x-direction in Fig. 1);
a gate electrode (70, [0065]) disposed on the active pattern (12) and extending in a second horizontal direction (y-direction in Fig. 1) different from the first horizontal direction (x-direction);
a lower source/drain region (50, [0052]) disposed on the active pattern (12) and on at least one side of the gate electrode (70);
an upper source/drain region (54, [0052]) spaced apart from the lower source/drain region (50) in a vertical direction;
an upper source/drain contact (75, [0069]) disposed on the upper source/drain region (54) and connected to the upper source/drain region (54);
an interlayer insulating layer (64, [0062]) surrounding the upper source/drain region (54);
a through-via (77, [0069]) disposed on one of two opposing sidewalls in the second horizontal direction (y-direction) of the upper source/drain region (54) and extending through the interlayer insulating layer (64) in the vertical direction, the through-via (77) being spaced apart from each of the upper source/drain region (54) and the upper source/drain contact (75) in the second horizontal direction (y-direction); and
a dam structure (60, [0059]) disposed on both of the two opposing sidewalls in the second horizontal direction (y-direction) of the upper source/drain region (54), the dam structure (60) being in contact with the upper source/drain region (54), and the dam structure (60) being spaced apart from the through-via (77) in the second horizontal direction (y-direction) (see annotated Fig. 11).
Xie fails to explicitly teach a lower source/drain contact disposed between the lower source/drain region and the upper source/drain region, and connected to the lower source/drain region and the through-via being connected to the lower source/drain contact.
However, Tsai teaches a similar semiconductor device with a dam structure in which a source drain region may have a silicide layer on top of it to enhance electrical conductivity between the via and the source/drain region [0046] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the lower source/drain region of Xie to include a source/drain contact as taught by Tsai. The contact would be on the entirety of the upper surface of the lower source/drain region, making this contact connected to the through via of Xie.
PNG
media_image1.png
600
1048
media_image1.png
Greyscale
Regarding claim 2, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie further teaches in Fig. 11, wherein the dam structure (60, [0059]) includes: a first portion (see annotated Fig. 11) in contact with a first sidewall of the upper source/drain region (54, [0052]); and
a second portion (see annotated Fig. 11) in contact with a second sidewall of the upper source/drain region (54) opposite to the first sidewall of the upper source/drain region (54) in the second horizontal direction (y-direction in Fig. 1).
PNG
media_image2.png
600
1048
media_image2.png
Greyscale
Regarding claim 3, Xie in view of Tsai teach the semiconductor device as claimed in claim 2. Xie further teaches in Fig. 11, wherein the second portion (see annotated Fig. 11) of the dam structure (60, [0059]) is spaced apart from the first portion (see annotated Fig. 11) of the dam structure (60) in the second horizontal direction (y-direction in Fig. 1).
Regarding claim 4, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie further teaches in Fig. 11, wherein the dam structure (60, [0059]) overlaps the lower source/drain contact (of the modified device) in the vertical direction.
Regarding claim 5, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie further teaches in Fig. 11, wherein the dam structure is spaced apart from the lower source/drain contact in the vertical direction. A portion is spaced apart so under BRI, Xie teaches the dam spaced apart from the lower source/drain contact (see annotated Fig. 11).
PNG
media_image3.png
600
1048
media_image3.png
Greyscale
Regarding claim 6, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie further teaches in Fig. 11, wherein the dam structure (60, [0059]) is in contact with both of the two opposing sidewalls in the second horizontal direction of the upper source/drain contact (75, [0069]).
Regarding claim 7, Xie in view of Tsai teach the semiconductor device as claimed in claim 6. Xie fails to teach a thickness in the second horizontal direction of a portion of the dam structure in contact with the upper source/drain region is greater than a thickness in the second horizontal direction of another portion of the dam structure in contact with the upper source/drain contact.
However, in Fig. 8A of Tsai a similar dam structure (gate spacer 260, [0033]) with a protective liner (420, [0040]) is formed along the sidewalls of the contact (570, [0045]). This liner is used to protect the ILD layer (185, [0041]) from being etched [0041]. The final product has some of the protective liner left making the dam (460) have a thinner region in thermal contact with the contact 570, and a thicker region in direct contact with the source/drain region 122. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dam structure of Xie to extend as taught by Tsai.
Regarding claim 8, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie fails to teach wherein a top surface of the dam structure is coplanar with a top surface of the interlayer insulating layer.
However, in Fig. 8A of Tsai a similar, yet elongated dam structure (gate spacer 260, [0033]) with a protective liner (420, [0040]) is formed along the sidewalls of the contact (570, [0045]). This liner is used to protect the ILD layer (185, [0041]) from being etched [0041]. The final product has some of the protective liner left and the dam (460) is extended to be coplanar with the top surface of the contact 570, which would be coplanar with the interlayer insulating layer of Xie. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dam structure of Xie to extend as taught by Tsai, to provide electrical isolation within the device [0039].
Regarding claim 9, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie further teaches wherein both of the two opposing sidewalls in the second horizontal direction (y-direction in Fig. 1) of the upper source/drain contact (75, [0069]) non-contacts the interlayer insulating layer. As the dam structure 60 is in direct contact with the source/drain contact, there are portions of the sidewalls non-contacting the interlayer insulating layer. Under BRI, having any portion of the sidewall not in direct contact with the interlayer insulating layer means that the sidewall non-contacts it.
Regarding claim 11, Xie in view of Tsai teach the semiconductor device as claimed in claim 1. Xie further teaches a plurality of lower nanosheets (24, [0028], see annotated Fig. 11) stacked on the active pattern (dielectric layer 12, [0027]) to be spaced apart from each other in the vertical direction;
an isolation layer (airgap, 56, [0057]) disposed on the plurality of lower nanosheets (24); and
a plurality of upper nanosheets (24, [0028], see annotated Fig. 11) stacked on the isolation layer (56) to be spaced apart from each other in the vertical direction,
wherein the gate electrode (70, [0065]) surrounds each of the plurality of lower nanosheets (24), the isolation layer (56) and the plurality of upper nanosheets (24).
PNG
media_image4.png
600
1048
media_image4.png
Greyscale
Regarding claim 12, Xie in view of Tsai teach the semiconductor device as claimed in claim 11. Xie further teaches wherein each of both opposing sidewalls in the first horizontal direction (x-direction in Fig. 1) of the lower source/drain contact (of the modified device of claim 1) is in contact with the isolation layer (airgap, 56, [0057]). As the airgap is directly in contact with the upper surface of the lower source/drain region 50 (and subsequently the lower source/drain contact of the modified device), the air gap (56) is in thermal contact with the sidewalls of the source/drain contact.
Regarding claim 14, Fig. 11 of Xie teaches a semiconductor device comprising:
a substrate (10, [0027]);
an active pattern (dielectric layer 12, [0027], will be referred to as the active pattern as the devices are formed atop it) disposed on the substrate (10) and extending in a first horizontal direction (x-direction in Fig. 1);
a gate electrode (70, [0065]) disposed on the active pattern (12) and extending in a second horizontal direction (y-direction in Fig. 1) different from the first horizontal direction (x-direction);
a lower source/drain region (50, [0052]) disposed on the active pattern (12) and on at least one side of the gate electrode (70);
an upper source/drain region (54, [0052]) spaced apart from the lower source/drain region (50) in a vertical direction;
a through-via (77, [0069]) spaced apart from the upper source/drain region in the second horizontal direction (y-direction); and
a dam structure (60, [0059]) disposed on each of both opposing sidewalls in the second horizontal direction (y-direction) of the upper source/drain region (54), the dam structure (60) is in contact with the upper source/drain region (54), the dam structure (60) is spaced apart from the through-via (77) in the second horizontal direction (y-direction) (see annotated Fig. 11),
wherein the dam structure (60) includes:
a first portion (see annotated Fig. 11) in contact with a first sidewall of the upper source/drain region (54); and
a second portion (see annotated Fig. 11) in contact with a second sidewall of the upper source/drain region (54)opposite to the first sidewall of the upper source/drain region (54) in the second horizontal direction (y-direction), the second portion is spaced apart from the first portion in the second horizontal direction (y-direction).
Xie fails to explicitly teach a lower source/drain contact disposed between the lower source/drain region and the upper source/drain region, and connected to the lower source/drain region, the through-via being connected to the lower source/drain contact, and the dam structure overlaps the lower source/drain contact in the vertical direction.
However, Tsai teaches a similar semiconductor device with a dam structure in which a source drain region may have a silicide layer on top of it to enhance electrical conductivity between the via and the source/drain region [0046] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the lower source/drain region of Xie to include a source/drain contact as taught by Tsai. The contact would be on the entirety of the upper surface of the lower source/drain region, making this contact connected to the through via of Xie. The dam structure of Xie would also overlap the lower source/drain contact in the vertical direction.
PNG
media_image5.png
600
1048
media_image5.png
Greyscale
Regarding claim 15, Xie in view of Tsai teach the semiconductor device as claimed in claim 14. Xie further teaches in Fig. 11, wherein the dam structure (60, [0059]) is spaced apart from the lower source/drain contact (in the modified device) in the vertical direction. A portion is spaced apart so under BRI, Xie teaches the dam spaced apart from the lower source/drain contact (see annotated Fig. 11).
PNG
media_image3.png
600
1048
media_image3.png
Greyscale
Regarding claim 16, Xie in view of Tsai teach the semiconductor device as claimed in claim 14. Xie further teaches in Fig. 11, further comprising an upper source/drain contact (75, [0069]) disposed on the upper source/drain region (54, [0052]) and connected to the upper source/drain region (54), the upper source/drain contact (75) is disposed between the first portion (see annotated Fig. 11) of the dam structure (60, [0059]) and the second portion (see annotated Fig. 11) of the dam structure (60).
PNG
media_image6.png
600
1048
media_image6.png
Greyscale
Regarding claim 17, Xie in view of Tsai teach the semiconductor device as claimed in claim 16. Xie further teaches in Fig. 11, wherein the upper source/drain contact (54, [0052]) is in contact with each of the first portion (see annotated Fig. 11) of the dam structure (60, [0059]) and the second portion (see annotated Fig. 11) of the dam structure (60).
Regarding claim 18, Xie in view of Tsai teach the semiconductor device as claimed in claim 14. Xie fails to teach wherein a top surface of the dam structure is coplanar with a top surface of the interlayer insulating layer.
However, in Fig. 8A of Tsai a similar, yet elongated dam structure (gate spacer 260, [0033]) with a protective liner (420, [0040]) is formed along the sidewalls of the contact (570, [0045]). This liner is used to protect the ILD layer (185, [0041]) from being etched [0041]. The final product has some of the protective liner left and the dam (460) is extended to be coplanar with the top surface of the contact 570, which would be coplanar with the interlayer insulating layer of Xie. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dam structure of Xie to extend as taught by Tsai, to provide electrical isolation within the device [0039].
Regarding claim 19, Xie in view of Tsai teach the semiconductor device as claimed in claim 14, further comprising:
a plurality of lower nanosheets (24, [0028], see annotated Fig. 11) stacked on the active pattern (dielectric layer 12, [0027]) to be spaced apart from each other in the vertical direction;
an isolation layer (airgap, 56, [0057]) disposed on the plurality of lower nanosheets (24), the isolation layer (56) is in contact with each of both opposing sidewalls in the first horizontal direction (x-direction) of the lower source/drain contact (of the modified device) (as the airgap is directly in contact with the upper surface of the lower source/drain region 50 (and subsequently the lower source/drain contact of the modified device), the air gap (56) is in thermal contact with the sidewalls of the source/drain contact); and
a plurality of upper nanosheets (24, [0028], see annotated Fig. 11) stacked on the isolation layer (56) to be spaced apart from each other in the vertical direction,
wherein the gate electrode (70, [0065]) surrounds each of the plurality of lower nanosheets (24), the isolation layer (56) and the plurality of upper nanosheets (24).
PNG
media_image4.png
600
1048
media_image4.png
Greyscale
Regarding claim 20, Fig. 11 of Xie teaches a semiconductor device comprising:
a substrate (10, [0027]);
an active pattern (dielectric layer 12, [0027], will be referred to as the active pattern as the devices are formed atop it) disposed on the substrate (10) and extending in a first horizontal direction (x-direction in Fig. 1);
a plurality of lower nanosheets (24, [0028], see annotated Fig. 11) stacked on the active pattern (12) to be spaced apart from each other in a vertical direction;
an isolation layer (airgap, 56, [0057]) disposed on the plurality of lower nanosheets (24);
a plurality of upper nanosheets (24, [0028], see annotated Fig. 11) stacked on the isolation layer (56) to be spaced apart from each other in the vertical direction;
a gate electrode (70, [0065]) disposed on the active pattern (12) and extending in a second horizontal direction (y-direction in Fig. 1) different from the first horizontal direction (x-direction), the gate electrode (70) surrounds each of the plurality of lower nanosheets (24), the isolation layer (56) and the plurality of upper nanosheets (24);
a lower source/drain region (50, [0052]) disposed on the active pattern (12) and on at least one side of each of the plurality of lower nanosheets (24);
an upper source/drain region (54, [0052]) disposed on the lower source/drain region (50, [0052]) and on at least one side of each of the plurality of upper nanosheets (24);
an upper source/drain contact (75, [0069]) disposed on the upper source/drain region (54) and connected to the upper source/drain region (54);
an interlayer insulating layer (64, [0062]) surrounding the upper source/drain region (54);
a through-via (77, [0069]) disposed on one of both opposing sidewalls in the second horizontal direction (y-direction) of the upper source/drain region (54) and extending through the interlayer insulating layer (64) in the vertical direction, the through-via (77) being spaced apart from each of the upper source/drain region (54) and the upper source/drain contact (75) in the second horizontal direction (y-direction); and
a dam structure (60, [0059]) disposed on both of two opposing sidewalls in the second horizontal direction (y-direction) of the upper source/drain region (54), the dam structure (60) is in contact with each of the upper source/drain region (54) and the upper source/drain contact (75), the dam structure (60) is spaced apart from the through-via (77) in the second horizontal direction (y-direction) (see annotated Fig. 11);
wherein the dam structure (60) comprises:
a first portion (see annotated Fig. 11) in contact with a first sidewall of the upper source/drain region (54); and
a second portion (see annotated Fig. 11) in contact with a second sidewall of the upper source/drain region (54) opposite to the first sidewall of the upper source/drain region (54) in the second horizontal direction (y-direction), the second portion being spaced apart from the first portion in the second horizontal direction (y-direction).
Xie fails to explicitly teach a lower source/drain contact disposed between the lower source/drain region and the upper source/drain region, and connected to the lower source/drain region, the through-via being connected to the lower source/drain contact, and the dam structure overlaps the lower source/drain contact in the vertical direction.
However, Tsai teaches a similar semiconductor device with a dam structure in which a source drain region may have a silicide layer on top of it to enhance electrical conductivity between the via and the source/drain region [0046] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the lower source/drain region of Xie to include a source/drain contact as taught by Tsai. The contact would be on the entirety of the upper surface of the lower source/drain region, making this contact connected to the through via of Xie. The dam structure of Xie would also overlap the lower source/drain contact in the vertical direction.
PNG
media_image7.png
600
1048
media_image7.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu et al. (US 2022/0262792 A1) teaches a semiconductor device with a dam structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
Prosecution Insights