DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the argument related to independent claim 1, Examiner agrees the amendment overcomes the prior art rejection of 4/1/2026. However, Examiner disagrees that claim 1 is allowable, and a new rejection will be below.
Regarding the arguments related to independent claims 14 and 20, Examiner agrees the amendments overcome the prior art rejection as well as put the claims into condition for allowance. See reasons for allowance below.
Regarding the arguments related to the rejections under 35 U.S.C. § 112, Examiner agrees the language is not indefinite, and subsequently the related rejections have been withdrawn, as also discussed in the interview on 5/6/2026.
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined. Claims 10 and 13 have been withdrawn per the 2/13/2026 restriction election.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “FINFET DEVICE WITH DAM STRUCTURE”.
Claim Objections
Claim 9 is objected to because of the following informalities: Line 3 of claim 9 states "contact contacts the interlayer insulating layer". This appears to be a typo assumed to read "contact the interlayer insulating layer". Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, 9, and 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (US 2022/0037497 A1, hereafter Chung).
Regarding claim 1, Figs. 50A and 50C teach a semiconductor device comprising:
a substrate (202, [0026]);
an active pattern (surface of substrate 202) disposed on the substrate (202) and extending in a first horizontal direction (X-direction, [0026], the active pattern extends in the X direction, as it is a 3-dimensional device);
a gate electrode (258, [0046]) disposed on the active pattern and extending in a second horizontal direction (Y-direction, [0026], the gate electrode extends in the Y-direction, as it is a 3-dimensional device) different from the first horizontal direction (X-direction);
a lower source/drain region (228D, [0038]) disposed on the active pattern and on at least one side of the gate electrode (258);
an upper source/drain region (248D, [0042]) spaced apart from the lower source/drain region (228D) in a vertical direction;
a lower source/drain contact (234, [0040]) disposed between the lower source/drain region (228D) and the upper source/drain region (248D), and connected to the lower source/drain region (228D);
an upper source/drain contact (264, [0049]) disposed on the upper source/drain region (248D) and connected to the upper source/drain region (248D);
an interlayer insulating layer (252, [0044]) surrounding the upper source/drain region (248D);
a metal silicide layer (240, [0040]) disposed between the lower source/drain region (228D) and the lower source/drain contact (234);
a through-via (270, [0049]) disposed on one of two opposing sidewalls in the second horizontal direction (Y-direction) of the upper source/drain region (248D) and extending through the interlayer insulating layer (252) in the vertical direction, the through-via (270) being spaced apart from each of the upper source/drain region (248D) and the upper source/drain contact (264) in the second horizontal direction (Y-direction), the through-via being connected to the lower source/drain contact (228D); and
a dam structure (upper inner spacer features, 226, [0035], see annotated Fig. 50A) disposed on both of the two opposing sidewalls in the second horizontal direction (Y-direction) of the upper source/drain region (248D), the dam structure (226) being in contact with the upper source/drain region (248D), and the dam structure (226) being spaced apart from the through-via (270) in the second horizontal direction (Y-direction).
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Regarding claim 2, Chung teaches the semiconductor device as claimed in claim 1, wherein the dam structure (upper inner spacer features, 226, [0035], see annotated Fig. 50A) includes: a first portion (see annotated Fig. 50A) in contact with a first sidewall of the upper source/drain region (248D, [0042]); and a second portion (see annotated Fig. 50A) in contact with a second sidewall of the upper source/drain region (248D) opposite to the first sidewall of the upper source/drain region (248D) in the second horizontal direction (Y-direction, [0026]) (as this is a 3-dimensional device, the dam structure extends in the second horizontal direction).
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Regarding claim 5, Chung teaches the semiconductor device as claimed in claim 1, wherein the dam structure (upper inner spacer features, 226, [0035], see annotated Fig. 50A) is spaced apart from the lower source/drain (228D, [0038]) contact in the vertical direction.
Regarding claim 6, Chung teaches the semiconductor device as claimed in claim 1, wherein the dam structure (upper inner spacer features, 226, [0035], see annotated Fig. 50A) is in contact with both of the two opposing sidewalls in the second horizontal direction (Y-direction, [0026]) of the upper source/drain contact (248D, [0042]) (as this is a 3-dimensional device, the dam structure extends in the second horizontal direction).
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Regarding claim 9, Chung teaches the semiconductor device as claimed in claim 1, wherein neither of the two opposing sidewalls in the second horizontal direction (Y-direction, [0026]) of the upper source/drain (234, [0040]) contact the interlayer insulating layer (252, [0044]) (as the upper source/drain is covered by layer 250, no sidewall is in contact with the interlayer insulating layer).
Regarding claim 11, Chung teaches the semiconductor device as claimed in claim 1, further comprising:
a plurality of lower nanosheets (208, 204a, [0045]) stacked on the active pattern (surface of substrate 202, [0026]) to be spaced apart from each other in the vertical direction;
an isolation layer (256, [0046]) disposed on the plurality of lower nanosheets (208, 204a); and
a plurality of upper nanosheets (208, 204b, [0045]) stacked on the isolation layer to be spaced apart from each other in the vertical direction,
wherein the gate electrode (258, [0046]) surrounds each of the plurality of lower nanosheets (208, 204a), the isolation layer (256) and the plurality of upper nanosheets (208, 204b).
Regarding claim 12, Chung teaches the semiconductor device as claimed in claim 11, wherein each of both opposing sidewalls in the first horizontal direction (X-direction, [0026]) of the lower source/drain contact (228D, [0038]) is in contact with the isolation layer (256, [0046]).
Allowable Subject Matter
Claim 3-4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 3-4 and 7-8 are indicated as containing allowable subject matter primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in dependent claim(s) 3: “wherein the second portion of the dam structure is spaced apart from the first portion of the dam structure in the second horizontal direction”;
The closest prior art of record, Chung teaches a semiconductor device with a dam structure but fails to teach the second portion of the dam structure is spaced apart from the first portion of the dam structure in the second horizontal direction, nor could Examiner find any reason for this limitation.
in dependent claim(s) 4: “wherein the dam structure overlaps the lower source/drain contact in the vertical direction”;
The closest prior art of record, Chung teaches a semiconductor device with a dam structure but fails to teach a dam structure overlaps the lower source/drain contact in the vertical direction, nor could Examiner find any reason for this limitation.
in dependent claim(s) 7: “wherein a thickness in the second horizontal direction of a portion of the dam structure in contact with the upper source/drain region is greater than a thickness in the second horizontal direction of another portion of the dam structure in contact with the upper source/drain contact”;
The closest prior art of record, Chung teaches a semiconductor device with a dam structure but fails to teach a thickness in the second horizontal direction of a portion of the dam structure in contact with the upper source/drain region is greater than a thickness in the second horizontal direction of another portion of the dam structure in contact with the upper source/drain contact, nor could Examiner find any reason for this limitation.
in dependent claim(s) 8: “wherein a top surface of the dam structure is coplanar with a top surface of the interlayer insulating layer”;
The closest prior art of record, Chung teaches a semiconductor device with a dam structure but fails to teach a top surface of the dam structure is coplanar with a top surface of the interlayer insulating layer, nor could Examiner find any reason for this limitation.
Claim 14-20 allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 14-20 are indicated as containing allowable subject matter primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim(s) 14: “a dam structure disposed on each of both opposing sidewalls in the second horizontal direction of the upper source/drain region, the dam structure is-being in contact with the upper source/drain region, the dam structure is being spaced apart from the through-via in the second horizontal direction, and, the dam structure overlaps overlapping the lower source/drain contact in the vertical direction, wherein the dam structure includes: a first portion in contact with a first sidewall of the upper source/drain region”.
The closest prior art of record, Chung teaches a semiconductor device with a dam structure but fails to teach a dam structure overlaps the lower source/drain contact in the vertical direction, nor could Examiner find any reason for this limitation.
in independent claim(s) 20: “a dam structure disposed on both of two opposing sidewalls in the second horizontal direction of the upper source/drain region, the dam structure being in contact with each of the upper source/drain region and the upper source/drain contact, the dam structure being spaced apart from the through-via in the second horizontal direction, the dam structure overlapping the lower source/drain contact in the vertical direction”.
The closest prior art of record, Chung teaches a semiconductor device with a dam structure but fails to teach a dam structure overlaps the lower source/drain contact in the vertical direction, nor could Examiner find any reason for this limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892 /ERIC W JONES/Primary Examiner, Art Unit 2892
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