DETAILED ACTION
This Office Action is in response to RCE filed May 20, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention. Regarding claim 1, Applicant originally disclosed the followings using the phrase “in parallel” in the original specification:
(A) Applicant originally disclosed in paragraph [0033] of current application that “Contacts are processed such that forward current can be passed in parallel through both of the junctions using a single voltage source”;
(B) Applicant originally disclosed in paragraph [0039] of current application that “The two p-n junctions are connected in parallel” describing Fig. 1 of current application;
(C) Applicant originally disclosed in paragraph [0070] of current application that “The two p-n junctions are connected in parallel” describing Fig. 2 of current application;
(D) Applicant originally disclosed in paragraph [0150] of current application that “The LED die of embodiment (a) to embodiment (b), wherein a forward current passes in parallel through the first light emitting stack and the second light emitting stack using a single voltage source”; and
(E) Applicant originally disclosed in paragraph [0161] of current application that “The method of embodiment (l) to embodiment (m), wherein a forward current passes in parallel through the first light emitting stack and the second light emitting stack using a single voltage source.”
(F) However, Applicant did not originally disclose “a first light emitting stack and a second light emitting stack connected in parallel” as recited on lines 2-3, because (a) Figs. 1 and 2 of current application actually show that the top/bottom surfaces of the two p-n junctions are parallel to each other, but do not necessarily show that the two p-n junctions are connected in parallel as disclosed in paragraphs [0039] and [0070] of current application since without any electrodes disposed in the intermediate structures shown in Figs. 1 and 2 of current application, no one can determine whether the two p-n junctions are connected in parallel since a current path would not be known without at least two electrodes connected to the two p-n junctions, (b) in other words, even a single stack of two p-n junctions can be connected in series or in parallel depending on how two or more electrodes are arranged for the two p-n junctions, (c) the light-emitting diode shown in Fig. 4 of current application, which is directed to Applicant’s elected species, is not exactly a light-emitting diode where the two light emitting stacks are connected in parallel as recited in the amended claim 1 since (i) Applicant did not originally disclose that the electrical bias applied along the current path 1 is the same with the electrical bias applied along the current path 2 illustrated below, which is the requirement for forming circuit elements connected in parallel,
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(d) in other words, as shown below, for two or more circuit elements to be connected in parallel, the same electrical bias should be applied to each of the two or more circuit elements, i.e. the voltage drops for each of the two or more circuit elements should be identical,
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(e) however, unless Applicant can provide a substantiating evidence that the topmost portion of the unclaimed cathode metal layer 216 shown in Fig. 4 of current application can be located anywhere inside the claimed light-emitting diode to form the claimed first and second light emitting stack connected in parallel, i.e. the voltage drops along the current path 1 and the current path 2 illustrated above are identical regardless of the location of the topmost portion of the cathode metal layer 216, Applicant did not originally disclose the claimed first and second light emitting stack connected in parallel, and (f) finally, Fig. 3 of Yan et al. (US 2020/0373456) shows how two light-emitting devices should be connected to form a parallel circuit, see paragraph [0047] of Yan et al. where Yan et al. state “the first light-emitting diode 121b and the second light-emitting diode 122b are electrically connected in parallel” and illustration below, but Applicant did not originally disclose such an electrical connection structure.
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Claims 2-11 depend on claim 1, and therefore, claims 2-11 also fail to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear what the newly added limitation “the second n-type layer comprises a common cathode or common anode” recited on line 10 suggests, because (a) even though Applicant originally disclosed in paragraph [0060] of current application that “The die is designed with electrical contacts such that the “middle” n-type layer of the structure is a common cathode (or common anode) to both of the two p-n junctions in the stack” describing Fig. 3 of current application, it is not clear whether the second n-type layer 204b shown in Fig. 4 of current application can also comprise a common cathode or common anode since the LED die structures and therefore the operating modes of the LED dies shown in Figs. 3 and 4 of current application are different from each other, (b) also, it is not clear whether the limitation cited above suggests that the second n-type layer functions as a common cathode or common anode, or the second n-type layer is connected to a common cathode (electrode) or common anode (electrode), and (c) in addition, a cathode is a negative terminal and an anode is a positive terminal in a light-emitting diode die, and therefore, it is not clear how the second n-type layer can possibly comprise a common cathode or common anode since it does not appear that the second n-type layer can supply holes to the claimed first and second light-emitting active region to function as a common anode.
(2) Further regarding claim 1, it is not clear what the limitation “a first light emitting stack on a second light emitting stack connected in parallel” recited on lines 2-3 refers to, because (a) as discussed above under 35 USC 112(a) rejection, Applicant did not originally disclose the claimed configuration of the first and second light emitting stack connected in parallel, and (b) therefore, it is not clear what the configuration of the first and second light emitting stack should be, and how two or more electrodes should be arranged for the first and second light emitting stack to be “connected in parallel”.
Claims 2-11 depend on claim 1, and therefore, claims 2-11 are also indefinite.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments traversing the 35 USC 112(a) rejection of claim 1 in the REMARKS are not persuasive, because (a) while Applicant made lengthy arguments based on structural arrangements of the component layers, Applicant could not explain why the claimed first and second light emitting stack are connected in parallel with any substantiating evidence, i.e. the two electrical potentials or biases should be identical along the two current paths shown in Fig. 4 of current application, and (b) in other words, while the claimed parallel circuit formed by the claimed first and second light emitting stack is based on an actual electrical characteristic of the claimed first and second light emitting stack, Applicant’s arguments in the REMARKS are primarily based on structural features of the first and second light emitting stack. As discussed above, Fig. 3 of Yan et al. (US 2020/0373456) disclose “the first light-emitting diode 121b and the second light-emitting diode 122b are electrically connected in parallel,” while Fig. 4 of current application, which is directed to Applicant’s elected species, does not show such an electrical connection configuration to form a parallel circuit.
Applicant argues that “Specifically, the first current path and the second current path originate from a common anode and terminate at a common cathode” on the third page of the REMARKS. It is not clear what this argument is about, because this argument is not based on Applicant’s original disclosure, and does not even reflect the LED die structure shown in Fig. 4 of current application, which does not show both “a common anode” and “a common cathode”.
Applicant argues that “A person of ordinary skill in the art would understand that this configuration illustrates that the electrical bias in both light-emitting stacks is the same when a voltage is supplied by a single source (emphasis added)” on the third page of the REMARKS. However, Applicant does not provide any substantiating evidence that “the electrical bias in both light-emitting stacks is the same when a voltage is supplied by a single source.” It appears that Applicant’s argument cited above is based on Applicant’s assumption that the second n-type layer 204b is a metal where the entirety of the second n-type layer 204b is maintained at the same electrical potential, which is not the case in the claimed LED die since the second n-type layer 204b, being formed of a semiconductor material, does not maintain a uniform electrical potential. In addition, since Applicant is one of ordinary skill in the art, Applicant should have been able to provide an evidence why “A person of ordinary skill in the art would understand that this configuration illustrates that the electrical bias in both light-emitting stacks is the same when a voltage is supplied by a single source”, which Applicant did not.
Applicant argues that “Accordingly, a person of ordinary skill in the art would realize that the specific arrangement of parts (i.e., first and second light emitting stack having opposite order of deposition, the location of the tunnel junction, the metal layer contact in the vias) illustrates parallel current paths sharing the same voltage” on the third page of the REMARKS. However, Applicant does not provide any substantiating evidence to support or substantiate this argument. Rather, due to the different arrangements of the semiconductor layers with different material compositions and/or thicknesses of the semiconductor layers, the voltage drops in the two current paths illustrated above would be different from each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.K./Primary Examiner, Art Unit 2815 August 14, 2026
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