DETAILED ACTION
This Office Action is in response to Amendment filed January 13, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention. Regarding claim 1, Applicant originally disclosed the followings using the phrase “in parallel” in the original specification:
(A) Applicant originally disclosed in paragraph [0033] of current application that “Contacts are processed such that forward current can be passed in parallel through both of the junctions using a single voltage source”;
(B) Applicant originally disclosed in paragraph [0039] of current application that “The two p-n junctions are connected in parallel” describing Fig. 1 of current application;
(C) Applicant originally disclosed in paragraph [0070] of current application that “The two p-n junctions are connected in parallel” describing Fig. 2 of current application;
(D) Applicant originally disclosed in paragraph [0150] of current application that “The LED die of embodiment (a) to embodiment (b), wherein a forward current passes in parallel through the first light emitting stack and the second light emitting stack using a single voltage source”; and
(E) Applicant originally disclosed in paragraph [0161] of current application that “The method of embodiment (l) to embodiment (m), wherein a forward current passes in parallel through the first light emitting stack and the second light emitting stack using a single voltage source.”
(F) However, Applicant did not originally disclose “a first light emitting stack and a second light emitting stack connected in parallel” as recited on lines 2-3, because (a) Figs. 1 and 2 of current application actually show that the top/bottom surfaces of the two p-n junctions are parallel to each other, but do not necessarily show that the two p-n junctions are connected in parallel as disclosed in paragraphs [0039] and [0070] of current application since without any electrodes disposed in the intermediate structures shown in Figs. 1 and 2 of current application, no one can determine whether the two p-n junctions are connected in parallel since a current path would not be known without at least two electrodes connected to the two p-n junctions, (b) in other words, even a single stack of two p-n junctions can be connected in series or in parallel depending on how two or more electrodes are arranged for the two p-n junctions, (c) the light-emitting diode shown in Fig. 4 of current application, which is directed to Applicant’s elected species, is not exactly a light-emitting diode where the two light emitting stacks are connected in parallel as recited in the amended claim 1 since (i) Applicant did not originally disclose that the electrical bias applied along the current path 1 is the same with the electrical bias applied along the current path 2 illustrated below, which is the requirement for forming circuit elements connected in parallel,
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(d) in other words, as shown below, for two or more circuit elements to be connected in parallel, the same electrical bias should be applied to each of the two or more circuit elements, i.e. the voltage drops for each of the two or more circuit elements should be identical, and
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(e) however, unless Applicant can provide a substantiating evidence that the topmost portion of the unclaimed cathode metal layer 216 shown in Fig. 4 of current application can be located anywhere inside the claimed light-emitting diode to form the claimed first and second light emitting stack connected in parallel, i.e. the voltage drops along the current path 1 and the current path 2 illustrated above are identical regardless of the location of the topmost portion of the cathode metal layer 216, Applicant did not originally disclose the claimed first and second light emitting stack connected in parallel. Claims 2-11 depend on claim 1, and therefore, claims 2-11 also fail to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear what the limitation “a first light emitting stack on a second light emitting stack connected in parallel” recited on lines 2-3 refers to, because (a) as discussed above under 35 USC 112(a) rejection, Applicant did not originally disclose the claimed configuration of the first and second light emitting stack connected in parallel, and (b) therefore, it is not clear what the configuration of the first and second light emitting stack should be, and how two or more electrodes should be arranged for the first and second light emitting stack to be “connected in parallel”.
(2) Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: a second contact or electrode, and its location, neither of which is claimed in line 10, because (a) for the first and second light emitting stack recited on line 2 to be “connected in parallel”, there should be a second contact or electrode, which Applicant does not claim in claim 1, (b) in addition, the location of the second contact or electrode is also critical for forming the first and second light emitting stack connected in parallel since, for example, if the second contact or electrode, which should correspond to the cathode metal layer 216 shown in Fig. 4 of current application, has a top surface disposed inside the second p-type layer 208b, then the first and second light emitting stack would be connected in series since there would be a single current path between the top surface of the cathode metal layer 216 and the top surface of the anode metal layer 218 in Fig. 4 of current application, and (c) in other words, the top surface of the unclaimed second contact or electrode should be disposed at a level disposed between the bottom surface of the first light-emitting region 206a and the top surface of the second light-emitting region 206b in Fig. 4 of current application for the claimed light-emitting diode such that the first and second light emitting stack may be connected in parallel.
Claims 2-11 depend on claim 1, and therefore, claims 2-11 are also indefinite.
(3) Regarding claim 3, it is not clear what the limitation of claim 3 suggests, because (1-a) Applicant originally disclosed in paragraph [0033] of current application that “Contacts are processed such that forward current can be passed in parallel through both of the junctions using a single voltage source (emphases added)”, in paragraphs [0039] and [0070] of current application that “The two p-n junctions are connected in parallel (emphasis added)” describing Fig. 1 and Fig. 2, respectively, in paragraph [0150] of current application that “The LED die of embodiment (a) to embodiment (b), wherein a forward current passes in parallel through the first light emitting stack and the second light emitting stack using a single voltage source (emphasis added)”, and in paragraph [0161] of current application that “The method of embodiment (l) to embodiment (m), wherein a forward current passes in parallel through the first light emitting stack and the second light emitting stack using a single voltage source (emphasis added)”, (1-b) however, the two p-n junctions shown in Figs. 2 and 4 of current application are not exactly connected in parallel, but rather share the same semiconductor component layers, 1-c) Applicant did not originally disclose what the limitation “a forward current passes in parallel through the first light emitting stack and the second light emitting stack” implies, especially when the current flow shown in Fig. 4 of current application shows irregular current paths, which cannot be “in parallel”, and (1-d) therefore, it is not clear whether the limitation of claim 3 is directed to a structural feature of the claimed LED die or an operating method of the claimed LED die; if it is the former, Applicant should further claim how the first and second light emitting stacks are arranged, and if it is the latter, Applicant should further claim operating condition(s) or parameter(s) for the claimed passage of the forward current.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments traversing the 35 USC 112(b) rejection of claim 3 are not persuasive, because (a) as shown in the illustration above, there are two distinct and unaligned/curved current paths, which cannot be described as “a forward current” passing “in parallel through the first light emitting stack and the second light emitting stack using one voltage source”, and (b) in other words, the curved current paths cannot be parallel to each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yeon et al. (US 9,954,028)
Pfeuffer et al. (US 10,361,249)
von Malm et al. (US 9,917,077)
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.K./Primary Examiner, Art Unit 2815 February 17, 2026