Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This is a response to Amendment/Req. Reconsideration-After Non-Final Office Action filed by Applicant on 11/12/2025.
Claims 1-20 are still pending.
Claims 1, 2, 4 and 8-15 have been amended.
Response to Arguments
Claim Rejections Under 35 U.S.C. 103:
Applicant’s arguments, see pages 7-9, filed 11/12/2025, with respect to the rejection(s) of claims 1-20 being rejected under 35 U.S.C. § 103 as being obvious over Bhat et al. US 2019/0369167 (Hereinafter Bhat) in view of Agarwal et al. US 2009/0251167 (Hereinafter Agarwal), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim et al. US 2023/0135676 in combination with the previously cited prior arts of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bhat et al. US 2019/0369167 (Previously Cited; Hereinafter Bhat) in view of Agarwal et al. US 2009/0251167 (Previously Cited; Hereinafter Agarwal) in further view of Kim et al. US 2023/0135676 (Newly Cited; Hereinafter Kim).
Regarding claim 1, Bhat teaches a testing system (Abstract; “A system for testing a phase leg of an inverter…”), comprising:
a Device Under Test (DUT) interface (Figs. 1, 3; [0034-0045]; interface; DUT, 310, 314) structured to couple to one or more DUTs (Figs. 1, 3; [0045]; “matching connectors for coupling the circuit to an inverter”); and
a device characterization circuit (Figs. 1-4; [0046], “a processing device, controller or computer”; [0038], “The controller 108 may be programmed to perform a variety of test cycles under a variety of conditions”) structured to be controlled to perform static testing and dynamic testing of the one or more DUTs (Figs. 1-4; [0033]; “The test circuit 400 may be operated to perform static tests (e.g., single-pulse test or I-V test), dynamic tests (e.g., double-pulse test), short circuit tests (e.g., shoot-through test), and breakdown tests (e.g., static and dynamic breakdown tests)”.
Bhat does not specifically teach a drain amplifier coupled to a drain of the one or more DUTs and structured to measure drain leakage current.
However, Agarwal does teach a drain amplifier ([0023, 0024]; amplifier) coupled to a drain ([0023, 0024]; drain) of the one or more DUTs and structured to measure drain leakage current ([0023, 0024]; device under test DUT).
It would have been obvious before the effective filing date of the claimed invention to modify the power electronic test automation circuit of Bhat by implementing the teachings of Agarwal regarding a drain amplifier coupled to a drain of the one or more DUTs and structured to measure drain leakage current; in order to “ provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability” (See Agarwal; Abstract).
The combination of Bhat and Agarwal does not specifically teach wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier.
However, Kim does teach wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier (Figs. 6-8; RFB).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Bhat and Agarwal by implementing the teachings of Kim regarding wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier; for the purpose of “measuring a voltage varied based on a short circuit resistance of the touch electrodes and detecting short-circuit states of the touch electrodes” (See Kim; Abstract).
Regarding claim 2, the combination of Bhat, Agarwal and Kim teaches the testing system according to claim 1, wherein Bhat further teaches in which the device characterization circuit further comprises a bypass switch, wherein operation of which enables or disables the drain amplifier to measure drain leakage current (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Regarding claim 3, the combination of Bhat, Agarwal and Kim teaches the testing system according to claim 1, wherein Agarwal further teaches in which the drain amplifier is coupled between the drain of the one or more DUTs and a ground reference ([0023, 0024]; amplifier) .
Regarding claim 4, the combination of Bhat, Agarwal and Kim teaches the testing system according to claim 1, wherein Bhat further teaches in which the one or more DUTs includes a first MOSFET device and a second MOSFET device (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”), and in which the device characterization circuit further comprises: an inductor coupled between the first and second MOSFET devices (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”); and a switch in series with the inductor and structured to controllably enable an effect of the inductor in the device characterization circuit (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Regarding claim 5, the combination of Bhat, Agarwal and Kim teaches the testing system according to claim 1, wherein Agarwal further teaches in which the device characterization circuit further comprises a gate amplifier coupled to a gate of the one or more DUTs and structured to measure a gate leakage current ([0023, 0024]; amplifier).
Regarding claim 6, the combination of Bhat, Agarwal and Kim teaches the testing system according to claim 5, wherein Agarwal further teaches in which the device characterization circuit further comprises a second gate amplifier coupled to a second gate of the one or more DUTs and structured to measure a second gate leakage current ([0023, 0024]; amplifier).
Regarding claim 7, the combination of Bhat, Agarwal and Kim teaches the testing system according to claim 5, wherein Agarwal further teaches in which the device characterization circuit further comprises a gate voltage driver structured to control a gate voltage of the one or more DUTs (Figs. 1-2; [0019, 0022], test integrated circuit).
Regarding claim 8, Bhat teaches a test and measurement system (Abstract; “A system for testing a phase leg of an inverter…”), comprising:
a measurement device (Abstract; “A system for testing a phase leg of an inverter…”); and
a power device (Figs. 1-4; [0015]; test system, 100), including:
an interface (Figs. 1, 3; [0034-0045]; interface) to allow connection to one or more devices under test (DUTs) (Figs. 1, 3; [0045]; “matching connectors for coupling the circuit to an inverter”; [0034-0045]; DUT, 310, 314),
a switching circuit (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314) structured to control an operation of the power device to perform both static testing and dynamic testing of the one or more DUTs (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314), and
a device characterization circuit (Figs. 1-4; [0046], “a processing device, controller or computer”; [0038], “The controller 108 may be programmed to perform a variety of test cycles under a variety of conditions”) under the control of the switching circuit (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Bhat does not specifically the device characterization circuit including a drain amplifier coupled to a drain of the one or more DUTs and structured to measure drain leakage current.
However, Agarwal does teach the device characterization circuit including a drain amplifier ([0023, 0024]; amplifier) coupled to a drain ([0023, 0024]; drain) of the one or more DUTs and structured to measure drain leakage current ([0023, 0024]; device under test DUT).
It would have been obvious before the effective filing date of the claimed invention to modify the power electronic test automation circuit of Bhat by implementing the teachings of Agarwal regarding the device characterization circuit including a drain amplifier coupled to a drain of the one or more DUTs and structured to measure drain leakage current; in order to “ provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability” (See Agarwal; Abstract).
The combination of Bhat and Agarwal does not specifically teach wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier.
However, Kim does teach wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier (Figs. 6-8; RFB).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Bhat and Agarwal by implementing the teachings of Kim regarding wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier; for the purpose of “measuring a voltage varied based on a short circuit resistance of the touch electrodes and detecting short-circuit states of the touch electrodes” (See Kim; Abstract).
Regarding claim 9, the combination of Bhat, Agarwal and Kim teaches the test and measurement system according to claim 8, wherein Bhat further teaches in which the device characterization circuit further comprises a bypass switch, the operation of which enables or disables the drain amplifier to measure drain leakage current (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Regarding claim 10, the combination of Bhat, Agarwal and Kim teaches the test and measurement system according to claim 8, wherein Agarwal further teaches in which the drain amplifier is coupled between the drain of the one or more DUTs and a ground reference ([0023, 0024]; amplifier).
Regarding claim 11, the combination of Bhat and Agarwal teaches the test and measurement system according to claim 8, wherein Bhat further teaches in which the one or more DUTs includes a first MOSFET device and a second MOSFET device (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”), and in which the device characterization circuit further comprises: an inductor coupled between the first and second MOSFET devices (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”); and a switch in series with the inductor and structured to controllably enable an effect of the inductor in the device characterization circuit (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Regarding claim 12, the combination of Bhat, Agarwal and Kim teaches the test and measurement system according to claim 8, wherein Agarwal further teaches in which the device characterization circuit further comprises a gate amplifier coupled to a gate of the one or more DUTs and structured to measure a gate leakage current ([0023, 0024]; amplifier).
Regarding claim 13, the combination of Bhat, Agarwal and Kim teaches the test and measurement system according to claim 12, wherein Agarwal further teaches in which the device characterization circuit further comprises a second gate amplifier coupled to a second gate of the one or more DUTs and structured to measure a second gate leakage current ([0023, 0024]; amplifier).
Regarding claim 14, the combination of Bhat, Agarwal and Kim teaches the test and measurement system according to claim 12, in which the device characterization circuit further comprises a gate voltage driver structured to control a gate voltage of the one or more DUTs (Figs. 1-2; [0019, 0022], test integrated circuit).
Regarding claim 15, Bhat teaches a method in a test environment (Abstract; “A system for testing a phase leg of an inverter…”), comprising:
accepting an input from a user to perform static or dynamic testing (Figs. 1-4; [0033]; “The test circuit 400 may be operated to perform static tests (e.g., single-pulse test or I-V test), dynamic tests (e.g., double-pulse test), short circuit tests (e.g., shoot-through test), and breakdown tests (e.g., static and dynamic breakdown tests)”) on one or more DUTs (Figs. 1, 3; [0045]; “matching connectors for coupling the circuit to an inverter”; [0034-0045]; DUT, 310, 314) in the test environment using a same characterization circuit for both tests (Figs. 1-4; [0046], “a processing device, controller or computer”; [0038], “The controller 108 may be programmed to perform a variety of test cycles under a variety of conditions”).
Bhat does not specifically teach measuring drain leakage current from the one or more DUTs through a drain amplifier coupled between the one or more DUTs and a ground reference voltage.
However, Agarwal does teach measuring drain leakage current from the one or more DUTs ([0023, 0024]; device under test DUT) through a drain amplifier ([0023, 0024]; amplifier) coupled between the one or more DUTs and a ground reference voltage ([0023, 0024]; amplifier).
It would have been obvious before the effective filing date of the claimed invention to modify the power electronic test automation circuit of Bhat by implementing the teachings of Agarwal regarding measuring drain leakage current from the one or more DUTs through a drain amplifier coupled between the one or more DUTs and a ground reference voltage; in order to “ provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability” (See Agarwal; Abstract).
The combination of Bhat and Agarwal does not specifically teach wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier.
However, Kim does teach wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier (Figs. 6-8; RFB).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Bhat and Agarwal by implementing the teachings of Kim regarding wherein a feedback resistor is coupled between an output of the drain amplifier and an input of the drain amplifier; for the purpose of “measuring a voltage varied based on a short circuit resistance of the touch electrodes and detecting short-circuit states of the touch electrodes” (See Kim; Abstract).
Regarding claim 16, the combination of Bhat, Agarwal and Kim teaches the method of claim 15, wherein Bhat further teaches further comprising disabling the drain amplifier by coupling inputs to the drain amplifier to one another through a controllable switch (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Regarding claim 17, the combination of Bhat, Agarwal and Kim teaches the method of claim 15, wherein Bhat further teaches in which the one or more DUTs comprises a MOSFET device, the method further comprising measuring a gate leakage current of the MOSFET device through a gate amplifier in the characterization circuit (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”).
Regarding claim 18, the combination of Bhat, Agarwal and Kim teaches the method of claim 15, wherein Bhat further teaches in which the one or more DUTs comprises a first MOSFET device and a second MOSFET device (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”), the method further comprising measuring a gate leakage current of the first MOSFET device through a first gate amplifier in the characterization circuit and measuring a gate leakage current of the second MOSFET device through a second gate amplifier in the characterization circuit (Figs. 1-4; [0038], “Different test cycles may be performed by operating the switch module, the switch 422, the pair of switching elements (406, 408), and an inverter under test (e.g., 300) in different sequences.”; See [0041-0044] for examples of switching between elements 310 and 314).
Regarding claim 19, the combination of Bhat, Agarwal and Kim teaches the method of claim 18, wherein Bhat further teaches further comprising controlling a gate voltage of the first MOSFET device and a second MOSFET device to isolate one of the MOSFET devices (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”).
Regarding claim 20, the combination of Bhat, Agarwal and Kim teaches the method of claim 18, wherein Bhat further teaches further comprising controlling an effect of an inductor coupled between the first MOSFET device and the second MOSFET device in the characterization circuit (Figs. 1-4; [0021, 0022, 0033]; From [0021]: “The upper switching element 310 and the lower switching element 314 may be active power semiconductor devices such as power MOSFETs or IGBTs.”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou US 2006/0139047 - A device characteristic testing system for testing a first DUT (device under test), a second DUT, a third DUT and a fourth DUT on a wafer, each of the DUTs includes a first end and a second end, the device characteristic testing system includes: a device characteristic testing circuit formed on the wafer includes a first conducting line connected to the second end of the first and the fourth DUT.
Agarwal et al. US 2009/0160463 - A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment.
Bhushan et al. US 2012/0256651 - An integrated test circuit includes pads of a padset for testing multiple device under test units (MDUTs).
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858