DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species B of Figs. 2A-2B, claims 1-14, in the reply filed on August 13, 2026 is acknowledged. The traversal is on the ground that “given that Applicant’s belief that there would be no excess examination burden to fully examine all claims”. However, this is not found persuasive because the species restriction requirement is based on distinction among different species and the serious search and examination burden that would result from examining all such species. Also Applicants did not provide any evidence that the species are obvious variants from each other. The requirement is still deemed proper and is therefore made FINAL. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b). Therefore, claims 1-14 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 2022/0130865, hereinafter Park) in view of Wei (US 2023/0067354).
Regarding claim 1, Park discloses for An integrated circuit comprising:
a first semiconductor device (first region I, Fig. 2, [0024]) having a first semiconductor region (NMOS, Fig. 2, [0024]) extending from a first source or drain region (bottom portion of first source/drain region 141, Fig. 2), and a first gate structure (first gate structure 120, Fig. 2) extending over the first semiconductor region (NMOS, Fig. 2, [0024]),
the first gate structure (120, Fig. 2) extending in a first direction (lateral DR1 direction, Fig. 2) over the first semiconductor region (NMOS, Fig. 2, [0024]) and the first semiconductor region (NMOS, Fig. 2, [0024]) extending in a second direction (vertical DR3 direction, Fig. 2) from the first source or drain region (141, Fig. 2), because the semiconductor channel nanowires NW1 by Park extends in a vertical DR3 direction from the bottom portion of the first source/drain region 141 (Fig. 2). Examiner notes that because Applicants do not specifically claim where the first semiconductor region extends from and to within the first source or drain region, and because the Merriam-Webster dictionary defines a word “region” as “an indefinite area of the world or universe”, therefore, an arbitrary point within the first source/drain region 141 in Park can be selected, for example, a stack of nanowires channel by Park extends from a bottom portion of the first source/drain region 141 (Fig. 2);
a second semiconductor device (second region II, Fig. 2, [0024]) having a second semiconductor region (PMOS, Fig. 2, [0024]) extending in the second direction (vertical DR3 direction, Fig. 2) from a second source or drain region (bottom portion of second source/drain region 142, Fig. 2), and a second gate structure (second gate structure 130, Fig. 2) extending in the first direction (lateral DR1 direction, Fig. 2) over the second semiconductor region (PMOS, Fig. 2, [0024]), the second source or drain region (142, Fig. 2) being adjacent to the first source or drain region (adjacent to 141, Fig. 2) along the first direction (lateral DR1 direction, Fig. 2); and
a dielectric wall (first interlayer insulating layer 150, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) between and contacting both the first semiconductor region (NMOS, Fig. 2) and the second semiconductor region (PMOS, Fig. 2), and extending in the second direction (vertical DR3 direction, Fig. 2) between both the first source or drain region (141, Fig. 2) and the second source or drain region (142, Fig. 2). Examiner notes that Applicants do not specifically claim what orientation the integrated circuit has and/or what the recited first and second directions refer to.
Park does not explicitly disclose that the first source or drain region and the second source or drain region both have n-type dopants or both have p-type dopants.
However, Wei discloses gate-all-around transistor structures including the dielectric wall 110 disposed between semiconductor devices 102 and 104 (Fig. 1A) and source/drain regions 128a/128b (Fig. 1B). Wei further teaches that “the composition and doping of the source and drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used” ([0024]), therefore, one of ordinary skill in the art would have understood that source/drain regions of semiconductor devices having the same polarity may be formed with the same conductivity type – for example, n-type dopants for two NMOS devices or two p-type dopants for two PMOS devices. Examiner notes that Applicants do not specifically claim whether the first and second semiconductor devices are MOS transistors of the same polarity or of different polarities. Also the claim does not require identical dopant species, concentrations, or source/drain compositions beyond the recited common n-type or common p-type dopant configuration.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second source/drain regions having the same doping type, as taught by Wei, in order to simplify process integration and provide electrical characteristics appropriate for the selected device polarity.
Regarding claim 2, Park further discloses that the dielectric wall (150, Fig. 2) directly separates the first gate structure (120, Fig. 2) from the second gate structure (130, Fig. 2).
Regarding claim 3, Park does not explicitly disclose that the first semiconductor region comprises a plurality of first semiconductor nanosheets and the second semiconductor region comprises a plurality of second semiconductor nanosheets.
However, Park further discloses that the semiconductor devices includes the first and second plurality of nanowires NW1 and NW2 (Fig. 2). It is well-known that nanowires and nanosheets were recognized as interchangeable channel structure options for gate-all-around FETs and both structures employ a plurality of semiconductor channels surrounded by gate structure and operate according to the same gate-all-around principles. Therefore, one of ordinary skill in the semiconductor art would have recognized that Park’s plurality of nanowires NW1 and NW2 could be replaced with respective plurality of nanosheets to obtain predictable operation of a gate-all-around FET. A nanosheet implementation would also allow selection of a channel width and aspect ratio suitable for the desired operation while retaining Park’s basic semiconductor configuration.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace Park’s plurality of nanowires with a plurality of nanosheets, and this substitution of one conventional gate-all-around channel architecture for another would have resulted in the claimed first and second semiconductor regions and would have yielded predictable results.
Regarding claim 4, Park further discloses that the dielectric wall (150, Fig. 2) is a first dielectric wall (middle 150, Fig. 1) and the integrated circuit further comprises:
a second dielectric wall (leftmost 150, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) and adjacent to the first semiconductor device (adjacent to region I, Fig. 2), such that the first gate structure (120, Fig. 2) extends in the first direction (lateral DR1 direction, Fig. 2) from the first dielectric wall (middle 150, Fig. 2) to the second dielectric wall (leftmost 150, Fig. 2), because the first gate structure 120 by Park laterally extends from 120_2 adjacent to the middle 150 to 120_1 adjacent to the leftmost 150 (Fig. 2); and
a third dielectric wall (rightmost 150, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) and adjacent to the second semiconductor device (adjacent to region II, Fig. 2), such that the second gate structure (130, Fig. 2) extends in the first direction (vertical direction, Fig. 2) from the first dielectric wall (middle 150, Fig. 2) to the third dielectric wall (rightmost 150, Fig. 2), because the second gate structure 130 by Park laterally extends from 130_1 adjacent to the middle 150 to 130_2 adjacent to the rightmost 150 (Fig. 2).
Regarding claim 5, Park in view of Wei does not explicitly disclose that the dielectric wall is a first dielectric wall and the integrated circuit further comprises: a third semiconductor device having a third semiconductor region extending from a third source or drain region, and a third gate structure extending over the third semiconductor region, the third gate structure extending in the first direction over the third semiconductor region and the third semiconductor region extending in the second direction from the third source or drain region; a fourth semiconductor device having a fourth semiconductor region extending in the second direction from a fourth source or drain region, and a fourth gate structure extending in the first direction over the fourth semiconductor region, the fourth source or drain region being adjacent to the third source or drain region along the first direction; and a second dielectric wall extending in the second direction between and contacting both the third semiconductor region and the fourth semiconductor region, and extending in the second direction between both the third source or drain region and the fourth source or drain region, wherein the third source or drain region and the fourth source or drain region both have n-type dopants or both have p-type dopants.
However, one of ordinary skill in the art would have understood that the semiconductor device arrangement illustrated by Park’s Fig. 2 and Wei’s Fig. 1A is a repeatable unit-cell structure in an integrated circuit array; and in this case, Park discloses that
the dielectric wall (150 in another unit, Fig. 2) is a first dielectric wall (middle 150 in another unit, Fig. 2) and the integrated circuit further comprises:
a third semiconductor device (first region I in another unit) having a third semiconductor region (NMOS in another unit, Fig. 2, [0024]) extending from a third source or drain region (first source/drain region 141 in another unit, Fig. 2), and a third gate structure (120 in another unit, Fig. 2) extending over the third semiconductor region (NMOS in another unit, Fig. 2, [0024]), the third gate structure (120 in another unit, Fig. 2) extending in the first direction (lateral DR1 direction, Fig. 2) over the third semiconductor region (NMOS in another unit, Fig. 2) and the third semiconductor region (NMOS in another unit, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) from the third source or drain region (bottom portion of 141 in another unit, Fig. 2);
a fourth semiconductor device (region II in another unit, Fig. 2) having a fourth semiconductor region (PMOS in another unit, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) from a fourth source or drain region (bottom portion of second source/drain region 142 in another unit, Fig. 2), and a fourth gate structure (130 in another unit, Fig. 2) extending in the first direction (lateral DR3 direction, Fig. 2) over the fourth semiconductor region (PMOS in another unit, Fig. 2), the fourth source or drain region (142 in another unit, Fig. 2) being adjacent to the third source or drain region (141 in another unit, Fig. 2) along the first direction (lateral DR1 direction, Fig. 2); and
a second dielectric wall (leftmost 150 in another unit, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) between and contacting both the third semiconductor region (NMOS in another unit, Fig. 2) and the fourth semiconductor region (PMOS in another unit, Fig. 2), and extending in the second direction (vertical DR3 direction, Fig. 2) between both the third source or drain region (141 in another unit, Fig. 2) and the fourth source or drain region (142 in another unit, Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replicate Park’s semiconductor device unit in an array to provide additional semiconductor devices and dielectric walls. Such replication of a conventional gate-all-around FET unit cell would have predictably increased circuit functionality and device density while maintaining the dielectric wall between adjacent semiconductor devices.
Further regarding claim 5, Park does not explicitly disclose that the third source or drain region and the fourth source or drain region both have n-type dopants or both have p-type dopants.
However, Wei discloses gate-all-around transistor structures including the dielectric wall 110 disposed between semiconductor devices 102 and 104 (Fig. 1A) and source/drain regions 128a/128b (Fig. 1B). Wei further teaches that “the composition and doping of the source and drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used” ([0024]), therefore, one of ordinary skill in the art would have understood that source/drain regions of semiconductor devices having the same polarity may be formed with the same conductivity type – for example, n-type dopants for two NMOS devices or two p-type dopants for two PMOS devices. Examiner notes that Applicants do not specifically claim whether the third and fourth semiconductor devices are MOS transistors of the same polarity or of different polarities. Also the claim does not require identical dopant species, concentrations, or source/drain compositions beyond the recited common n-type or common p-type dopant configuration.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide third and fourth source/drain regions having the same doping type, as taught by Wei, in order to simplify process integration and provide electrical characteristics appropriate for the selected device polarity.
Regarding claim 6, Park in view of Wei does not explicitly disclose that the dielectric wall is a first dielectric wall and the integrated circuit further comprises: a third semiconductor device having a third semiconductor region extending from a third source or drain region, and a third gate structure extending over the third semiconductor region, the third gate structure extending in the first direction over the third semiconductor region and the third semiconductor region extending in the second direction from the third source or drain region; a fourth semiconductor device having a fourth semiconductor region extending in the second direction from a fourth source or drain region, and a fourth gate structure extending in the first direction over the fourth semiconductor region; and a second dielectric wall extending in the second direction and contacting the fourth semiconductor region.
However, one of ordinary skill in the art would have understood that the semiconductor device arrangement illustrated by Park’s Fig. 2 and Wei’s Fig. 1A is a repeatable unit-cell structure in an integrated circuit array; and in this case, Park discloses that
the dielectric wall (150 in another unit, Fig. 2) is a first dielectric wall (middle 150 in another unit, Fig. 2) and the integrated circuit further comprises:
a third semiconductor device (region I in another unit, Fig. 2) having a third semiconductor region (NMOS in another unit, Fig. 2) extending from a third source or drain region (141 in another unit, Fig. 2), and a third gate structure (120 in another unit, Fig. 2) extending over the third semiconductor region (NMOS in another unit, Fig. 2), the third gate structure (120 in another unit, Fig. 2) extending in the first direction (lateral DR1 direction, Fig. 2) over the third semiconductor region (NMOS in another unit, Fig. 2) and the third semiconductor region (region I in another unit, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) from the third source or drain region (bottom portion of 141 in another unit, Fig. 2);
a fourth semiconductor device (region II in another unit, Fig. 2) having a fourth semiconductor region (PMOS in another unit, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) from a fourth source or drain region (bottom portion of 142 in another unit, Fig. 2), and a fourth gate structure (130 in another unit, Fig. 2) extending in the first direction (lateral DR1 direction, Fig. 2) over the fourth semiconductor region (PMOS in another unit, Fig. 2); and
a second dielectric wall (rightmost 150 in another unit, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) and contacting the fourth semiconductor region (PMOS in another unit, Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replicate Park’s semiconductor device unit in an array to provide additional semiconductor devices and dielectric walls. Such replication of a conventional gate-all-around FET unit cell would have predictably increased circuit functionality and device density while maintaining the dielectric wall between adjacent semiconductor devices.
Regarding claim 8, Wei further discloses A printed circuit board (motherboard 502, Fig. 5) comprising the integrated circuit of claim 1 (Fig. 1), because “the motherboard 502 may be, for example, any printed circuit board (PCB)” ([0073]).
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 2022/0130865, hereinafter Park) in view of Cheng et al. (US 11,462,612; hereinafter Cheng).
Regarding claim 9, Park discloses for An integrated circuit comprising:
a first semiconductor device (region I, Fig. 2) having a first semiconductor region (NMOS, Fig. 2, [0024]) extending from a first source or drain region (left 141, Fig. 2) to a second source or drain region (right 141, Fig. 2), and a first gate structure (120, Fig. 2) extending over the first semiconductor region (NMOS, Fig. 2, [0024]), the first gate structure (120, Fig. 2) extending in a first direction (lateral DR1 direction, Fig. 2) over the first semiconductor region (NMOS, Fig. 2, [0024])) and the first semiconductor region (NMOS, Fig. 2, [0024]) extending in a second direction (vertical DR3 direction, Fig. 2) from the first source or drain region (left 141, Fig. 2) to the second source or drain region (right 141, Fig. 2), because Applicants do not specifically claim what portion of the first semiconductor region extends in a second direction, and because the Merriam-Webster dictionary defines a word “region” as “an indefinite area of the world or universe”, therefore, an arbitrary point within the first source/drain region 141 in Park can be selected, for example, nanowires NW1 by Park vertically extends from a bottom portion of the left first source/drain region 141 to a top portion of the right first source/drain region 141 (Fig. 2);
a first dielectric wall (leftmost first interlayer insulating layer 150, Fig. 2) extending in the second direction (vertical DR3, Fig. 2) and contacting the first semiconductor region (NMOS, Fig. 2);
a second dielectric wall (middle first interlayer insulating layer 150, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) and adjacent to the first semiconductor device (NMOS, Fig. 2), such that the first gate structure (120, Fig. 2) extends in the first direction (lateral DR1 direction, Fig. 2) from the first dielectric wall (leftmost 150, Fig. 2) to the second dielectric wall (middle 150, Fig. 1); and
a second semiconductor device (region II, Fig. 2) having a second semiconductor region (PMOS, Fig. 2, [0024]) extending in the second direction (vertical DR3 direction, Fig. 2) from a third source or drain region (left 142, Fig. 2) to a fourth source or drain region (right 142, Fig. 2), because Applicants do not specifically claim what portion of the second semiconductor region extends in a second direction, and because the Merriam-Webster dictionary defines a word “region” as “an indefinite area of the world or universe”, therefore, an arbitrary point within the second source/drain region 142 in Park can be selected, for example, nanowires NW2 by Park vertically extends from a bottom portion of the left second source/drain region 142 to a top portion of the right second source/drain region 142 (Fig. 2), and
a second gate structure (130, Fig. 2) extending in the first direction (lateral DR1 direction, Fig. 2) from the second dielectric wall (middle 150, Fig. 2) and surrounding the second semiconductor region (PMOS, Fig. 2, [0024]).
Park does not explicitly disclose that a first dielectric wall extending in the second direction adjacent to both the first source or drain region and the second source or drain region.
However, Cheng discloses gate-all-around FET structures having multi-bridge-channel (MBC) transistors and the device includes the semiconductor device with p-well 202P (Fig. 17), which may correspond to the first semiconductor device in the claimed invention, and the left second layer 226 (labeled in Fig. 16), which may correspond to the first dielectric wall in the claimed invention, disposed between the channel layers 208 (Fig. 17). Cheng further teaches that the left second layer 226 is formed between the n-type source/drain features 260N, and therefore, the left and right n-type source/drain features 260P may correspond to the first and second source or drain region in the claimed invention (Fig. 17). Therefore, the left second layer 226 vertically extends (i.e., the claimed second direction) adjacent to the n-type source/drain features 260N.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Cheng’s gate-all-around FET structures having dielectric wall adjacent to a pair of source/drain regions into Park’s device structure, in order to increase the integration density of gate-all-around FETs, thereby improving the device performance.
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Regarding claim 10, Park in view of Cheng does not explicitly disclose that the first semiconductor region comprises a plurality of semiconductor nanosheets and the second semiconductor region comprises a plurality of semiconductor nanoribbons.
However, Park further discloses that the semiconductor devices include the first and second plurality of nanowires NW1 and NW2 (Fig. 2) and Cheng further discloses that the channel members resemble a sheet or a nanosheet (Col. 11, line 56). It is well-known that nanowires, nanosheets and nanoribbons were recognized as interchangeable channel structure options for gate-all-around FETs and both structures employ a plurality of semiconductor channels surrounded by gate structure and operate according to the same gate-all-around principles. Therefore, one of ordinary skill in the semiconductor art would have recognized that Park’s plurality of nanowires NW1 and NW2 could be replaced with respective plurality of nanosheets or nanoribbons to obtain predictable operation of a gate-all-around FET. A nanosheet or nanoribbons implementation would also allow selection of a channel width and aspect ratio suitable for the desired operation while retaining Park’s basic semiconductor configuration.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace Park’s plurality of nanowires with a plurality of nanosheets or nanoribbons, and this substitution of one conventional gate-all-around channel architecture for another would have resulted in the claimed first and second semiconductor regions and would have yielded predictable results.
Regarding claim 11, Cheng further discloses that the first source or drain region (n-type source/drain feature 260N on the left side of 226, Fig. 16-17) and the second source or drain region (n-type source/drain feature 260N on the right side of 226, Fig. 16-17) both have n-type dopants (n-type, Col. 10, lines 31-63) and the third source or drain region (p-type source/drain feature 260P on the left side of 226, Fig. 16-17) and the fourth source or drain region (p-type source/drain feature 260P on the right side of 226, Fig. 16-17) both have p-type dopants (p-type, Col. 10, lines 31-63) or the first source or drain region and the second source or drain region both have p-type dopants and the third source or drain region and the fourth source or drain region both have n-type dopants.
Regarding claim 12, Park further discloses that a third dielectric wall (rightmost 150, Fig. 2) extending in the second direction (vertical DR3 direction, Fig. 2) and adjacent to the second semiconductor device (region II, Fig. 2), such that the second gate structure (130, Fig. 2) extends in the first direction (lateral DR1 direction, Fig. 2) from the second dielectric wall (middle 150, Fig. 2) to the third dielectric wall (rightmost 150, Fig. 2), because the second gate structure extends from 130_1 adjacent to the middle 150 to 130_2 adjacent to the rightmost 150 (Fig. 2).
Regarding claim 13, Park further discloses that the second direction (vertical DR3 direction, Fig. 2) is substantially perpendicular to the first direction (lateral DR1 direction, Fig. 2).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 2022/0130865, hereinafter Park) in view of Cheng et al. (US 11,462,612; hereinafter Cheng) as applied to claim 9 above, and further in view of Wei (US 2023/0067354). The teachings of Park in view of Cheng are discussed above.
Regarding claim 14, Park in view of Cheng does not explicitly disclose that A printed circuit board comprising the integrated circuit of claim 9.
However, Wei discloses that “the motherboard 502 may be, for example, any printed circuit board (PCB)” ([0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide integrated circuit of Park and Cheng on a printed circuit board, as taught by Wei, to enable routine mounting and electrical interconnection of the integrated circuit on a PCB.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this office action do not teach the claim limitation, “the first, second and fourth semiconductor devices are forksheet transistor devices” of claim 7.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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