DETAILED ACTION
Response to Arguments
Applicant's arguments filed 8/31/26 have been fully considered.
Regarding Claim 1, applicant has argued that the newly recited co-reactants are not taught by the Belau and/or Korolik. The argument is persuasive. However, the co-reactants are well known in the memory stack etching art as shown by newly cited Saitoh et al.
Regarding Claims 13 and 18, applicant has argued that Belau does not provide any teaching or suggestion to utilize only frequency in the range about 13.56 MHz to about 30MHz. However, the argument is not persuasive at least because the Claims do not recite forming plasma only at a frequency in the range about 13.56 MHz to about 30MHz.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8, 13, 14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2016/0064245 to Saitoh et al.
Regarding Claim 1, Saitoh et al. teaches a semiconductor processing method comprising: providing a hydrogen-containing precursor, a fluorine-containing precursor, and a co-reactant (Paragraph 66-72) to a processing region of a semiconductor processing chamber (Fig 3), wherein the co-reactant comprises boron trichloride (BCl3). sulfur dioxide (SO2). or carbonyl sulfide (COS), wherein a substrate (W) is disposed on a substrate support (18) within the processing region, and wherein one or more layers of silicon-containing material (IL1, IL2) are disposed on the substrate; forming plasma effluents of the hydrogen-containing precursors and lithe fluorine-containing precursor, and the co-reactant; and contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor and lithe fluorine-containing precursor, and the co- reactant, wherein the contacting etches a portion of the one or more layers of silicon-containing material.
Regarding Claim 2, Saitoh et al. teaches (Paragraphs 40, 69) the hydrogen-containing precursor comprises diatomic hydrogen (H2).
Regarding Claim 3, Saitoh et al. teaches (Paragraphs 40, 68) the fluorine-containing precursor comprises hydrogen fluoride (HF) or nitrogen trifluoride (NF3).
Regarding Claim 4, Saitoh et al. teaches (Paragraphs 17, 25) the one or more layers of silicon-containing material comprising alternating layers of silicon-and- oxygen-containing material and silicon-and-nitrogen-containing material.
Regarding Claim 5, Saitoh et al. teaches (Paragraph 25) the one or more layers of silicon-containing material comprise greater than or about 20
Regarding Claim 6, Saitoh et al. teaches (Paragraphs 48, 54, 55) bias power to the substrate support during the contacting.
Regarding Claim 8, Saitoh et al. teaches (Paragraphs 48, 54, 55) the contacting etches a feature in the one or more layers of silicon-containing material.
Regarding Claim 13, Saitoh et al. teaches semiconductor processing method comprising: providing a hydrogen-containing precursor and a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate (W) is disposed on a substrate support (18) within the processing region, and wherein alternating layers of silicon-and- oxygen-containing material and silicon-and-nitrogen-containing material (IL1, IL2) are disposed on the substrate; forming plasma effluents of the hydrogen-containing precursor and the fluorine- containing precursor at a frequency between about 13.56 MHz and about 30 MHz (Paragraphs 47, 48 and 73); and contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor, wherein the contacting etches a feature through the alternating layers of silicon-and-oxygen-containing material and silicon-and-nitrogen-containing material.
Regarding Claim 14, Saitoh et al. teaches (Paragraph 66-72) providing a co-reactant with the hydrogen-containing precursor and the fluorine-containing precursor, wherein the co-reactant comprises a boron-containing precursor, a phosphorous-containing precursor, or a sulfur-containing precursor.
Regarding Claim 16, Saitoh et al. teaches (Paragraph 65-90) a pressure within the semiconductor processing chamber is maintained at less than or about 150 mTorr.
Regarding Claim 17, Saitoh et al. teaches (Paragraph 65-90) the plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor are generated at a plasma power of less than or about 5,000 W.
Regarding Claim 18, Saitoh et al. teaches semiconductor processing method comprising: providing a hydrogen-containing precursor and a fluorine-containing precursor to a processing region of a semiconductor processing chamber (Fig 3), wherein a substrate (W) is disposed on a substrate support (18) within the processing region, and wherein alternating layers of silicon-and- oxygen-containing material and silicon-and-nitrogen-containing material (IL1, IL2) are disposed on the substrate; providing a co-reactant with the hydrogen-containing precursor and the fluorine- containing precursor; forming plasma effluents of the hydrogen-containing precursor, the fluorine- containing precursor, and the co-reactant at a frequency between about 13.56 MHz and about 30 MHz (Paragraphs 47, 48 and 73); contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor, the fluorine-containing precursor, and the co-reactant, wherein the contacting etches a feature through the alternating layers of silicon-and-oxygen- containing material and silicon-and-nitrogen-containing material; and applying a pulsed bias power (Paragraph 52) to the substrate support during the contacting, wherein the bias power draws the plasma effluents of the hydrogen-containing precursor, the fluorine-containing precursor, and the co-reactant to the substrate resulting in an anisotropic etch.
Claims 13, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2019/0131135 to Belau et al.
Regarding Claim 13, Belau et al. teaches a semiconductor processing method comprising: providing a hydrogen-containing precursor (Paragraph 24) and a fluorine-containing precursor (Paragraph 24) to a processing region of a semiconductor processing chamber (349), wherein a substrate (208) is disposed on a substrate support (308) within the processing region, and wherein one or more layers (Paragraph 13) of silicon-containing material comprising alternating layers of silicon-and-oxygen-containing material (224) and silicon-and-nitrogen-containing material (228) are disposed on the substrate; forming plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor at a frequency of between about 13.56 and 30 MHz (Paragraph 14); and contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor ad the co-reactant, wherein the contacting etches a portion of the one or more layers of silicon-containing material.
Regarding Claim 16, Belau et al. teaches (Paragraph 18) a pressure within the semiconductor processing chamber is maintained at less than or about 150 mTorr.
Regarding Claim 17, Belau et al. teaches (Paragraph 18) the plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor are generated at a plasma power of less than or about 5,000 W.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7, 9-11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication 2016/0064245 to Saitoh et al. in view of US Publication 2019/0131135 to Belau et al.
Regarding Claim 7, Saitoh et al. does not expressly teach bias greater than 400V. However, the limitation is well known as shown by Belau et al. (Paragraph 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a pulsed bias in the method of Saitoh et al. as shown by Belau et al. in order to provide high aspect ratio with predictable results.
Regarding Claim 9, Saitoh et al. does not expressly teach the feature is characterized by an aspect ratio of greater than or about 10:1 However, the limitation is well known as shown by Belau et al. (Paragraph 19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an aspect ratio of greater than or about 10:1 in the method of Saitoh et al. as shown by Belau et al. in order to provide a memory device with predictable results.
Regarding Claim 10, Saitoh et al. teaches cooling (Paragraph 34) but does not expressly teach the substrate is characterized by a temperature of less than or about 100 °C. However, the limitation is well known for memory stack etching with fluorocarbon plasma as shown by Belau et al. (Paragraph 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a temperature of less than or about 100 °C in the method of Saitoh et al. as shown by Belau et al. in order to improve the etching characteristics with predictable results.
Regarding Claims 11 and 15, Saitoh et al. does not expressly teach the contacting etches the portion of the one or more layers of silicon-containing material at an etch rate of greater than or about 200 nm/min, or etches the alternating layers of silicon-and-oxygen-containing material and silicon- and-nitrogen-containing material at an etch rate of greater than or about 500 nm/min. However, the same etching rate would reasonably be expected to be achieved using the same chemistry and process conditions or else is the result of essential limitations which have not been claimed.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication 2019/0131135 to Belau et al. in view of US Publication 2021/0143016 to Yokoyama et al.
Regarding Claim 18, Belau et al. teaches a semiconductor processing method comprising: providing a hydrogen-containing precursor (Paragraph 24) and a fluorine- containing precursor (Paragraph 24) to a processing region of a semiconductor processing chamber (349), wherein a substrate (208) is disposed on a substrate support (308) within the processing region, and wherein and wherein one or more layers (Paragraph 13) of silicon-containing material comprising alternating layers of silicon-and-oxygen-containing material (224) and silicon-and-nitrogen-containing material (228) are disposed on the substrate; (Paragraph 18 and 24) providing a co-reactant with the hydrogen-containing precursor and the fluorine-containing precursor; forming plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor, and co-reactant at a frequency between 13.56 and 30MHz (Paragraph 14); and contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor, wherein the contacting etches a portion of the one or more layers of silicon-containing material.
Regarding Claim 18, Belau et al. teaches the method of the invention substantially as claimed, but does not expressly teach pulsed bias power. However, pulsed bias power is well-known in the art of etching a silicon containing stack. For example, Yokoyama et al teaches (Paragraph 59-65 and 99-106) pulsed bias provides interleaved etching and deposition phases for etching an oxide/nitride stack (Paragraph 32) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a pulsed bias in the method of Belau et al. in order to balance etching and deposition with predictable results.
Regarding Claim 19, as applied above, Belau et al. in view of teaches the method of the invention substantially as claimed, but does not expressly teach a co-reactant such as a phosphorous containing precursor. However, Yokoyama et al. teaches (Paragraphs 24 and 74) a phosphorous containing precursor for plasma etching an alternating silicon oxide/nitride stack. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a phosphorus containing precursor in the method of Belau et al. in order to improve selectivity in a silicon stack etching process with predictable results.
Regarding Claim 20, Belau et al. teaches (Paragraph 20) a temperature of the substrate is less than or about 0°C.
Conclusion
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/ROBERTS P CULBERT/Primary Examiner, Art Unit 1716
