DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/29/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shu et al. US 10566202 in view of Xie et al. US 2024/0162118.
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Re claim 1, Shu teaches an integrated circuit structure (fig1), comprising:
a plurality of gate lines (104 and 106, fig1, col2 line 55-60) extending over a plurality of semiconductor channel structures (102, fig1, col2 line55-60).
Shu does not explicitly show a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures;
Xie teaches an integrated circuit structure (fig1), comprising:
a plurality of gate lines (GS 22, fig1 and 12C, [29]) extending over a plurality of semiconductor nanowire stack channel structures (16, fig12C, [30]);
a plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]) extending over a plurality of source or drain structures (24, 25, fig12D, [30]), individual ones of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]) alternating with individual ones of the plurality of gate lines (22, fig1, 12A and 12C, [29]);
a backside metal routing layer (38, 39, fig1 and 12D, [57]) extending beneath one or more of the plurality of gate lines (22, fig12C, [29]) and beneath one or more of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]); and
a conductive structure (part of 27 between 15, fig12D, [30]) coupling the backside metal routing layer (38, 39, fig1 and 12D, [57]) to one of the one or more of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]), the conductive structure having a cut (space between 27, fig12D) between first and second conductive structure portions (27 between 38 and 25, 27 between 39 and 24, fig12D).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu and Xie to form a gate all around device with backside power rails. The motivation to do so is to free up space for high density devices with better gate control and reduce backside metal level resistance (Xie, [4, 24]).
Shu in view of Xie teaches wherein a cut in a first one of the plurality of gate lines (Shu, 108, fig1, col2 line 60) adjacent to the cut in the conductive structure (Xie, space between 27, fig12D) is smaller than a cut in a second one of the plurality of gate lines (Shu, 110, fig1, col2 line 60) adjacent to the first or second conductive structure portions (Xie, 27 between 38 and 25, 27 between 39 and 24, fig12D).
Re claim 2, Shu modified above teaches the integrated circuit structure of claim 1, wherein the backside metal routing layer is a backside power delivery line (Xie, 38, 39, fig12D, [56]).
Re claim 3, Shu modified above teaches the integrated circuit structure of claim 1, wherein the conductive structure is a deep via bar structure (Xie, part of 27 between 15, fig12D, [30]).
Re claim 4, Shu modified above teaches the integrated circuit structure of claim 1, wherein the conductive structure is a recessed deep via bar structure (Xie, part of 27 between 15, fig12D, [30]).
Re claim 6, Shu teaches an integrated circuit structure (fig1), comprising:
a plurality of gate lines (104 and 106, fig1, col2 line 55-60) extending over a plurality of semiconductor fin structures (102, fig1, col2 line55-60);
Shu does not explicitly show a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines; a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure having a cut between first and second conductive structure portions, wherein a cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.
Xie teaches an integrated circuit structure (fig1), comprising:
a plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]) extending over a plurality of source or drain structures (24, 25, fig12D, [30]), individual ones of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]) alternating with individual ones of the plurality of gate lines (22, fig1, 12A and 12C, [29]);
a backside metal routing layer (38, 39, fig1 and 12D, [57]) extending beneath one or more of the plurality of gate lines (22, fig1, 12A and 12C, [29]) and beneath one or more of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]); and
a conductive structure (part of 27 between 15, fig12D, [30]) coupling the backside metal routing layer (38, 39, fig1 and 12D, [57]) to one of the one or more of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]), the conductive structure (part of 27 between 15, fig12D, [30]) having a cut (space between 27, fig12D) between first and second conductive structure portions (27 between 38 and 25, 27 between 39 and 24, fig12D).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu and Xie to form a device with backside power rails. The motivation to do so is to free up space for high density devices and reduce backside metal level resistance (Xie, [4, 24]).
Shu in view of Xie teaches wherein a cut in a first one of the plurality of gate lines (Shu, 108, fig1, col2 line 60) adjacent to the cut in the conductive structure (Xie, space between 27, fig12D) is smaller than a cut in a second one of the plurality of gate lines (Shu, 110, fig1, col2 line 60) adjacent to the first or second conductive structure portions.
Re claim 7, Shu modified above teaches the integrated circuit structure of claim 6, wherein the backside metal routing layer is a backside power delivery line (Xie, 38, 39, fig12D, [56]).
Re claim 8, Shu modified above teaches the integrated circuit structure of claim 6, wherein the conductive structure is a deep via bar structure (Xie, part of 27 between 15, fig12D, [30]).
Re claim 9, Shu modified above teaches the integrated circuit structure of claim 6, wherein the conductive structure is a recessed deep via bar structure (Xie, part of 27 between 15, fig12D, [30]).
Re claim 11, Shu teaches a computing device (fig1), comprising:
a board (202, fig1 and 2, col3 line 40-45); and
a component coupled to the board (100, fig1, col2 line 55-60), the component including an integrated circuit structure (fig1), comprising:
a plurality of gate lines (104 and 106, fig1, col2 line 55-60) extending over a plurality of semiconductor nanowire stack channel structures or semiconductor fin structures (102, fig1, col2 line55-60);
Shu does not explicitly show a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines; a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure having a cut between first and second conductive structure portions, wherein a cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.
Xie teaches an integrated circuit structure (fig1), comprising:
a plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]) extending over a plurality of source or drain structures (24, 25, fig12D, [30]), individual ones of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]) alternating with individual ones of the plurality of gate lines (22, fig1, 12A and 12C, [29]);
a backside metal routing layer (38, 39, fig1 and 12D, [57]) extending beneath one or more of the plurality of gate lines (22, fig1, 12A and 12C, [29]) and beneath one or more of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]); and
a conductive structure (part of 27 between 15, fig12D, [30]) coupling the backside metal routing layer (38, 39, fig1 and 12D, [57]) to one of the one or more of the plurality of trench contacts (part of 27 in layer 28 contacting 24/25, fig12D, [30]), the conductive structure having a cut (space between 27, fig12D) between first and second conductive structure portions (27 between 38 and 25, 27 between 39 and 24, fig12D).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu and Xie to form a device with backside power rails. The motivation to do so is to free up space for high density devices and reduce backside metal level resistance (Xie, [4, 24]).
Shu in view of Xie teaches wherein a cut in a first one of the plurality of gate lines (Shu, 108, fig1, col2 line 60) adjacent to the cut in the conductive structure (Xie, space between 27, fig12D) is smaller than a cut in a second one of the plurality of gate lines (Shu, 110, fig1, col2 line 60) adjacent to the first or second conductive structure portions.
Re claim 12, Shu modified above teaches the computing device of claim 11, comprising the semiconductor nanowire stack channel structures (Xie, 16, fig12C, [30]).
Re claim 13, Shu modified above teaches the computing device of claim 11, comprising the semiconductor fin structures (Shu, 102, fig1 and 2, col2 line55-60).
Claim(s) 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shu et al. US 10566202, Xie et al. US 2024/0162118 and Murthy et al. US 2023/0187273.
Re claim 14, Shu does not explicitly show the computing device of claim 11, further comprising: a memory coupled to the board.
Murthy teaches IC circuit with backside power rail comprising a memory coupled to the board (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form a device with backside power rails with a memory coupled to the board. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Re claim 15, Shu does not explicitly show the computing device of claim 11, further comprising: a communication chip coupled to the board.
Murthy teaches IC circuit with backside power rail comprising a communication chip coupled to the board (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form a device with backside power rails with a communication chip coupled to the board. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Re claim 16, Shu does not explicitly show the computing device of claim 11, further comprising: a battery coupled to the board.
Murthy teaches IC circuit with backside power rail comprising a battery coupled to the board (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form a device with backside power rails with a battery coupled to the board. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Re claim 17, Shu does not explicitly show the computing device of claim 11, further comprising: a camera coupled to the board.
Murthy teaches IC circuit with backside power rail comprising a camera coupled to the board (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form a device with backside power rails with a camera coupled to the board. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Re claim 18, Shu does not explicitly show the computing device of claim 11, further comprising: a display coupled to the board.
Murthy teaches IC circuit with backside power rail comprising a display coupled to the board (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form a device with backside power rails with a display coupled to the board. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Re claim 19, Shu does not explicitly show the computing device of claim 11, wherein the component is a packaged integrated circuit die.
Murthy teaches a packaged integrated circuit die (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form a packaged integrated circuit die with backside power rails. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Re claim 20, Shu does not explicitly show the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Murthy teaches IC circuit with backside power rail comprising a processor (1004, fig4, [64]), a communications chip (1006, fig4, [64]), and a digital signal processor (fig4, [65]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Shu, Xie and Murthy to form computing system with backside power rails. The motivation to do so is to free up space and reduce congestion of front side interconnects due to power and signal routing (Murthy, [1]), reduce backside metal level resistance (Xie, [4, 24]) and achieve most satisfactory printout of gate structure for gates of different types of transistors (Shu, col1 line 25-35).
Allowable Subject Matter
Claim 5 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to form current deep via bar (DVB) to assist self-alignment to gate edges and recession of the DVB enable cell height reduction and performance improvement.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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