Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 01/15/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryu, US 2022/0223732.
Ryu shows the invention as claimed including a semiconductor memory device comprising:
A substrate 100;
A bit-line 120 on the substrate 100, the bit-line extending in a first direction (see paragraph 0030);
A first channel pattern (left portion of channel layer 130) on the bit-line;
A second channel pattern (right portion of channel layer 130) on the bit-line and spaced apart from the first channel pattern in the first direction;
A first word-line 150A between the first channel pattern and the second channel pattern and extending in a second direction that intersects the first direction;
A second word-line 150B between the first channel pattern and the second channel pattern, the second word-line extending in the second direction and being spaced apart from the first word-line in the first direction (see figs. 2-3 and their descriptions);
A first capacitor 170A on and connected to the first channel pattern;
A second capacitor 170B on and connected to the second channel pattern, wherein:
The first channel pattern and the second channel pattern each include a first metal oxide pattern 132 and a second metal oxide pattern 134 sequentially on the bit-line (see paragraph 0041), each of the first metal oxide pattern and the second metal oxide pattern includes an amorphous metal oxide, and a composition of the first metal oxide pattern is different from a composition of the second metal oxide pattern (see paragraphs 0043-0044).
Concerning dependent claim 2, note that Ryu discloses the first word-line includes first portions and second portions alternately disposed in the second direction, and a width of each of the first portions of the first word-line in the first direction is smaller than a width of each of the second portions of the first word-line in the first direction (see fig. 1 and its description).
With respect to dependent claim 3, note that the semiconductor memory device of Ryu further comprises: the first channel pattern is closer to the first word-line than it is to the second word-line, and the first channel pattern is between adjacent second portions of the first word-line in the second direction (see figs. 1-2 and their descriptions).
As to dependent claim 4, note that in Ryu the first and second metal oxide patterns comprise IGZO and amorphous ITO, respectively (see paragraph 0044).
Regarding dependent claim 7, note that Ryu discloses the first channel pattern and the second channel pattern each further include a third metal oxide pattern between the first metal oxide and the bitline, and the third metal oxide pattern includes an amorphous metal oxide.
Concerning dependent claim 8, note that Ryu discloses a gate isolation pattern 114 on the bit-line, the gate isolation pattern separating the first word-line and the second word-line, wherein: the first channel pattern and the second channel pattern are connected to each other by a connection channel pattern, and the gate isolation pattern is on the connection channel pattern.
Regarding dependent claim 9, note that Ryu discloses a gate isolation pattern 114 in contact with the bitline 120.
With respect to dependent claim 10, note that Ryu discloses a protruding insulating pattern (first interlayer insulating layer 112) on the bitline 120, wherein the first channel pattern includes a vertical portion extending along a sidewall of the protruding insulating pattern and a horizontal portion extending along an upper surface of the bitline 120.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu, US 2022/0223732 in view of Ho et al., KR 2017-0142982.
Ryu is applied as above but does not expressly disclose a ratio of content of indium to a content of gallium in the first metal oxide pattern is smaller than a ratio of content of indium to a content of gallium in the second metal oxide pattern.
Ho et al. discloses layers of IGZO with different indium to gallium concentrations (see paragraphs 0008-0023). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Ho et al. so as to comprise different indium/gallium ratios because in such a way the particular characteristics of the device can be optimized.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu, US 2022/0223732.
Ryu is applied as above but does not expressly disclose further comprising a gate insulating film between the first channel pattern and the first word-line but does not expressly disclose wherein a height from the bitline to the uppermost surface of the gate insulaing film is larger than a height from the bitline to the uppermost surface of the first channel pattern. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum relative height of these device features based upon a variety of factors including the desired electrical characteristics and such limitation would not lend patentability to the instant invention absent a showing of unexpected results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2024/0244831 (see fig. 2) and US 2023/0371243 both show capacitor/bitline configurations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
March 5, 2026