CTNF 18/212,824 CTNF 90799 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is responsive to an Application filed on 06/22/2023. Currently, claims 1-20 are examined as below. Information Disclosure Statement Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 09/17/2024. The IDS has been considered. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2-5 and 7-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 is indefinite , because the limitation “ the conductive trench structure” in lines 2-3 is not mentioned before. Only “a conductive trench contact structure” is recited in the base claim 1. There is insufficient antecedent basis. Claim 7 is indefinite , because the limitation “ the conductive trench structure” in lines 2-3 is not mentioned before. Only “a conductive trench contact structure” is recited in the base claim 6. There is insufficient antecedent basis. Note the dependent claims 3-5 and 8-10 necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 and 6-7 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by US 2023/0015572 A1 to Khaderbad et al. (“Khaderbad”) . PNG media_image1.png 762 809 media_image1.png Greyscale PNG media_image2.png 708 842 media_image2.png Greyscale Regarding independent claim 1 , Khaderbad in Figs. 1A-1B teaches an integrated circuit structure 100 (Figs. 1A-1B, ¶ 22 & ¶ 54, semiconductor device 100 of an integrated circuit (IC)), comprising: a plurality of horizontally stacked nanowires 122 (Fig. 1B, ¶ 26, semiconductor layers 122 are nanowires); a gate stack 112 (¶ 25, gate structure 112) over the plurality of horizontally stacked nanowires 122 (Fig. 1B); and a conductive trench contact structure 142 (¶ 39, conductive contact 142) at a level below the plurality of horizontally stacked nanowires 122 (Fig. 1B, the contact 142 is in a layer which is a level below the nanowires 122), the conductive trench contact structure 142 having outwardly tapered sidewalls from a top of the conductive trench contact structure 142 to a bottom of the conductive trench contact structure 142 (Fig. 1B). Regarding claim 2 , Khaderbad in Figs. 1A-1B further teaches a dielectric plug 141 (¶ 38, low-temperature liner layer 141) laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench structure 142. Regarding independent claim 6 , Khaderbad in Figs. 1A-1B teaches an integrated circuit structure 100 (Figs. 1A-1B, ¶ 22 & ¶ 54, semiconductor device 100 of an integrated circuit (IC)), comprising: a fin 108 (Figs. 1A-1B, ¶ 25, fin structure 108); a gate stack 112 (Figs. 1A-1B, ¶ 25, gate structure 112) over the fin 108; and a conductive trench contact structure 142 (¶ 39, conductive contact 142) at a level below the fin 108 (Figs. 1A-1B, at least a portion of the structure 142 is in a layer which is a level below the fin 108), the conductive trench contact structure 142 having outwardly tapered sidewalls from a top of the conductive trench contact structure 142 to a bottom of the conductive trench contact structure 142 (Figs. 1A-1B). Regarding claim 7 , Khaderbad in Figs. 1A-1B further teaches a dielectric plug 141 (¶ 38, low-temperature liner layer 141) laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench structure 142 . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khaderbad in view of US 2021/0202696 A1 to Guha et al. (“Guha”) . Regarding independent claim 11 , Khaderbad in Figs. 1A-1B, 14 and 20 teaches a component 100 (Figs. 1A-1B, 14, ¶ 74 & ¶ 87, semiconductor structure 100 including a gate-all- around field effect transistor (GAA FET)), the component 100 including an integrated circuit structure 100 (Figs. 1A-1B, ¶ 22, ¶ 54 & ¶ 87, semiconductor device 100 of an integrated circuit (IC), which makes the IC a GAA IC), comprising: a plurality of horizontally stacked nanowires 122 (Fig. 1B, ¶ 26, semiconductor layers 122 are nanowires) or a fin 108 (Figs. 1A-1B, ¶ 25, fin structure 108); a gate stack 112 (Figs. 1A-1B, ¶ 25, ¶ 32, gate structure 112, which is a gate-all-around (GAA) structure) over the plurality of horizontally stacked nanowires 122 or the fin 108 (Figs. 1A-1B); and a conductive trench contact structure 142 (¶ 39, conductive contact 142) at a level below the plurality of horizontally stacked nanowires 122 (Fig. 1B, the contact 142 is in a layer which is a level below the nanowires 122) or the fin 108 (Figs. 1A-1B, at least a portion of the structure 142 is in a layer which is a level below the fin 108), the conductive trench contact structure 142 having outwardly tapered sidewalls from a top of the conductive trench contact structure 142 to a bottom of the conductive trench contact structure 142 (Figs. 1A-1B). However, Khaderbad does not explicitly disclose a computing device, comprising: a board; and the component coupled to the board. Guha recognizes a need for providing an electronic device that processes data (¶ 112). Guha satisfies the need by providing a computing device 900 (Fig. 9, ¶ 106, computing device 900), comprising: a board 902 (¶ 106, board 902); and a component (¶ 109-¶ 111, gate-all-around integrated circuit structure) coupled to the board 902 (Fig. 9, ¶ 106-¶ 107, ¶ 109-¶ 111). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the component taught by Khaderbad with the computing device including the board taught by Guha, so as to provide an electronic device that processes data (Guha: ¶ 112). Regarding claim 12 , Khaderbad in Fig. 1B further teaches the plurality of horizontally stacked nanowires 122. Regarding claim 13 , Khaderbad in Figs. 1A-1B further teaches the fin 108. Regarding claim 14 , the combination of Khaderbad and Guha further teaches a memory (Guha: Fig. 9, ¶ 107) coupled to the board 902. Regarding claim 15 , the combination of Khaderbad and Guha further teaches a communication chip 906 (Guha: Fig. 9, ¶ 106, communication chip 906) coupled to the board 902. Regarding claim 16 , the combination of Khaderbad and Guha further teaches a battery (Guha: Fig. 9, ¶ 107) coupled to the board 902. Regarding claim 17 , the combination of Khaderbad and Guha further teaches a camera (Guha: Fig. 9, ¶ 107) coupled to the board 902. Regarding claim 18 , the combination of Khaderbad and Guha further teaches a display (Guha: Fig. 9, ¶ 107) coupled to the board 902. Regarding claim 19 , the combination of Khaderbad and Guha further teaches the component is a packaged integrated circuit die (Guha: ¶ 109-¶ 110, ¶ 137, claim 19). Regarding claim 20 , the combination of Khaderbad and Guha further teaches the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (¶ 106-¶ 107) . Allowable Subject Matter 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claims 3-5 and 8-10 are rejected . 07-43-02 AIA Claim s 3-5 and 8-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claim 3 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 3, wherein the dielectric plug comprises a plug liner and a plug fill . Claims 4-5 would be allowable , because they depend from the allowable claim 3. Claim 8 would be allowable , because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 8, wherein the dielectric plug comprises a plug liner and a plug fill . Claims 9-10 would be allowable , because they depend from the allowable claim 8. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2020/0357930 A1 to Glass et al. relates to a gate-all-around integrated circuit structures having nanowires, in which the integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires, a gate stack is around the vertical arrangement of horizontal silicon nanowires, a first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires. US 2021/0408246 A1 to Ganguly et al. relates to a transistor device comprising a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. The transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region . Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.L./Examiner, Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817 Application/Control Number: 18/212,824 Page 2 Art Unit: 2817 Application/Control Number: 18/212,824 Page 3 Art Unit: 2817 Application/Control Number: 18/212,824 Page 4 Art Unit: 2817 Application/Control Number: 18/212,824 Page 5 Art Unit: 2817 Application/Control Number: 18/212,824 Page 6 Art Unit: 2817 Application/Control Number: 18/212,824 Page 7 Art Unit: 2817 Application/Control Number: 18/212,824 Page 8 Art Unit: 2817 Application/Control Number: 18/212,824 Page 9 Art Unit: 2817 Application/Control Number: 18/212,824 Page 10 Art Unit: 2817
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