DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 21 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on page 8 of the REMARKS, “Thus, even assuming arguendo that Shih's conductive structure 5 corresponds generally to a "conductive post," the cited reference does not disclose or suggest a conductive post having a substantially uniform thickness as recited”. Applicant further argues on page 9 of the REMARKS, “The cited references therefore do not disclose, individually or in combination, the claimed uniform- thickness conductive post structure”. The Office respectfully disagrees. The claim language has not structurally limited the conductive post nor defined the conductive post. Therefore Shih (US 2019/0035753 A1) shows (in Fig 1) a post structure (e.g. 51,52) where 51 has a substantially uniform thickness and 52 has a substantially uniform thickness. It is unclear from the claim language if only a portion of the post requires a uniform thickness. A datum of reference is not defined in the claim language to reference the thickness being claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 6, 7, 21 – 23 and 26 – 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih (US 2019/0035753 A1).
Regarding Claim 1, Shih (US 2019/0035753 A1) discloses a printed circuit (Abstract; “circuit”) board (PCB) (Fig 1) comprising: an insulating layer (3; [0046]); a first solder resist layer (6; [0048] “solder resist”) disposed on an upper surface (about 62) of the insulating layer (3); a first conductive pattern (5; [0049]) disposed on the insulating layer (6) and providing a conductive post (52; [0049-0051]) protruding from an upper surface (61) of the first solder resist layer (6), the conductive post (52) having a substantially uniform thickness (see Fig 1 showing 52 having a substantially uniform thickness or height); and wherein a thickness ([0049]) of the first solder resist layer (6) is less than a thickness (see Fig 1; [0049]) of the conductive post (52,51), and a second conductive pattern (42) buried in the insulating layer (3) and having an upper surface (upper surface of 42 and below 48) positioned to be lower than the upper surface of the insulating layer (3).
Regarding Claim 2, Shih further discloses the PCB (Fig 1) of claim 1, further comprising: a conductive via (84) connected to the first conductive pattern (5); and a third conductive pattern (86) connected to the conductive via (84) and disposed below the insulating layer (3), wherein a width of a surface (upper surface of 84) of the conductive via (84) connected to the first conductive pattern (5) is less than a width of a surface (lower surface of 84) of the conductive via (84) connected to the third conductive pattern (86).
Regarding Claim 3, Shih further discloses the PCB (Fig 1) of claim 1, further comprising: a second solder resist layer (9; [0053]) disposed below the insulating layer (3), wherein a thickness of the first solder resist layer (6) is thinner (see Fig 1 showing 9 is thicker than 6) than a thickness of the second solder resist layer (9).
Regarding Claim 6, Shih further discloses the PCB (Fig 1) of claim 1, wherein a distance between the first (5) and second (42) conductive patterns is less than a width of the first conductive pattern (5).
Regarding Claim 7, Shih further discloses the PCB (Fig 1) of claim 1, wherein a width of the first conductive pattern (5) is greater than a width of the second conductive pattern (42).
Regarding Claim 21, Shih discloses a printed circuit (Abstract, “circuit”) board (PCB) (Fig 1) comprising: an insulating layer (3; [0046]); a first conductive pattern (5) buried in the insulating layer (3); a second conductive pattern (42) buried in the insulating layer (3) and having an upper surface (upper surface of 42 and lower surface of 48) positioned to be lower than an upper surface (upper surface of 3) of the insulating layer (3); a first solder resist layer (6; [0048] “solder resist”) disposed on the insulating layer (3) to cover the second conductive pattern (42); and a conductive post (52; [0049-0051]) extending from the first conductive pattern (5) to protrude from an upper surface (at 61) of the first solder resist layer (6), wherein the conductive post (52) has a substantially uniform thickness (see Fig 1 showing 52 having a substantially uniform thickness or height), and wherein a thickness of the first solder resist (6) layer is less than a thickness ( see Fig 1; [0049]) of the conductive post (51,52).
Regarding Claim 22, Shih further discloses the PCB (Fig 1) of claim 21, wherein the conductive post (52) and the first conductive pattern (5) include a same material ([0047-0052] “copper” “integrally” “monolithic”).
Regarding Claim 23, Shih further discloses the PCB (Fig 1) of claim 21, wherein the first conductive pattern (5) and the second conductive pattern (42) are buried (see Fig 1 showing 44 and 42 are buried in 3 and the lower surface of both are at the same depth) in the insulating layer at substantially a same depth.
Regarding Claim 26, Shih further discloses the PCB (Fig 1) of claim 21, further comprising: a conductive via (84) connected to the first conductive pattern (5); and a third conductive pattern (86) connected to the conductive via (84) and disposed below the insulating layer (3), wherein a width of a surface (upper surface of 84) of the conductive via (84) connected to the first conductive pattern (5) is less than a width of a surface (lower surface of 84) of the conductive via (84) connected to the third conductive pattern (86).
Regarding Claim 27, Shih further discloses the PCB (Fig 1) of claim 21, further comprising: a second solder resist layer (9; [0053]) disposed below the insulating layer (3), wherein a thickness of the first solder resist layer (6) is thinner (see Fig 1 showing 9 is thicker than 6) than a thickness of the second solder resist layer (9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 21 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (US 2017/0094797 A1) in view of Kim (US 2015/0061143 A1).
Regarding Claim 1, Baek (US 2017/0094797 A1) discloses a printed circuit (Abstract; “circuit”) board (PCB) (Fig 1) comprising: an insulating layer (110; [0038]); a first solder resist layer (160; [0071] “solder resist”) disposed on an upper surface (about 150) of the insulating layer (110); a first conductive pattern (111,150; [0071-0072]) disposed on the insulating layer (110) and providing a conductive post (150; [0019]) protruding from an upper surface (about 161) of the first solder resist layer (160), the conductive post (150) having a substantially uniform thickness (see Fig 1 showing 150 having a substantially uniform thickness or height); and wherein a thickness (see Fig 1 showing thickness of 160 at 161) of the first solder resist layer (160) is less than a thickness (see Fig 1) of the conductive post (150), and a second conductive pattern (111) buried in the insulating layer (110).
Baek does not disclose having an upper surface positioned to be lower than the upper surface of the insulating layer.
Kim (US 2015/0061143 A1) teaches of a printed circuit board (PCB) (Fig 5-6) comprising: an insulating layer (501,601); a first solder resist layer (530; [0109] “solder resist”) disposed on an upper surface of the insulating layer (501,601); a first conductive pattern (603) disposed on the insulating layer and providing a conductive post, and a second conductive pattern (604) buried in the insulating layer (501,601) and having an upper surface positioned to be lower than the upper surface of the insulating layer (501,601).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Baek, comprising a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than the upper surface of the insulating layer as taught by Kim, in order to better prevent shorting between surface or embedded interconnects (Kim, [0011,0120-0122,0140]).
Regarding Claim 4, Baek further discloses the PCB (Fig 1) of claim 1, wherein the first solder resist layer (160) includes an opening (opening or portion of 160 which allows 150 to protrude above 160) in which the conductive post (150) is disposed, and a portion (portion of 150) of a side surface (sidewall of 150 as seen in Fig 1) of the conductive post (150) is in contact with the first solder resist layer (160).
Regarding Claim 21, Baek discloses a printed circuit (Abstract, “circuit”) board (PCB) (Fig 1) comprising: an insulating layer (110; [0038]); a first conductive pattern (111 at 150) buried in the insulating layer (110); a second conductive pattern (111 between 150 as seen centrally located in Fig 1) buried in the insulating layer (110); a first solder resist layer (160; [0071] “solder resist”) disposed on the insulating layer (110) to cover the second conductive pattern (111 between 150 as seen centrally located in Fig 1); and a conductive post (150; [0019]) extending from the first conductive pattern (111 at 150) to protrude from an upper surface (about 161) of the first solder resist layer (160), wherein the conductive post (150) has a substantially uniform thickness (see Fig 1 showing 150 having a substantially uniform thickness or height), and wherein a thickness of the first solder resist (160) layer is less than a thickness (see Fig 1 showing thickness of 160 at 161) of the conductive post (150).
Baek does not disclose the second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than an upper surface of the insulating layer.
Kim (US 2015/0061143 A1) teaches of a printed circuit board (PCB) (Fig 5-6) comprising: an insulating layer (501,601); a first solder resist layer (530; [0109] “solder resist”) disposed on an upper surface of the insulating layer (501,601); a first conductive pattern (603) disposed on the insulating layer and providing a conductive post, and a second conductive pattern (604) buried in the insulating layer (501,601) and having an upper surface positioned to be lower than the upper surface of the insulating layer (501,601).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Baek, comprising a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than an upper surface of the insulating layer as taught by Kim, in order to better prevent shorting between surface or embedded interconnects (Kim, [0011,0120-0122,0140]).
Regarding Claim 28, Baek further discloses the PCB (Fig 1) of claim 21, wherein the first solder resist layer (160) includes an opening (opening or portion of 160 which allows 150 to protrude above 160 at 161) in which the conductive post (150) is disposed, and a portion (portion of 150) of a side surface (sidewall of 150 as seen in Fig 1) of the conductive post (150) is in contact with the first solder resist layer (160).
Claim(s) 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Buot (US 2021/0287976 A1) in view of Baek (US 2017/0094797 A1).
Regarding Claim 1, Buot (US 2021/0287976 A1) discloses a printed circuit board (PCB) (Fig 1) comprising: an insulating layer (102; [0015]); a first solder resist layer (104; [0015]) disposed on an upper surface (upper surface of 102) of the insulating layer (102); a first conductive pattern (M1 at 114) disposed on the insulating layer (102); and a second conductive pattern (110) buried in the insulating layer (102) and having an upper surface (upper surface of 110) positioned to be lower than the upper surface of the insulating layer (102).
Buot does not disclose providing a conductive post protruding from an upper surface of the first solder resist layer, the conductive post having a substantially uniform thickness; and wherein a thickness of the first solder resist is less than a thickness of the conductive post.
Baek (US 2017/0094797 A1) discloses a printed circuit (Abstract; “circuit”) board (PCB) (Fig 1) comprising: an insulating layer (110; [0038]); a first solder resist layer (160; [0071] “solder resist”) disposed on an upper surface (about 150) of the insulating layer (110); a first conductive pattern (111,150; [0071-0072]) disposed on the insulating layer (110) and providing a conductive post (150; [0019]) protruding from an upper surface (about 161) of the first solder resist layer (160), the conductive post (150) having a substantially uniform thickness (see Fig 1 showing 150 having a substantially uniform thickness or height); and wherein a thickness (see Fig 1 showing thickness of 160 at 161) of the first solder resist layer (160) is less than a thickness (see Fig 1) of the conductive post (150), and a second conductive pattern (111) buried in the insulating layer (110).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Buot, providing a conductive post protruding from an upper surface of the first solder resist layer, the conductive post having a substantially uniform thickness; and wherein a thickness of the first solder resist is less than a thickness of the conductive post as taught by Baek, in order to provide a terminal for external connections while also preventing unwanted shorting or bridging (Baek, [0068-0074]).
Regarding Claim 5, Buot in view of Baek teaches the limitations of the preceding claim and Buot further discloses the PCB (Fig 1) of claim 1, wherein the insulating layer (102) includes a recessed portion (portion of 102 is showing a recessed region or portion about 110), and a portion of the first solder resist layer (104) and the second conductive pattern (110) contact each other (see Fig 1 showing 104 contacting the recessed 110 within M1) in the recessed portion.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 2019/0035753 A1) as applied to claim 1 above and further in view of Huemoeller (US 8,704,369 B1).
Regarding Claim 8, Shih further discloses the PCB (Fig 1) of claim 1, further comprising a semiconductor chip ([0042-0044] “pillar can be connected to the semiconductor chip”) connected to the conductive post (51,52).
Shih does not explicitly disclose a flip-chip structure.
Huemoeller (US 8,704,369 B1) teaches of a board (Fig 11) comprising a chip (1140) connected to conductive post (630) in a flip-chip structure (see Fig 11).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board with semiconductor chip as disclosed by Shih, further comprising a semiconductor chip connected to the conductive post in a flip-chip structure as taught by Huemoeller, in order to allow solder to be directly applied to pad, to provide reliability, and to provide a means that is extremely well-suited for high-density substrates (Huemoeller, Column 1, lines 25-64,Column 3, lines 30-49,Column 7, lines 40-56).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896
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