DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claims 1 and 21 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: previously withdrawn claim 25 was referencing unelected species with respect to Figure 6. As seen in Applicant’s Specification ([0025]), Applicant Specification is referencing another example, where the side surface of the post has a constant slope. Slope is defined (see Slope - definition of slope by The Free Dictionary) as an incline or slanting, i.e. the configuration as shown in unelected Figure 6. As seen in Figure 1J, the side surface of the conductive post does not have a slope. However Figure 6 shows the conductive post having a side surface with a constant slope.
[0025] A portion of the protective pattern 117 and the first conductive layer 132 that does not vertically overlap the etch stop pattern 133 may be etched. Accordingly, an unfinished PCB 100j may include a conductive post 134 vertically overlapping the etch stop pattern 133. The forming of the conductive post 134 may include forming the conductive posts 134 on an upper surface of the first conductive pattern 125. In one example, a side surface of the conductive post 134 may have a substantially constant slope with respect to the upper surface of the insulating layer 112. The configuration in which the side surface of the conductive post 134 may have a substantially constant slope with respect to the upper surface of the insulating layer 112 may include the example in which the side surface of the conductive post 134 may have a constant slope with respect to the upper surface of the insulating layer 112, and also the example in which a minute deviation in slope may exist due to a process error occurring in the manufacturing process, a measurement error, or the like, recognizable by one of ordinary skill in the art.
Since Applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 1 and 21 should be withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. In order to speed prosecution, the Office is providing a reference showing a post having a constant slope.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 21 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 3, 5 – 8, 21 – 23, 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Moran (US 2009/0148594 A1) in view of Kim (US 2015/0061143 A1).
Regarding Claim 1, Moran (US 2009/0148594 A1) discloses a printed circuit board (PCB) (Fig 1-14A) comprising: an insulating layer (132); a first solder resist layer (156; [0049]) disposed on an upper surface (176) of the insulating layer (132); a first conductive pattern (133) disposed on the insulating layer (132) and providing a conductive post (130; [0038]) protruding from an upper surface of the first solder resist layer (156), the conductive post having a substantially uniform thickness (see height of 130 in Fig 13A); and wherein a thickness of the first solder resist layer (156) is less than a thickness (see height of 130 in Fig 13A) of the conductive post (130), and a second conductive pattern (250,252) buried in the insulating layer (132), the first solder resist layer (156) includes an opening (opening or space in 156 allowing 130a-130d to protrude) in which the conductive post (130) is disposed, and a portion of a side surface (side surface of 130) of the conductive post (130) is in contact (see Fig 13A) with the first solder resist layer (156), and the side surface of the conductive post (130) has a substantially constant slope (see Fig 13A; [0033] “sloped”) with respect to the upper surface of insulating layer (132).
Moran does not disclose having an upper surface positioned to be lower than the upper surface of the insulating layer.
Kim (US 2015/0061143 A1) teaches of a printed circuit board (PCB) (Fig 13) comprising: an insulating layer (1301); a first solder resist layer (1340; [0152-0158] “solder resist”) disposed on an upper surface of the insulating layer (1301); a first conductive pattern (1310) disposed on the insulating layer and providing a conductive post, and a second conductive pattern (1305,1307) buried in the insulating layer (1301) and having an upper surface positioned to be lower than the upper surface of the insulating layer (1301).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Moran, comprising a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than the upper surface of the insulating layer as taught by Kim, in order to better prevent shorting between surface or embedded interconnects (Kim, [0011,0120-0122,0140]).
Regarding Claim 2, Moran further discloses the PCB (Fig 1-14A) of claim 1, further comprising: a conductive via (136) connected to the first conductive pattern; and a third conductive pattern (138) connected to the conductive via (136) and disposed below the insulating layer (132), wherein a width of a surface (upper surface of 136) of the conductive via (136) connected to the first conductive pattern (133) is less than a width of a surface (lower surface of 136) of the conductive via (136) connected to the third conductive pattern (138).
Regarding Claim 3, Moran further discloses the PCB (Fig 1-14A) of claim 1, further comprising: a second solder resist layer (158; [0049]) disposed below the insulating layer (132), wherein a thickness of the first solder resist layer (156) is thinner (see Fig 13A showing 158 is thicker than 156) than a thickness of the second solder resist layer (158).
Regarding Claim 5, Moran in view of Kim teaches the limitations of the preceding claim and Kim further teaches the PCB (Fig 13) of claim 1, wherein the insulating layer (1301) includes a recessed portion (portion of 1301 is showing a recessed region or portion about 1305), and a portion of the first solder resist layer (1340) and the second conductive pattern (1305) contact each other (see Fig 13; [0159]) in the recessed portion.
Regarding Claim 6, Moran further discloses the PCB (Fig 1-14A) of claim 1, wherein a distance between (see Fig 13A) the first (133) and second (250,252) conductive patterns is less than a width of the first conductive pattern (133).
Regarding Claim 7, Moran further discloses the PCB (Fig 1-14A) of claim 1, wherein a width of the first conductive pattern (133) is greater than a width of the second conductive pattern (250).
Regarding Claim 8, Moran further discloses the PCB (Fig 1-14A) of claim 1, further comprising a semiconductor chip (172; [0053]) connected to the conductive post (130) in a flip-chip structure (see Fig 14A; [0053]).
Regarding Claim 21, Moran discloses a printed circuit board (PCB) (Fig 1-14A) comprising: an insulating layer (132); a first conductive pattern (133) buried in the insulating layer (132); a second conductive pattern (250,252) buried in the insulating layer (132); a first solder resist layer (156; [0049]) disposed on the insulating layer (132) to cover the second conductive pattern (250,252); and a conductive post (130; [0038]) extending from the first conductive pattern (133) to protrude from an upper surface of the first solder resist layer (156), wherein the conductive post (130) has a substantially uniform thickness (see 130 in Fig 13A), and wherein a thickness of the first solder resist layer (156) is less than a thickness of the conductive post (130), the first solder resist layer (156) includes an opening (opening or space in 156 allowing 130a-130d to protrude) in which the conductive post (130) is disposed, and a portion of a side surface (side surface of 130) of the conductive post (130) is in contact (see Fig 13A) with the first solder resist layer (156), and the side surface (side surface of 130) of the conductive post (130) has a substantially constant slope (see Fig 13A; [0033] “sloped”) with respect to the upper surface of insulating layer (132).
Moran does not disclose having an upper surface positioned to be lower than the upper surface of the insulating layer.
Kim (US 2015/0061143 A1) teaches of a printed circuit board (PCB) (Fig 13) comprising: an insulating layer (1301); a first solder resist layer (1340; [0152-0158] “solder resist”) disposed on an upper surface of the insulating layer (1301); a first conductive pattern (1310) disposed on the insulating layer and providing a conductive post, and a second conductive pattern (1305,1307) buried in the insulating layer (1301) and having an upper surface positioned to be lower than the upper surface of the insulating layer (1301).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Moran, comprising a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than the upper surface of the insulating layer as taught by Kim, in order to better prevent shorting between surface or embedded interconnects (Kim, [0011,0120-0122,0140]).
Regarding Claim 22, Moran further discloses the PCB (Fig 1-14A) of claim 21, wherein the conductive post (130) and the first conductive pattern (133) include a same material ([0037] “copper”).
Regarding Claim 23, Moran further discloses the PCB (Fig 1-14A) of claim 21, wherein the first conductive pattern (133) and the second conductive pattern (250,252) are buried (see Fig 13A showing 133,250 are buried in 132) in the insulating layer (130) at substantially a same depth (see Fig 13A).
Regarding Claim 26, Moran further discloses the PCB (Fig 1-14A) of claim 21, further comprising: a conductive via (136) connected to the first conductive pattern (133); and a third conductive pattern (138) connected to the conductive via (136) and disposed below the insulating layer (132), wherein a width of a surface (upper surface of 136) of the conductive via (136) connected to the first conductive pattern (133) is less than a width of a surface (lower surface of 136) of the conductive via (136) connected to the third conductive pattern (138).
Regarding Claim 27, Moran further discloses the PCB (Fig 1-14A) of claim 21, further comprising: a second solder resist layer (158; [0049]) disposed below the insulating layer (132), wherein a thickness of the first solder resist layer (132) is thinner (see Fig 13A showing 158 is thicker than 156) than a thickness of the second solder resist layer (158).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
Prosecution Insights