DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 12/17/2025 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments have overcome each claim objections previously set forth in the Non-Final Office Action mailed on 08/22/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Petzold et al., (United States Patent Application Publication Number, US 2016/0336278 A1) hereinafter referenced as Petzold, in view of Stuber et al., (United States Patent Number, US 8,232,597 B2) hereinafter referenced as Stuber, and in view of Costa (United States Patent Application Publication Number, US 2015/0255368 A1), hereinafter referenced as Costa.
Regarding claim 1, Petzold teaches an integrated device die comprising: a substrate having a first side and a second side opposite the first side (Fig.11, element #106, first side is the top side and second side is the bottom side); a buried oxide layer over the first side of the substrate (Fig.11, element #104), the buried oxide layer having a through via in contact with the first side of the substrate (Fig.11, element #108 located on the left side of element #102) a heat generating electronic component disposed over the buried oxide layer (Fig.11, element #102 is over element #104, laterally offset from element #108 and is a transistor as shown in Fig.14A), the heat generating electronic component laterally offset from the through via (Fig.11, element #102 is laterally offset from the through via); a dielectric layer disposed over the heat generating electronic component (Fig.11, element #114), a surface of the dielectric layer faces away from the buried oxide layer including a terminal (Fig.11, the top surface of element #114 includes terminal, element #112), electrically connected to the heat generating electronic component and laterally offset from the heat generating electronic component (Fig.21, element #112, is electrically connected to element #150 which is equivalent to element #102 in Fig.11, paragraph [0191], rows 5-7, and laterally offset from the heat generating electronic component)
Petzold teaches a silicon layer between the through via and the dielectric layer (Fig.13, element #115). Petzold does not teach a first active region between the through via and the dielectric layer. Stuber teaches a first active region between the through via and the dielectric layer (Fig.3, active region, formed by elements #302 and #301, is located between the via in the buried oxide layer, element #102 and the dielectric layer, element #103, column 6, rows 42-45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Stuber and disclose a first active region between the through via and the dielectric layer. As disclosed by Stuber, the active region can be part of a diode that can help latch the body to the gate of the electronic components (column 6, rows 49-54). We note that Petzold also discloses a diode that connects the body to the gate of the electronic component (Fig.54A).
Petzold discloses a second buried oxide layer through via laterally offset from the heat generating electronic component (Fig.11, element #108 located on the right side of element #102), where the second via is part of the same substrate bias network as the first via (Fig.15). Therefore, it would have been obvious to have second active region between the second through via and the dielectric layer, which is also located between the oxide layer and the dielectric layer, similar to the first active region disclosed by Stuber. Without this active region, the connection between the gate of the electronic component and the second via would shunt the diode (first active region is part of a diode as noted above) located between the first via and the gate, and render it useless. The second active region would be similar to the first active region, laterally offset from the heat generating electronic component. Therefore, the combination of Petzold and Stuber teaches a second active region between the buried oxide layer and the dielectric layer, the second active region laterally offset from the through via and laterally offset from the heat generating electronic component.
Petzold further teaches a thermally conductive structure formed within the dielectric layer and positioned between the buried oxide layer and the terminal (Fig.11, element #110, is made of metal and therefore thermally conductive), the thermally conductive structure in thermal contact with the first active region, the second active region, and the heat generating electronic component (element #110 is connected to the heat generating electronic component and to the vias, though the active regions disclosed by Stuber). Petzold does not explicitly disclose the thermally conductive structure to provide at least three thermal pathways between the heat generating electronic component and the terminal. However, since the element #110 is thermally conductive and in contact with the electronic component, this will provide a first thermal pathway. Furthermore, Costa discloses two thermal pathways going from the heat generating electronic component through the buried oxide layer, the substrate and the metallization structure (Fig.6). Since both Petzold and Costa disclose a similar layer structure, the two thermal pathway, that go through the buried oxide layer and the two through vias, should also exist.
Regarding claim 2, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 1 wherein the heat generating electronic component is a transistor or a resistor (Fig.21, element #150 which is equivalent to element #102 in Fig.11, is a transistor).
Regarding claim 3, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 1 wherein the thermally conductive structure is formed on an active region at or near a surface of the dielectric layer that faces the substrate (Fig.11, element #110 is formed on the active Si, element #102, located near the bottom surface of the dielectric layer, which faces the substrate, element #106).
Regarding claim 4, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Stuber further teaches the wherein the first active region is a silicon pot (column 6, rows 45-49). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Stuber and disclose wherein the first active region is a silicon pot. As disclosed by Stuber, thin film processes allow one to manufacture an active device, a diode, in the thin film (column 6, rows 46-49), and the diode can help latch the body to the gate of the electronic components (column 6, rows 49-54). We note that Petzold also discloses a diode that connects the body to the gate of the electronic component (Fig.54A).
Regarding claim 5, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Stuber further teaches the integrated device die of claim 1 wherein the first active region is a doped region (Fig.3, active region, formed by elements #302 and #301 is a doped region, column 6, rows 42-45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Stuber and disclose the first active region is a doped region. As disclosed by Stuber, the active region can be part of a diode that can help latch the body to the gate of the electronic components (column 6, rows 49-54).
Regarding claim 6, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 1 wherein the thermally conductive structure includes metal vias that extend at least partially through a thickness of the dielectric layer (Fig.11, element #110 includes vias extending through dielectric layer, element #114).
Regarding claim 7, the combination of Petzold, Stuber and Costa teaches the integrated device die of claims 1 and 6 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 6 wherein the thermally conductive structure also includes metal traces that extend laterally through a portion of the dielectric layer (Fig.11, element #110 includes metal traces extending laterally through dielectric layer, element #114).
Regarding claim 8, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 1 wherein the surface of the dielectric layer that faces away from the substrate further includes a second terminal laterally offset from the terminal, the second terminal is configured to connect to a heatsink (Fig.12, element #113, has the top surface exposed and therefore, can be connected to a heatsink).
Regarding claim 9, the combination of Petzold, Stuber and Costa teaches the integrated device die of claims 1 and 8 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 8 further comprising a second thermally conductive structure positioned between the second terminal and the substrate (Fig.12, a metallization structure, therefore thermally conductive, is present between second terminal element #113 and the substrate, element #106).
Regarding claim 10, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 1 wherein the terminal is configured to connect to a heatsink (Fig.6, element #112 has the top surface exposed and therefore, can be connected to a heatsink).
Claims 11, 12, 14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Petzold in view of Stuber, Costa and in view of Kanda et al., (United States Patent Number, US 9,543,228 B2) hereinafter referenced as Kanda.
Regarding claim 11, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. Petzold further teaches the substrate is made of silicon (paragraph [0139], rows 4-6). The combination of Petzold, Stuber and Costa does not teach the material used for the dielectric layer and therefore it does not teach the thermal conductivity of the dielectric layer. Kanda teaches wherein the substrate is made of silicon and the dielectric layer is made of silicon oxide (substrate element #21 is silicon, column 3, row 25, and dielectric is silicon oxide, column 3, row 45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kanda and disclose the dielectric layer is made of silicon oxide. Silicon oxide is a very common material used in the semiconductor industry to separate BEOL metal layers and therefore a prima facie case of obviousness exists (MPEP 2144.03). Given the material properties of silicon and silicon dioxide, the combination of Petzold, Stuber, Costa and Kanda teaches a thermal conductivity of the substrate is greater than a thermal conductivity of the dielectric layer.
Regarding claim 12, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection and the combination of Petzold, Stuber, Costa and Kanda teaches the integrated device die of claim 11 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 11 wherein the substrate is a silicon substrate (paragraph [0139], rows 4-6).
Regarding claim 14, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. The combination of Petzold, Stuber and Costa does not teach the integrated device die of claim 1 wherein the thermally conductive structure includes pieces of a conductive material, a density of the conductive material relative to a material of the dielectric layer in the thermally conductive structure is more than 50%. Kanda teaches wherein the thermally conductive structure (Fig.1, element #20H) includes pieces of a conductive material (Fig.1, elements #24h-28h and #24H-28H, column 5, rows 5-10), a density of the conductive material relative to a material of the dielectric layer in the thermally conductive structure is more than 50% (column 5, rows 60-63, therefore the combined density of elements #24h-28h and #24H-28H is more than 50% relative to the dielectric layer between them even after including openings OP). The claimed range overlaps the range disclosed by Kanda and therefore a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 16, Petzold teaches an electronic system comprising: an integrated device die including a substrate (Fig.11, element #106), an insulation layer having a through via in contact with the substrate (Fig.11, element #104 has a through via, element #108 in contact with element #106), a heat generating electronic component over the insulation layer, the heat generating electronic component laterally offset from the through via (Fig.11, element #102 is over element #104, laterally offset from element #108 and is a transistor as shown in Fig.14A), a dielectric layer disposed over the heat generating electronic component (Fig.11, element #114), and a thermally conductive structure formed within the dielectric layer (Fig.11, element #110, is made of metal and therefore thermally conductive), a surface of the dielectric layer that faces away from the insulation layer including a terminal (Fig.11, the top surface of element #114 includes terminal, element #112), electrically connected to the heat generating electronic component and laterally offset from the heat generating electronic component (Fig.21, element #112, is electrically connected to element #150 which is equivalent to element #102 in Fig.11, paragraph [0191], rows 5-7, and laterally offset from the heat generating electronic component).
Petzold teaches a silicon layer between the through via and the dielectric layer (Fig.13, element #115). Petzold does not teach a first active region between the through via and the dielectric layer. Stuber teaches a first active region between the through via and the dielectric layer (Fig.3, active region, formed by elements #302 and #301, is located between the via in the insulation layer, element #102 and the dielectric layer, element #103, column 6, rows 42-45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Stuber and disclose a first active region between the through via and the dielectric layer. As disclosed by Stuber, the active region can be part of a diode that can help latch the body to the gate of the electronic components (column 6, rows 49-54). We note that Petzold also discloses a diode that connects the body to the gate of the electronic component (Fig.54A).
Petzold discloses a second buried oxide layer through via laterally offset from the heat generating electronic component (Fig.11, element #108 located on the right side of element #102), where the second via is part of the same substrate bias network as the first via (Fig.15). Therefore, it would have been obvious to have second active region between the second through via and the dielectric layer, which is also located between the insulation layer and the dielectric layer, similar to the first active region disclosed by Stuber. Without this active region, the connection between the gate of the electronic component and the second via would shunt the diode (first active region is part of a diode as noted above) located between the first via and the gate, and render it useless. The second active region would be similar to the first active region, laterally offset from the heat generating electronic component. Therefore, the combination of Petzold and Stuber teaches a second active region between the insulation layer and the dielectric layer, the second active region laterally offset from the through via and laterally offset from the heat generating electronic component.
Petzold further teaches a thermally conductive structure formed within the dielectric layer (Fig.11, element #110) in thermal contact with the first active region, the second active region, and the heat generating electronic component (element #110 is connected to the heat generating electronic component and to the vias, though the active regions disclosed by Stuber). Petzold does not explicitly disclose the thermally conductive structure to provide at least three thermal pathways between the heat generating electronic component and the terminal. However, since the element #110 is thermally conductive and in contact with the electronic component, this will provide a first thermal pathway. Furthermore, Costa discloses two thermal pathways going from the heat generating electronic component through the buried oxide layer, the substrate and the metallization structure (Fig.6). Since both Petzold and Costa disclose a similar layer structure, the two thermal pathway, that go through the buried oxide layer and the two through vias, should also exist.
The combination of Petzold, Stuber and Costa does not teach a heatsink coupled with the terminal by way of a thermally conductive material. Kanda teaches a heatsink (Fig.7, element #11, column 5, rows 45-46) coupled with the terminal (Fig.7, element #28H, column 5, row 43) by way of a thermally conductive material (Fig.7, element #30H, column 5, row 44). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kanda and disclose a heatsink coupled with the terminal by way of a thermally conductive material. As disclosed by Kanda, the heat sink conducts the heat generated by the transistor and thus provides an efficient heat dissipation away from it.
Regarding claim 17, the combination of Petzold, Stuber, Costa and Kanda teaches the integrated device die of claim 16 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 1 wherein the heat generating electronic component is a transistor or a resistor (Fig.14A, element #102 is a transistor).
Regarding claim 18, the combination of Petzold, Stuber, Costa and Kanda teaches the integrated device die of claim 16 as set forth in the obviousness rejection. Petzold further teaches the integrated device die of claim 16 wherein the thermally conductive structure is formed on an active region at or near a surface of the dielectric layer that faces the substrate (Fig.11, element #110 is formed on the active Si, element #102, located near the bottom surface of the dielectric layer, which faces the substrate, element #106).
Regarding claim 19, the combination of Petzold, Stuber, Costa and Kanda teaches the integrated device die of claim 16 as set forth in the obviousness rejection. Stuber further teaches the integrated device die of claim 16 wherein the first active region is a silicon pot (column 6, rows 45-49). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Stuber and disclose wherein the first active region is a silicon pot. As disclosed by Stuber, thin film processes allow one to manufacture an active device, a diode, in the thin film (column 6, rows 46-49), and the diode can help latch the body to the gate of the electronic components(column 6, rows 49-54). We note that Petzold also discloses a diode that connects the body to the gate of the electronic component (Fig.54A).
Regarding claim 20, the combination of Petzold, Stuber, Costa and Kanda teaches the integrated device die of claim 16 as set forth in the obviousness rejection. Stuber further teaches the integrated device die of claim 16 wherein the first active region is a doped region (Fig.3, active region, formed by elements #302 and #301 is a doped region, column 6, rows 42-45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Stuber and disclose the first active region is a doped region. As disclosed by Stuber, the active region can be part of a diode that can help latch the body to the gate of the electronic components (column 6, rows 49-54).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Petzold in view of Stuber, Costa and in view Yoshioka, (United States Patent Application Publication Number, US 2009/0044162 A1) hereinafter referenced as Yoshioka.
Regarding claim 13, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. The combination of Petzold, Stuber and costa does not teach the integrated device die of claim 1 further comprising a second thermally conductive structure disposed laterally between the heat generating electronic component and the thermally conductive structure. Yoshioka teaches an integrated device die comprising a second thermally conductive structure disposed laterally between the heat generating electronic component and the thermally conductive structure (Fig.7, below each conductive part element #55 there is a conductive structure, and in Fig.9, the conductive structure below element #55 second from left to right is between the conductive structure below the element #55 first from left to right and heat generating electronic component of inverter cell B). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yoshioka and disclose a second thermally conductive structure disposed laterally between the heat generating electronic component and the thermally conductive structure. As disclosed by Yoshioka, providing the second thermally conductive structure disposed laterally between the heat generating electronic component and the thermally conductive structure device allows the manufacture of an integrated circuit that can release heat through the thermally conductive structure, without modification of the cells where the generating electronic device resides (paragraph [0095], rows 8-13), while having multiple thermally conductive structures, can increase heat dissipation for the same cell of different cells disposed laterally (Fig.9).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Petzold in view of Stuber, Costa and in view of Deeter et al., (United States Patent Application Publication Number, US 6,646,340 B2) hereinafter referenced as Deeter.
Regarding claim 15, the combination of Petzold, Stuber and Costa teaches the integrated device die of claim 1 as set forth in the obviousness rejection. The combination of Petzold, Stuber and Costa does not teach the integrated device die of claim 1 wherein the thermally conductive structure includes disconnected portions spaced apart by a portion of the dielectric layer. Deeter teaches the integrated device die of claim 1 wherein the thermally conductive structure includes disconnected portions spaced apart by a portion of the dielectric layer (Fig.7, thermally conductive line #720 and thermally conductive via, element #730, are separated by dielectric #755; element #725 is optional, similar to element #425, column 6, row 56-57). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Deeter and disclose the thermally conductive structure includes disconnected portions spaced apart by a portion of the dielectric layer. As disclosed by Deeter, this allows heat dissipation from the heat generation parts of the die while keeping them at different electrical potentials (i.e. not shorting them).
Response to Arguments
Applicant’s arguments filed on 12/17/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899