DETAILED ACTION
This Notice is responsive to communication filed on 02/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, reading on Fig. 13 and Sub-Species A, reading on Fig. 4 in the reply filed on 02/11/2026 is acknowledged.
Claims 2, 10, 11, 21-25, and 28-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/11/2026.
Applicant's election with traverse of Sub-Species J, K, and L, reading on Fig. 14, 15, and 16 in the reply filed on 02/11/2026 is acknowledged. The traversal is on the ground(s) that groups of the identified subspecies show combined connections between upper test pads and lower test pads, i.e. Fig. 8 shows the lower test pads BTP and their connections TWP1 for Fig. 7, and Fig. 9 shows the upper test pads TTP and their connections TWP2 for Fig. 7 as well. This is found persuasive. Therefore, Applicant’s election of SubSpecies J-L is deemed an appropriate election of the Subspecies II Restriction Requirement.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/23/23 and 04/09/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 8, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20120097944).
Regarding claim 1, Lin teaches a semiconductor package, comprising:
a substrate Fig. 1: 20 (para. 0019);
a first semiconductor chip Fig. 5A: 510 (corresponding to Fig. 1: A) on the substrate Fig. 1: 20, the first semiconductor chip Fig. 5A: 510 including a first semiconductor substrate Fig. 5A: 510 (para. 0038) and a first test pattern Fig. 5A: 511-514, 530 on a first surface of the first semiconductor substrate Fig. 5A: 510; and
a second semiconductor chip Fig. 5A: 520 (corresponding to Fig. 1: B) on the first semiconductor chip Fig. 5A: 510, the second semiconductor chip Fig. 5A: 520 including a second semiconductor substrate Fig. 5A: 520 and a second test pattern Fig. 5A: 521-524, 525 on a second surface of the second semiconductor substrate Fig. 5A: 520,
wherein the second semiconductor chip Fig. 5A: 520 and the first semiconductor chip Fig. 5A: 510 are bonded to each other to allow the first test pattern Fig. 5A: 511-514, 530 to face the second test pattern Fig. 5A: 521-524, 525 (para. 0038, 0041),
wherein the first test pattern Fig. 5A: 511-514, 530 includes a first in-pad, first connection pads, and a first out-pad that are arranged in a plurality of rows and columns (i.e. in-pad 511, out-pad 514, connection pads 512 and 513; Fig. 4A/4B para 0034 also show test pads 401-405 considered in-pads, out-pads, and connection pads),
wherein the second test pattern Fig. 5A: 521-524, 525 includes a second in-pad bonded to the first in-pad, a second out-pad bonded to the first out-pad, and second connection pads bonded to the first connection pads (i.e. in-pad 521, out-pad 524, connection pads 522 and 523; Fig. 4A/4B para 0034 also show test pads 401-405 considered in-pads, out-pads, and connection pads), and
wherein the first connection pads Fig. 5A: 512-513 and the second connection pads Fig. 5A: 522-523 are connected in series to alternately connect with each other and form a series wiring pattern, so that each first connection pad connects to another first connection pad in one direction along the series wiring pattern and to a second connection pad in an opposite direction along the series wiring pattern (Fig. 4A/4B show a series wiring pattern).
Regarding claim 4, Lin teaches the semiconductor package of claim 1, wherein: the second in-pad Fig. 5A: 521 is electrically connected to one of the second connection pads Fig. 5A: 522 (para. 0038), and the second out-pad Fig. 5A: 524 is electrically connected to another one of the second connection pads Fig. 5A: 523 (para. 0038 teaches redistribution structures, such as structure 525 to connect bumps).
Regarding claim 5, Lin teaches the semiconductor package of claim 1, wherein each of the first and second connection pads has a circular planar shape, a tetragonal planar shape, or polygonal planar shape (Fig. 5A shows a circular shape of i.e. 511, while Fig. 4A/4B show a polygonal shape of i.e. 401).
Regarding claim 6, Lin teaches the semiconductor package of claim 1, wherein: on the first surface of the first semiconductor substrate Fig. 6: 610, the first test pattern Fig. 6: 650 is adjacent to a corner of the first semiconductor substrate Fig. 6: 610, and on the second surface of the second semiconductor substrate Fig. 6: 620, the second test pattern is adjacent to a corner of the second semiconductor substrate Fig. 6: 620 (item 650 corresponding to substrate 620).
Regarding claim 8, Lin teaches the semiconductor package of claim 1, wherein: the first semiconductor chip Fig. 5A: 510 further includes a first through via Fig. 5A: 504 that vertically penetrates the first semiconductor substrate Fig. 5A: 510, the first through via Fig. 5A: 504 being connected to the first out-pad Fig. 5A: 514, and the second semiconductor chip Fig. 5A: 520 further includes a second through via that vertically penetrates the second semiconductor substrate Fig. 5A: 520, the second through via being connected to the second in-pad Fig. 5A: 521 (also shown in Fig. 1: 40 corresponding to Fig. 1: B; para. 0038 teaches TSVs in substrate 520).
Regarding claim 12, Lin teaches the semiconductor package of claim 1, wherein: the first in-pad and the second in-pad are bonded to each other, the first in-pad and the second in-pad constituting a single unitary piece formed of the same material, the first out-pad and the second out-pad are bonded to each other, the first out-pad and the second out-pad constituting a single unitary piece formed of the same material, and the first connection pads and the second connection pads are bonded to each other, each first connection pad and corresponding second connection pad constituting a single unitary piece formed of the same material. Fig. 1 discloses the pads between the first semiconductor chip Fig. 1: A and the second semiconductor chip Fig. 1: B are a unitary piece formed of the same material (para. 0019).
Regarding claim 13, Lin teaches the semiconductor package of claim 1, wherein: the first surface of the first semiconductor chip Fig. 5A: 510 is flat and coplanar with a top surface of the first test pattern Fig. 5A: 511-514, 530 (i.e. top surface of 510 and 530 are flat and coplanar), and the second surface of the second semiconductor chip Fig. 5A: 520 is flat and coplanar with a bottom surface of the second test pattern Fig. 5A: 521-524, 525 (i.e. bottom surface of 510 is flat and coplanar with bottom surface of 525).
Claim 27 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 9653430).
Regarding claim 27, Kim teaches a semiconductor package, comprising:
a substrate Fig. 4B: 300;
semiconductor chips Fig. 4B: 912 stacked on the substrate Fig. 4B: 300; and
a molding layer Fig. 4B: 90 on the substrate Fig. 4B: 300, the molding layer surrounding the semiconductor chips Fig. 4B: 912,
wherein each of the semiconductor chips Fig. 4B: 912 includes:
a semiconductor substrate Fig. 4B: 911 having a first surface (top surface) and a second surface (bottom surface) that are opposite to each other;
a semiconductor element Fig. 4B: 400 on the first surface of the semiconductor substrate Fig. 4B: 911;
first signal pads and first test pads on the first surface of the semiconductor substrate (annotated);
second signal pads and second test pads on the second surface of the semiconductor substrate (annotated);
first vias that vertically penetrate the semiconductor substrate, the first vias connecting the first signal pads to the second signal pads (annotated); and
second vias that vertically penetrate the semiconductor substrate, the second vias connecting respective ones of the first test pads to ones of the second test pads (annotated),
wherein two neighboring ones of the semiconductor chips Fig. 4B: 911 are bonded to each other (bonded to Fig. 4B: 913), the first signal pads and the second signal pads contact each other, and the first test pads and the second test pads contact each other (shown in Fig. 4B),
wherein the first and second signal pads are on a central region of the semiconductor substrate (see annotated signal pads below),
wherein the first and second test pads are on a test region between the central region and a corner of the semiconductor substrate (see annotated signal pads below), and
wherein the first and second test pads are connected in series and alternately connected with each other (shown in Fig. 8B; via 180/280).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120097944) as applied to claim 1 above, and further in view of Lu et al. (US 20220336299).
Regarding claim 3, although Lin teaches the substantial elements of the claimed invention, Lin fails to explicitly teach the semiconductor package of claim 1, wherein each of the first connection pads is disposed to simultaneously overlap two neighboring ones of the second connection pads, such that each of the first connection pads is bonded to two overlapping neighboring ones of the second connection pads. However, Lu teaches wherein each of the first connection pads Fig. 2: 206 is disposed to simultaneously overlap two neighboring ones of the second connection pads Fig. 2: 214, such that each of the first connection pads Fig. 2: 206 is bonded to two overlapping neighboring ones of the second connection pads Fig. 2: 214. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lin and Lu for the purpose of creating a daisy chain seal ring structure to reduce/prevent wafer cracking (para. 0016, 0036-0037).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120097944) as applied to claim 1 above, and further in view of Kim et al. (US 20130221493 A1).
Regarding claim 7, although Lin teaches the substantial features of the claimed invention, Lin fails to explicitly teach the semiconductor package of claim 1, wherein: each of the second in-pad, the second connection pads, and the second out-pad has a width of about 2 µm to about 50 µm, and each of the second in-pad, the second connection pads, and the second out-pad has a width of about 2 µm to about 50 µm. However, Kim teaches wherein: each of the second in-pad, the second connection pads, and the second out-pad has a width of about 2 µm to about 50 µm, and each of the second in-pad, the second connection pads, and the second out-pad has a width of about 2 µm to about 50 µm. Kim teaches conductive test pads Fig. 3: 170, 175 in a standard width in a range between 10µm – 70µm which includes the claimed range (para. 0112). Therefore, it would have been obvious to one of skill in the art before the effective filing date to combine the teachings of Lin and Kim. A change in size is a matter of design choice, which a person within the level of ordinary skill in the art would have found to be obvious about persuasive evidence that the particular configuration of the claimed areas was significant, and a change in size is generally recognized as being within the level of ordinary skill in the art. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120097944) as applied to claim 1 above, and further in view of Chang (US 20220344223 A1).
Regarding claim 9, Lin teaches the semiconductor package of claim 1, wherein: the first semiconductor chip Fig. 1: A further includes a first semiconductor element Fig. 1: 30 at a bottom surface of the first semiconductor substrate Fig. 1: A, but Lin fails to explicitly teach the first test pattern being electrically insulated from the first semiconductor element, and the second semiconductor chip further includes a second semiconductor element at the second surface of the second semiconductor substrate, the second test pattern being electrically insulated from the second semiconductor element. However, Chang teaches the first test pattern Fig. 4: 428 being electrically insulated from the first semiconductor element Fig. 420a, and the second semiconductor chip further Fig. 4: 204 includes a second semiconductor element Fig. 4: 420b at the second surface of the second semiconductor substrate Fig. 4: 204, the second test pattern Fig. 4: 428 being electrically insulated from the second semiconductor element Fig. 4: 420b (para. 0043-44 teaches that conductive paths between test circuit 428 and the circuits416b, and the transistors 420a/b are blocked). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lin and Chang for the purpose of enabling independent testing of the circuits and transistors of the die to be performed by a test signal (para. 44).
Claims 14-20, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 9653430) and further in view of Lu et al. (US 20220336299).
Regarding claim 14, Kim teaches a semiconductor package, comprising:
a substrate Fig. 1G: 85;
a first semiconductor chip Fig. 1G: 100 on the substrate Fig. 1G: 85; and
a second semiconductor chip Fig. 1G: 200 on the first semiconductor chip Fig. 1G: 100,
wherein the first semiconductor chip Fig. 1G: 100 includes:
a first semiconductor substrate Fig. 1G: 111;
a first circuit layer Fig. 1G: 118 on a bottom surface of the first semiconductor substrate Fig. 1G: 111;
first test pads Fig. 1G: 117 on a top surface of the first semiconductor substrate Fig. 1G: 111 and adjacent to a corner of the first semiconductor substrate Fig. 1G: 111; and
first through vias Fig. 1G: 115 that vertically penetrate the first semiconductor substrate Fig. 1G: 111, the first through vias Fig. 1G: 115 being electrically connected to the first circuit layer Fig. 1G: 118 (col. 12, lines 65-67),
wherein the second semiconductor chip Fig. 1G: 200 includes:
a second semiconductor substrate Fig. 1G: 211; and
a second circuit layer Fig. 1G: 217 on a bottom surface of the second semiconductor substrate Fig. 1G: 211, the second circuit layer Fig. 1G: 217 including second test pads Fig. 1G: 217 adjacent to a corner of the second semiconductor substrate Fig. 1G: 211.
Kim fails to explicitly teach wherein each of the second test pads is bonded to and simultaneously overlaps, from a plan view, two neighboring ones of the first test pads, the first and second test pads constituting a series circuit. However, Lu teaches wherein each of the second test pads Fig. 2: 206 is bonded to and simultaneously overlaps, from a plan view, two neighboring ones of the first test pads Fig. 2: 214, the first and second test pads constituting a series circuit (i.e. starting from leftmost Fig. 2: 206, through 214, through 206, through 214, and through 206). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lin and Lu for the purpose of creating a daisy chain seal ring structure to reduce/prevent wafer cracking (para. 0016, 0036-0037) and can improve contamination prevention (para. 0043).
Regarding claim 15, Kim teaches the semiconductor package of claim 14, wherein the first semiconductor chip Fig. 1G: 100 further includes a protection layer Fig. 1G: 113 on the top surface of the first semiconductor substrate Fig. 1G: 111, the protection layer Fig. 1G: 113 surrounding the first test pads Fig. 1G: 117, wherein the protection layer Fig. 1G: 113 is bonded to the second circuit layer Fig. 1G: 217 (shown in Fig. 1G).
Regarding claim 16, Kim teaches the semiconductor package of claim 15, wherein a top surface of the protection layer Fig. 1G: 113 is coplanar with top surfaces of the first test pads Fig. 1G: 117 (shown in Fig. 1G).
Regarding claim 17, Kim teaches the semiconductor package of claim 14, wherein one of the first through vias Fig. 1G: 115 is connected to one of the first test pads Fig. 1G: 117, the one of the first test pads Fig. 1G: 117 being on an end of the series circuit (test pad on the leftmost or rightmost portion).
Regarding claim 18, Kim teaches the semiconductor package of claim 17, wherein the first semiconductor chip Fig. 1G: 100 further includes first signal pads Fig. 1G: 117 on the top surface of the first semiconductor substrate Fig. 1G: 111 and on a central portion of the first semiconductor substrate Fig. 1G: 111 (i.e. test pads towards the center top surface of the first substrate), wherein remaining ones of the first through vias Fig. 1G: 115 connect the first signal pads Fig. 1G: 117 to respective first semiconductor elements Fig. 1G: 118 formed on the bottom surface of the first semiconductor substrate Fig. 1G: 111.
Regarding claim 19, Kim teaches the semiconductor package of claim 18, wherein the second circuit layer Fig. 1G: 217 of the second semiconductor chip Fig. 1G: 200 further includes second signal pads Fig. 1G: 217 on a central portion of the second semiconductor substrate Fig. 1G: 211 (i.e. test pads towards the center surface of the second substrate), the second signal pads Fig. 1G: 217 being connected to respective second semiconductor elements Fig. 1G: 218/219 on the bottom surface of the second semiconductor substrate, wherein each second signal pad Fig. 1G: 217 and respective first signal pad Fig. 1G: 117 are bonded to constitute a single unitary piece (shown in Fig. 1G).
Regarding claim 20, Kim teaches the semiconductor package of claim 19, wherein: the first test pads Fig. 1G: 117 are electrically insulated from the first semiconductor elements Fig. 1G: 118, and the second test pads Fig. 1G: 217 are electrically insulated from the second semiconductor elements Fig. 1G: 218. Kim teaches backside pads 118/218 that are formed over an insulating layer 116/216 that may electrically insulate the backside pads from the semiconductor substrate (col. 13, lines 1-11; col. 12, lines 31-46).
Regarding claim 26, Kim teaches the semiconductor package of claim 14, wherein: the first semiconductor chip Fig. 1G: 100 and the second semiconductor chip Fig. 1G: 200 are bonded to each other, and the first test pads Fig. 1G: 117 and the second test pads Fig. 1G: 217 constitute a single unitary piece formed of the same material (col. 11, lines 28-30, lines 54-56).
Conclusion
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 6, 2026
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