Attorney Docket Number: P202300686US01
Filing Date: 6/23/2023
Inventors: Xie et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendment filed 12/18/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed on 12/18/2025, responding to the Office action mailed 9/18/2025, has
been entered. Applicant amended claim 1, and cancelled claims 13 and 18-19. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have overcome the respective claim rejections under 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 9/18/2025. Accordingly, the claim rejections of 35 U.S.C. 102 and 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 1-12, 14-17, and 20. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Dennard (US 20120299080 A1) in view of Su (US 20210104616 A1) further in view of Dyer (US 20080283930 A1), Liu (US 9646962 B1), and Schmenn (US 20170047423 A1).
Regarding claim 1, Dennard (see, e.g., fig. 1) shows most aspects of the instant invention including a semiconductor structure comprising:
A logic device region (e.g., CMOS arrangement on p-type substrate 1) comprising:
a plurality of first conductivity type field effect transistors (FETS) (e.g., nfets 10A) and a plurality of second conductivity type FETs (e.g., pfets 10B), wherein the first conductivity type FETs (e.g., nfets 10A) are spaced apart (see, e.g., space between nfets and pfets) from the second conductivity type FETs (e.g., pfets 10B) and the first conductivity type FETs (e.g., nfets 10A) are of a different conductivity than the second conductivity type FETs (e.g., pfets 10B);
A first trench isolation structure (e.g., shallow intra-well STI 6) located in a space between each neighboring pair (e.g., note that STI 6 is between pfets, as shown in fig. 1) of first conductivity type FETs (e.g., nfets 10A) and between each pair of second conductivity type FETs (e.g., pfets 10B);
A second trench isolation structure (e.g., deep inter-well STI 7) located in a space between each neighboring pair of first conductivity type FETs (e.g., nfets 10A) and second conductivity type FETs (e.g., pfets 10B);
Dennard (see, e.g., fig. 4), however, fails to show the first trench isolation structure comprises a first trench dielectric material as a sole trench dielectric material, while it also fails to show the second trench isolation structure comprises at least a second trench dielectric material that is compositionally different from the first trench dielectric material, while it also fails to teach passive device region comprising at least one electrostatic discharge protection diode located adjacent to the logic device region, and a passive device region-logic device region second trench isolation structure located in a space between the logic device region and the passive device region, wherein the passive device region-logic device region second trench isolation structure comprises at least the second trench dielectric material; and a frontside contact structure contacting a first surface of the at least one electrostatic discharge protection diode, and a backside contact structure contacting a second surface of the at least one electrostatic discharge protection diode, wherein the second surface is opposite the first surface.
Su (see, e.g., fig. 1A), in a similar device to Dennard, teaches a trench isolation structure (e.g., STI regions 104) comprises a second trench dielectric material (see, e.g., paragraph 26 “STI regions 104 can be made of a dielectric material. In some embodiments, STI regions 104 can include … silicon nitride (SiN.sub.x)…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the material of Su within the STI region of Dennard, as the material was well-known in the art at the time of filing to include as a material serving as an STI region, as taught by Su.
Dennard in view of Su (see, e.g., fig. 1A), however, fails to teach the first trench isolation structure comprises a first trench isolation structure, and that it’s a sole trench material, and a passive device region-logic device region second trench isolation structure located in a space between the logic device region and the passive device region, wherein the passive device region-logic device region second trench isolation structure comprises at least the second trench dielectric material; and a frontside contact structure contacting a first surface of the at least one electrostatic discharge protection diode, and a backside contact structure contacting a second surface of the at least one electrostatic discharge protection diode, wherein the second surface is opposite the first surface.
Dyer (see, e.g., fig. 10), in a similar device to Dennard in view of Su, teaches the first trench isolation structure (e.g., intrawell isolation trench structure 81) as a sole trench dielectric material (see, e.g., paragraph 61 “a dielectric material is deposited…within the at least one intra-well isolation trench to form at least one intra-well isolation trench structure 81… The dielectric material preferably comprises an oxide such as silicon dioxide”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the material of Dyer within the intra-well region of Dennard in view of Su, as the material was well-known in the art at the time of filing to include as a material serving as an intra-well region, as taught by Dyer.
Dennard in view of Su further in view of Dyer, however, fails to teach a passive device region-logic device region second trench isolation structure located in a space between the logic device region and the passive device region, wherein the passive device region-logic device region second trench isolation structure comprises at least the second trench dielectric material; and a frontside contact structure contacting a first surface of the at least one electrostatic discharge protection diode, and a backside contact structure contacting a second surface of the at least one electrostatic discharge protection diode, wherein the second surface is opposite the first surface.
Liu (see, e.g., fig. 4A), in a similar device to Dennard in view of Su further in view of Dyer, comprises a passive device region (e.g., ESD device 102) located adjacent to a logic device region (e.g., finFET 104), and a passive device region-logic device region second trench isolation structure (e.g., trench 420) located in a space between the logic device region (e.g., finFET 104) and the passive device region (e.g., ESD device 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the passive device region of Liu adjacent to the logic device region of Dennard in view of Su further in view of Dyer, in order to protect the logic device region from any potential ESD current (see, e.g., paragraph 43 of Liu).
While Liu does not explicitly teach the passive device region-logic device region second trench isolation structure comprises the same dielectric material as the second trench dielectric material (such as SiN, per Su), it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material of Su composition (say, silicon nitride) within the dielectric trench of Dennard in view of Su further in view of Dyer and Liu, because many are recognized in the semiconductor art for their usage in dielectric materials, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Dennard in view of Su further in view of Dyer and Liu, however, fails to teach a frontside contact structure contacting a first surface of the at least one electrostatic discharge protection diode, and a backside contact structure contacting a second surface of the at least one electrostatic discharge protection diode, wherein the second surface is opposite the first surface.
Schmenn (see, e.g., fig. 3A), in a similar device to Dennard in view of Su further in view of Dyer and Liu, teaches a frontside contact structure (e.g., first contact 303) contacting a first surface (e.g., top surface of fig. 3A) of an electrostatic discharge protection element (e.g., ESD protection element 200), and a backside contact structure (e.g., second contact 302) contacting a second surface (e.g., bottom surface of fig. 3A) of the at least one electrostatic discharge protection element (e.g., ESD protection element 200), wherein the second surface (e.g., bottom surface of fig. 3A) is opposite the first surface (e.g., top surface of fig. 3A).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the frontside contact and backside contact structure of Schmenn within the device of Dennard in view of Su further in view of Dyer and Liu, in order to achieve the expected result connecting the diode to the rest of the semiconductor structure.
Regarding claim 2, Su (see, e.g., fig. 1A) teaches the second trench isolation structure (e.g., STI regions 104) is entirely composed of the second trench dielectric material (e.g., note that the STI region 104 is a single layer + paragraph 26 “STI regions 104 can be made of a dielectric material).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to limit the second trench isolation structure of Dennard in view of Su further in view of Dyer, Liu, and Schmenn to a single dielectric material (also note that the trench isolation of structure of Dennard is also a single layer), in order to limit the cost of manufacturing during the process of fabrication of the device.
Regarding claim 14, Su (see, e.g., fig. 1A) teaches the second trench isolation structure (e.g., STI regions 104) is entirely composed of the second trench dielectric material (e.g., note that the STI region 104 is a single layer).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to limit the passive device region-logic device region second trench isolation structure of Dennard in view of Su further in view of Dyer, Liu, and Schmenn to the same material restraint as the second trench isolation structure, in order to limit the cost of manufacturing during the process of fabrication of the device.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Mun (US 20240243058 A1).
Regarding claim 3, Dennard in view of Su further in view of Dyer, Liu, and Schmenn fails to teach a third trench dielectric material located entirely above the second trench dielectric material, wherein the third trench dielectric material is compositionally different from the second trench dielectric material.
Mun (see, e.g., fig. 1), in a similar device to Dennard in view of Su further in view of Dyer, Liu, and Schmenn, teaches a trench dielectric material located above another trench dielectric material, wherein the two materials are compositionally different (see, e.g., paragraph 32 “the dielectric-filled trench 180… may be filled with…multiple layers of dielectric material where at least two of the layers are different dielectric materials”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the distinct dielectric material layers of Mun in the trench of Dennard in view of Su further in view of Dyer, Liu, and Schmenn, as it was well-known at the time of filing that numerous dielectric material layers of different compositions could be used to satisfy the purpose of isolation within the configuration.
Regarding claim 4, Mun (see, e.g., fig. 1) does not explicitly teach that the third trench dielectric material and the first trench dielectric material (e.g., the trench material of Dyer) are composed of a compositionally same trench dielectric material.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the trench dielectric material of Dyer (e.g., the silicon dioxide) within the third trench dielectric material of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Mun, as silicon dioxide was a well-known material to be included within a trench isolation material at the time of filing the invention, as taught by Dyer.
Regarding claim 5, Mun (see, e.g., fig. 1) does not explicitly teach the third trench dielectric material and the first trench dielectric material (e.g., the trench material of Dyer) are compositionally different.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include one of the known dielectrics of Mun within a trench as a dielectric material layer within the aforementioned trench (see, e.g., paragraph 35 “The dielectric can include any ILD material listed herein” + paragraph 20 “ILD layers 132 may include but are not limited to… silicon oxycarbide”), because many are recognized in the semiconductor art for their usage in dielectric materials, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). Therefore, it was well-known in the art at the time of filing the invention that silicon oxycarbide (a compositionally different material than the silicon dioxide of Dyer) could serve as a dielectric to use as a layer within the third trench dielectric material of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Mun.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Ichinose (US 20040009636 A1).
Regarding claim 6, Dennard (see, e.g., fig. 1) shows the first trench isolation structure (e.g., shallow intra-well STI 6) has a first width (see, e.g., paragraph 27 “The width of the deep inter-well STI 7 may be in the range of about 25 nm to about 200 nm, with 50 nm being a nominal value”).
Dennard in view of Su further in view of Dyer, Liu, and Schmenn, however, fails to teach the second trench isolation structure has a second width wherein the first width is greater than the second width.
Ichinose (see, e.g., fig. 8), in a similar device to Dennard in view of Su further in view of Dyer, Liu, and Schmenn, teaches the width (see, e.g., paragraph 95 “The width H1 of the intra-well isolation is about .2 µm”) of a trench isolation structure (e.g., intra-well isolation (ISOp-p)).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the width of the trench of Ichinose within the trench configuration of Dennard in view of Su further in view of Dyer, Liu, and Schmenn in order to provide a configuration with wider trenches between same-conductivity-type FETs, lowering the resistance due to a wider conduction path, and thinner trenches between different-conductivity-type FETs, improving the switching performance within the neighboring FETs sharing opposing conductivities (also note that .2 µm is 200 nm, the top range of the first trench isolation structure’s width).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli (US 20180175034 A1).
Regarding claim 7, Dennard (see, e.g., figs. 1 and 2) shows source/drain regions (e.g., source 14/drain 16 of fig. 2, note that fig. 2 is a cross section of FETs 10) of at least one neighboring pair of first conductivity type FETs (e.g., nfets 10A) or source/drain regions (e.g., source 14/drain 16 of fig. 2, note that fig. 2 is a cross section of FETs 10) of at least one neighboring pair (see, e.g., neighboring pair of pfets 10B in fig. 1) of second conductivity type FETs (e.g., pfets 10B).
Dennard in view of Su further in view of Dyer, Liu, and Schmenn, however, fails to teach a merged backside source/drain contact structure contacting the source/drain regions of at least one neighboring pair of first conductivity type FETs or source/drain regions of at least one neighboring pair of second conductivity type FETs.
Goktepeli (see, e.g., fig. 6A), in a similar device to Dennard in view of Su further in view of Dyer, Liu, and Schmenn teaches a backside source/drain contact structure (e.g., shared contact 640) contacting source/drain regions (e.g., drain of front-side transistor 610 and drain of backside transistor 630).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the backside source/drain contact structure of Goktepeli in the device of Dennard in view if Su further in view of Dyer, Liu, and Schmenn in order to achieve the expected result of moving the contacts of the device to the backside, preserving space on the frontside for additional signal routing, improving power delivery of the device.
Regarding claim 9, Dennard (see, e.g., fig. 1) in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli teaches the first trench isolation structure (e.g., shallow intra-well STI 6) located in the space between the at least one neighboring pair of first conductivity type FETs (e.g., nfets 10A) or the at least one neighboring pair of second conductivity type FETs (e.g., pfets 10B) including the merged backside source/drain contact structure (e.g., shared contact 640 of Goktepeli) has a depth that is less than a depth of the second trench isolation structure (e.g., deep inter-well STI 7 - see, e.g., difference in depth between shallow intra-well STI 6 and deep inter-well STI 7).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli, and Peng (US 20220344263 A1).
Regarding claim 8, Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli fails to teach an additional backside back-end-of-the-line (BEOL) structure electrically contacted to the merged backside source/drain contact structure via a VDD power rail located in an initial backside BEOL structure.
Peng (see, e.g., figs. 1F and 8), in a similar device to Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli teaches an additional back-end-of-the-line (BEOL) structure (e.g., backside interconnect 840 of fig. 8, including VDD line 802 and VSS line 804) comprising a VDD power rail (e.g., VDD line 802 of fig. 8), while it also teaches a backside source/drain contact structure (e.g., backside contacts 2BB and 3BB of fig. 1F) connected to a power rail (e.g., power rail 131 of fig. 1F).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to combine the two aforementioned embodiments of Peng, resulting in providing a VDD and VSS line into the power rail (in order to supply the positive and negative power supplies to the terminals as needed), then connecting the power rail to the backside interconnect, to create an immediate stacked-BEOL structure and allow additional connection from the source/drain contact structures to an interconnect structure, providing connection to the rest of the device.
Furthermore, it also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include these combined embodiments in the device of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli, in order to provide the positive and negative voltage supply to the FET structures as needed and give additional connection to the device as necessary.
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli, and Thomas (US 20230037957 A1).
Regarding claim 10, Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli fails to explicitly teach a frontside contact structure contacting a source/drain region of the first conductivity type FETs not including the merged backside source/drain contact structure or a source/drain region of the second conductivity type FETs not including the merged backside source/drain contact structure.
Thomas (see, e.g., fig. 1A), in a similar device to Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli, teaches a frontside contact structure (e.g., contact 131 + paragraph 25) contacting a source/drain region (e.g., source region 113).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the frontside contact structure of Thomas onto the source/drain of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli, in order to achieve the expected result of providing electrical connections onto the source/drain regions of the FETS.
In addition, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention to duplicate the merged backside source/drain contact structure of Goktepeli to form a frontside contact structure onto the frontside of Dennard, to achieve the expected result of providing contact to the remaining FETs throughout the rest of the arrangement in order for every FET within the device to be electrically connected, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Regarding claim 12, Dennard (see, e.g., fig. 1) in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli teaches a backside placeholder structure (e.g., underlying substrate 1) under the source/drain regions (e.g., source 14/drain 16 of fig. 2, note that fig. 2 is a cross section of FETs 10) that contacts the frontside contact structure (e.g., duplicated merged backside source/drain contact structure of Goktepeli, see paragraphs 30 and 31 above).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli, Thomas, and Goktepeli (US 9780210 A1, hereinafter Goktepeli2).
Regarding claim 11, Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli, and Thomas fails to teach a frontside BEOL structure contacting the frontside contact structure.
Goktepeli2 (see, e.g., claim 20), in a similar device to Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli, and Thomas, teaches a frontside BEOL structure contacting a frontside contact structure (see, e.g., claim 20 “a back-end-of-line (BEOL) interconnect coupled to a front-side contact on the second source/drain region of the transistor, the BEOL interconnect within a front-side dielectric layer”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the frontside BEOL structure of Goktepeli2 within the device of Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli, and Thomas, in order to achieve the expected result of providing an interconnect structure onto the source/drain contact setup and allowing electrical connection through other portions of the device as desired.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Mun.
Regarding claim 15, Dennard in view of Su further in view of Dyer, Liu, and Schmenn fails to teach third trench dielectric material located entirely above the second trench dielectric material, wherein the third trench dielectric material is compositionally different from the second trench dielectric material.
Mun (see, e.g., fig. 1), in a similar device to Dennard in view of Su further in view of Dyer and Liu teaches a trench dielectric material located above another trench dielectric material, wherein the two materials are compositionally different (see, e.g., paragraph 32 “the dielectric-filled trench 180… may be filled with…multiple layers of dielectric material where at least two of the layers are different dielectric materials”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the distinct dielectric material layers of Mun in the trench of Dennard in view of Su further in view of Dyer, Liu, and Schmenn, as it was well-known at the time of filing that numerous dielectric material layers of different compositions could be used to satisfy the purpose of isolation within the configuration.
Regarding claim 16, Mun (see, e.g., fig. 1) does not explicitly teach that the third trench dielectric material and the first trench dielectric material (e.g., the trench material of Dyer) are composed of a compositionally same trench dielectric material.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the trench dielectric material of Dyer (e.g., the silicon dioxide) within the third trench dielectric material of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Mun, as silicon dioxide was a well-known material to be included within a trench isolation material at the time of filing the invention, as taught by Dyer.
Regarding claim 17, Mun (see, e.g., fig. 1) does not explicitly teach the third trench dielectric material and the first trench dielectric material (e.g., the trench material of Dyer) are compositionally different.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include one of the known dielectrics of Mun within a trench as a dielectric material layer within the aforementioned trench (see, e.g., paragraph 35 “The dielectric can include any ILD material listed herein” + paragraph 20 “ILD layers 132 may include but are not limited to… silicon oxycarbide”). Therefore, it was well-known in the art at the time of filing the invention that silicon oxycarbide (a compositionally different material than the silicon dioxide of Dyer) could serve as a dielectric to use as a layer within the third trench dielectric material of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Mun.
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Dennard in view of Su further in view of Dyer, Liu, Schmenn, Goktepeli2, and Peng.
Regarding claim 20, Dennard in view of Su further in view of Dyer, Liu, and Schmenn fails to teach wherein the frontside contact structure electrically connects the at least one electrostatic discharge protection diode to a frontside BEOL structure, and the backside contact structure electrically connects the at least one electrostatic discharge protection diode to an additional backside BEOL structure via a VSS power rail that is present in an initial backside BEOL structure.
Goktepeli2 (see, e.g., claim 20), in a similar device to Dennard in view of Su further in view of Dyer, Liu, and Schmenn, teaches a frontside BEOL structure contacting a frontside contact structure (see, e.g., claim 20 “a back-end-of-line (BEOL) interconnect coupled to a front-side contact on the second source/drain region of the transistor, the BEOL interconnect within a front-side dielectric layer”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the frontside BEOL structure of Goktepeli2 within the device of Dennard in view of Su further in view of Dyer, Liu, and Schmenn, in order to achieve the expected result of providing an interconnect structure onto the frontside contact structure of the electrostatic discharge protection, connecting the ESD region to the rest of the device for protection potential as desired.
Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli2, however, fails to teach the backside contact structure electrically connects the at least one electrostatic discharge protection diode to an additional backside BEOL structure via a VSS power rail that is present in an initial backside structure.
Peng (see, e.g., figs 1F and 8), in a similar device to Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli2, however, teaches a BEOL structure (e.g., interconnect 840 of fig. 8) includes a VSS power rail (e.g., VSS line 804).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the BEOL structure and VSS power rail of Peng within the device of Dennard in view of Su further in view of Dyer, Liu, Schmenn, and Goktepeli2, in order to connect the electrostatic protection diode to the VSS power rail for electrostatic discharge protection. Note that regarding connecting the backside contact structure to the additional backside BEOL structure, the comments regarding connecting a contact structure and a BEOL structure with respect to paragraphs 64-66 are considered to be relevant here.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814