DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 4 May 2026 of Applicants’ amendments of the specification and the claims in which claims 1 and 4 are amended. In view of the amendments, the Office withdraws the drawing objections, specification objection, claim objection, and indefiniteness rejections identified in the Office Communication dated 5 January 2026.
Response to Arguments
Applicants’ arguments with respect to independent claim(s) 1 and 4 have been considered but are not persuasive.
Applicants argue in the third paragraph of page 8 and with respect to claim 1 that Yasuhara does not teach the subject matter newly added to the claim whereby “an emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches.” Claim 1 is rejected for obviousness over the teachings of Yasuhara. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Yasuhara teaches in Fig. 10 (an alternative embodiment to that applied for the remaining limitations of the claim) an emitter region (34) continuously extends across a first mesa section (section between adjacent trenches 22 including layers 32, 24, 26) to simultaneously contact adjacent gate trenches (22). The motivation for combining the teaching of this embodiment with Yasuhara’s main embodiment is identified below with respect to the rejection of claim 1.
Applicants argue in the third paragraph of page 8 and with respect to claim 1 that Yasuhara and Iwakaji do not teach the subject matter, newly added to the claim, of: (1) “two adjacent gate trenches … with a first mesa section interposed therebetween” and (2) “the emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches.” Claim 4 is rejected over the combined teachings of Yasuhara and Iwakaji. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Yasuhara teaches in Fig. 8 and paragraphs [0035, 0036] two adjacent gate trenches (21), which are two adjacent trenches discretely formed from the front surface side of the semiconductor substrate (10) with a first mesa section (mesa section separating adjacent 21s) interposed therebetween. Additionally, Yasuhara teaches in another embodiment illustrated by Fig. 10 that an emitter region (34) continuously extends across a first mesa section (mesa section separating adjacent 22) to simultaneously contact adjacent gate trenches (22). The motivation for combining the teaching of the embodiment illustrated by Fig. 10 with that illustrated by Fig. 8 is identified below with respect to the rejection of claim 4.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1, lines 6 and 7, recites “an emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches,” which is not illustrated by the drawings. Specifically, e.g., Fig. 1 illustrates that a contact (132) extends downwardly from an emitter pad (104) into a P-body layer 118, which is disposed between adjacent gate electrodes (120G), and the contact (132) has an emitter region (122) disposed on opposite vertical sides. And no other drawing illustrates a continuous emitter region (e.g., 122) disposed between adjacent gate electrodes (120G).
Claim 4, lines 21-23, recites “the emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches,” which is not illustrated by the drawings. Specifically, e.g., Fig. 1 illustrates that a contact (132) extends downwardly from an emitter pad (104) into a P-body layer 118, which is disposed between adjacent gate electrodes (120G), and the contact (132) has an emitter region (122) disposed on opposite vertical sides. And no other drawing illustrates a continuous emitter region (e.g., 122) disposed between adjacent gate electrodes (120G).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, lines 6 and 7, recites “an emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches,” which is new matter because it lacks adequate support in the original application. Specifically, e.g., Fig. 1 illustrates that a contact (132) extends downwardly from an emitter pad (104) into a P-body layer 118, which is disposed between adjacent gate electrodes (120G), and the contact (132) has an emitter region (122) disposed on opposite vertical sides. And no other drawing illustrates a continuous emitter region (e.g., 122) disposed between adjacent gate electrodes (120G). And the original specification does not disclose an emitter region continuously extends across a mesa section to simultaneously contact adjacent gate trenches. Claims 2 and 3 are rejected due to their dependence from base claim 1.
Claim 4, lines 21-23, recites “the emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches,” which is new matter because it lacks adequate support in the original application. Specifically, e.g., Fig. 1 illustrates that a contact (132) extends downwardly from an emitter pad (104) into a P-body layer 118, which is disposed between adjacent gate electrodes (120G), and the contact (132) has an emitter region (122) disposed on opposite vertical sides. And no other drawing illustrates a continuous emitter region (e.g., 122) disposed between adjacent gate electrodes (120G). And the original specification does not disclose an emitter region continuously extends across a mesa section to simultaneously contact adjacent gate trenches. Claims 5 and 6 are rejected due to their dependence from base claim 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yasuhara et al. (US20220302288A1).
Regarding claim 1, Yasuhara teaches in Fig. 8 a trench gate type IGBT, comprising:
a semiconductor substrate (10) {[0036]};
two adjacent gate trenches (21), which extend from the front surface toward the back surface side of the semiconductor substrate (10), and with a first mesa section (section between adjacent trenches 21 including layers 32, 24, 26) interposed therebetween {[0036]};
a switch trench (22), which extends from the front surface toward the back surface side of the semiconductor substrate (30) and has no emitter region (34) formed therearound {[0036]}; and
a setting terminal (Vg2 terminal) for externally controlling the voltage of the switch trench (22) {[0080]}; wherein
a switching between a first state, in which a voltage drop at on-time is relatively small and an energy loss at turn-off time is relatively large, and a second state, in which the voltage drop at on-time is relatively large and the energy loss at turn-off time is relatively small, can be performed, according to a voltage applied to the setting terminal (Vg2 terminal) {Fig. 9; [0148-0153]; see Examiner’s Note, below}.
Yasuhara does not teach in the embodiment illustrated by Fig. 8 that an emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches.
In an embodiment illustrated by Fig. 10, Yasuhara teaches an emitter region (34) continuously extends across a first mesa section (section between adjacent trenches 22 including layers 32, 24, 26) to simultaneously contact adjacent gate trenches (22). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yasuhara’s trench gate type IGBT based on the further teachings of Yasuhara, to achieve the above-identified subject matter, so on-resistance of the IGBT … is reduced. Yasuhara [0159]. Moreover, all the claimed elements (e.g., emitter region, mesa section, adjacent gate trenches) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yasuhara) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: Yasuhara’s IGBT has the same structure as that claimed by Applicants. Page 5, lines 3-7, of the instant application admits that a collector-emitter voltage drop Vce is inversely proportional to an amount of holes in the IGBT structure. And page 9, lines 1-7, of the instant application admits that energy loss (i.e., switching loss; see page 9, lines 1-7) is directly proportional to the amount of holes. Similar to the instant application, Yasuhara teaches in paragraphs [0148-0153] that holes are discharged when a negative voltage is applied to the Vg2 terminal prior to an off-time to reduce the off-time switching loss (i.e., energy loss) and are not discharged when a zero voltage is applied to the Vg2 terminal prior to an on-time.
Regarding claim 2, Yasuhara teaches the trench gate type IGBT according to claim 1, and Yasuhara further teaches the first state is adopted when an on-off frequency is low and the second state is adopted when the on-off frequency is high.
Examiner’s Note: As discussed more fully with respect to base claim 1, Yasuhara teaches the first state is employed at on-time and the second state is employed at off-time. Thus, each state is employed regardless of the frequency with which the on-off cycle occurs. Moreover, the recitations of “when an on-off frequency is low” and “when the on-off frequency is high” are directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 3, Yasuhara teaches the trench gate type IGBT according to claim 2, and Yasuhara further teaches wherein the voltage applied to the setting terminal can be changed continuously.
Examiner’s Note: As discussed more fully with respect to base claim 1, Yasuhara teaches the voltage applied to the setting terminal can be changed depending on whether an on-state or an off-state transition is desired. The American Heritage Dictionary, 4th edition, defines “can” as “[p]ossession of a capability.” Regardless of whether the recited limitation of “continuously” is intended to mean linearly or uninterrupted in time, Yasuhara’s IGBT possesses the capability to be changed both linearly (due to parasitic capacitances/resistances) and uninterrupted in time.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yasuhara in view of Iwakaji et al. (US20200303525A1).
Regarding claim 4, Yasuhara teaches in Fig. 8 a trench gate type IGBT, comprising:
a semiconductor substrate (10) {[0036]};
an emitter electrode (12), which is formed on the front surface of the semiconductor substrate (10) {[0035]};
a collector pad (14), which is formed on the back surface of the semiconductor substrate (10) {[0035]};
a P-type P-collector layer (28), which is formed on the back surface side of the semiconductor substrate (10) on the collector pad (14) {[0036]};
an N-type N-drift layer (30), which is positioned on the P-collector layer (28) in the semiconductor substrate (10) {[0036]};
a P-type P-body layer (32), which is formed on the semiconductor substrate (10) {[0036]};
two adjacent gate trenches (21), which are two adjacent trenches discretely formed from the front surface side of the semiconductor substrate (10) with a first mesa section (mesa section separating adjacent 21s) interposed therebetween and extending toward the back surface side to the N-drift layer (30), and have a gate region (51) formed inside with an insulating film therebetween {[0035, 0036]};
a switch trench (22), which is a trench discretely formed from the front surface side of the semiconductor substrate (10) with a second mesa section (mesa section adjacent to 22) adjacent thereto and extending toward the back surface side to the N-drift layer (30), and is connected to a setting terminal (52) formed inside with an insulating film (42) therebetween and allowing a voltage to be set externally {[0035, 0036, 0080]};
an emitter region (34) formed on the front surface side of the P-body layer (32), and connected to the emitter electrode (12) {[0041, 0050]};
a first mesa region (32 region of mesa section separating adjacent 21s), which is the P-body layer (32) of the first mesa section (mesa section separating adjacent 21s) and connected to the emitter electrode (12) through a first contact (34 & 36 between 21s), and functions as a channel due to the presence of the emitter region (34) on the front surface side {[0049]}; and
a second mesa region (32 region of mesa section adjacent to 22), which is the P-body layer (32) of the second mesa section (mesa section adjacent to 22) and connected to the emitter electrode (12) through a second contact (36 adjacent 22), and does not function as a channel due to an absence of the emitter region (34) on the front surface side {[0004], see Examiner’s Note, below}; wherein
the second mesa region (32 region of mesa section adjacent to 22) is positioned around the switch trench (22).
Yasuhara does not teach an N-type carrier store layer, which is formed on the N-drift layer and has an impurity concentration higher than that of the N-drift layer; and the P-type P-body layer is formed on the front surface side of the carrier store layer.
In an analogous art, Iwakaji teaches in Fig. 2 and paragraph [0041] an N-type carrier store layer (33) that is disposed between an N-drift layer (32) and a P-type P-body layer (34) and has an impurity concentration higher than that of the N-drift layer (32). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yasuhara’s trench gate type IGBT based on the teachings of Iwakaji – to include an N-type carrier store layer, which is formed on the N-drift layer and has an impurity concentration higher than that of the N-drift layer, whereby the P-type P-body layer is formed on the front surface side of the carrier store layer – for reducing an on-resistance of the IGBT. Iwakaji [0042]. Moreover, all the claimed elements (e.g., N-type carrier store layer, N-drift layer, P-type P-body layer, impurity concentration) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Iwakaji) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Yasuhara does not teach in the embodiment illustrated by Fig. 8 that the emitter region continuously extends across the first mesa section to simultaneously contact the adjacent gate trenches.
In an embodiment illustrated by Fig. 10, Yasuhara teaches an emitter region (34) continuously extends across a first mesa section (section between adjacent trenches 22 including layers 32, 24, 26) to simultaneously contact adjacent gate trenches (22). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yasuhara’s trench gate type IGBT as modified by Iwakaji based on the further teachings of Yasuhara, to achieve the above-identified subject matter, so on-resistance of the IGBT … is reduced. Yasuhara [0159]. Moreover, all the claimed elements (e.g., emitter region, mesa section, adjacent gate trenches) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yasuhara) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: Yasuhara teaches in paragraph [0004] [i]n the IGBT, a channel is formed in the p-type base region by applying a positive voltage equal to or higher than a threshold voltage to the gate electrode. Then, electrons are injected from the n-type emitter region into the n-type drift region, and holes are injected from the collector region into the n-type drift region at the same time. As a result, a current using electrons and holes as carriers flows between the collector electrode and the emitter electrode. Thus, in the absence of the n-type emitter region adjacent the switching trench, no electrons are injected from the n-type emitter region into the [non-existent] n-type drift region and no current flows; therefore, no current channel is produced.
Regarding claim 5, Yasuhara as modified by Iwakaji teaches the trench gate type IGBT according to claim 4, and Yasuhara further teaches wherein the first state is adopted when an on-off frequency is low and the second state is adopted when the on-off frequency is high.
Examiner’s Note: As discussed more fully with respect to base claim 4, Yasuhara teaches the first state is employed at on-time and the second state is employed at off-time. Thus, each state is employed regardless of the frequency with which the on-off cycle occurs. Moreover, the recitations of “when an on-off frequency is low” and “when the on-off frequency is high” are directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 6, Yasuhara as modified by Iwakaji teaches the trench gate type IGBT according to claim 5, and Yasuhara further teaches wherein the voltage applied to the setting terminal can be changed continuously.
Examiner’s Note: As discussed more fully with respect to base claim 4, Yasuhara teaches the voltage applied to the setting terminal can be changed depending on whether an on-state or an off-state transition is desired. The American Heritage Dictionary, 4th edition, defines “can” as “[p]ossession of a capability.” Regardless of whether the recited limitation of “continuously” is intended to mean linearly or uninterrupted in time, Yasuhara’s IGBT possesses the capability to be changed both linearly (due to parasitic capacitances/resistances) and uninterrupted in time.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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