Prosecution Insights
Last updated: April 19, 2026
Application No. 18/213,661

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Jun 23, 2023
Examiner
NARAGHI, ALI
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toyoda Gosei Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
666 granted / 771 resolved
+18.4% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
24 currently pending
Career history
795
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
61.6%
+21.6% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
13.1%
-26.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 771 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-4 in the reply filed on 10/29/2025 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is absolutely unclear what applicant is referring by the limitation “a width of the second layer the ion implantation region”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2,4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuroski et al (US Pub No. 20180026131), in view of Nakano et al (US Pub No. 20150295079). With respect to claim 1, Kuroski et al discloses a semiconductor device (Fig.8) formed of a group III nitride semiconductor (Para 13), of trench gate type (15), comprising: a substrate (10); a first layer (11) formed of an n-type group III nitride semiconductor (Para 44) and provided on the substrate (Fig.8); a second layer (12) formed of a p-type group III nitride semiconductor (Para 45) and provided on the first layer (Fig.8); a third layer formed of an n-type group III nitride semiconductor (13, para 46) and provided on the second layer; and a trench provided in a partial region of a surface of the third layer (Fig.8) and having a depth penetrating through the third layer (Fig.8) and the second layer (Fig.8)and reaching the first layer (Fig.8), wherein a region on a side surface of the trench where the second layer is exposed is perpendicular to a main surface of the substrate (Fig.8), and a region on the side surface of the trench where the third layer is exposed (Fig.8) includes a first region from a surface of the second layer to a predetermined height in the third layer (near the second layer), the first region being perpendicular to the main surface of the substrate (Fig.8). However, Kuroski et al does not explicitly disclose and a second region from the predetermined height in the third layer to the surface of the third layer the second region being inclined with respect to the main surface of the substrate, a cross-sectional area of the trench at the second region in a plane parallel to a bottom surface of the trench increasing from a bottom surface side toward an upper surface side of the trench. On the other hand, Nakano et al discloses the third layer (32,Fig.9) is exposed includes a first region (32 vertical portion in 32) from a surface of the second layer (31) to a predetermined height in the third layer (near the bottom portion of 32), and a second region (slanted 29 in 32) from the predetermined height (from top of 32 to near the bottom of 32) in the third layer to the surface of the third layer (Fig.9), the first region being perpendicular to the main surface of the substrate (bottom portion of Fig.9), the second region being inclined with respect to the main surface of the substrate (Fig.9) , a cross-sectional area of the trench at the second region (Fig.9) in a plane parallel to a bottom surface of the trench (plane parallel to x direction) increasing from a bottom surface side (from near second layer, Fig.9) toward an upper surface side of the trench (top of 32; the upper side is wider than near bottom of 32). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Kuroski et al according to the teachings of the Nakano such that a second region from the predetermined height in the third layer to the surface of the third layer the second region being inclined with respect to the main surface of the substrate, a cross-sectional area of the trench at the second region in a plane parallel to a bottom surface of the trench increasing from a bottom surface side toward an upper surface side of the trench, in order to make a device that can withstand high voltage near the top of the device. With respect to claim 2, Kuroski et al does not explicitly disclose further comprising: an ion implantation region formed by implanting ions into a predetermined region of the surface of the second layer; and a p-type impurity region formed in a region having a predetermined depth from a surface of the first layer and a width of the second layer under the ion implantation region. On the other hand, Nakano et al discloses an ion implantation region (12,Fig.2a) formed by implanting ions into a predetermined region of the surface of the second layer (22); and a p-type impurity region (14) formed in a region (under 12) having a predetermined depth from a surface of the first layer (bottom of 22) and a width of the second layer under the ion implantation region (Fig.2a). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Kuroski et al according to the teachings of Nakano et al such that channel layer and source contact regions are formed, in order to make device functioning. Furthermore with respect to claim limitation “implanting ions”, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). With respect to claim 4, the arts cited above do not explicitly disclose wherein a width of the second region in a direction parallel to the main surface of the substrate is 0.1um to 0.3 um. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the second region in a direction parallel to the main surface of the substrate is 0.1um to 0.3 um, in order to use the device for high voltage application. Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuroski et al (US Pub No. 20180026131), in view of Nakano et al (US Pub No. 20150295079), in view of Saitoh et al (US Patent No. 10192967). With respect to claim 3, Nakano et al discloses an inclination of the second region is less than 90 degrees (Fig.8); however, the arts cited above do not explicitly disclose wherein an inclination angle of the second region is 15 degrees to 75 degrees. On the other hand, Saitoh et al discloses inclination angle of the second region is 15 degrees to 75 degrees (Col 5). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Saitoh et al such that inclination angle of the second region is 15 degrees to 75 degrees, in order to be able to deposit more dielectric material at the angled region to protect the gate from high voltage scenarios. Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALI NARAGHI/Examiner, Art Unit 2817
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Prosecution Timeline

Jun 23, 2023
Application Filed
Nov 15, 2025
Non-Final Rejection — §103, §112
Apr 06, 2026
Applicant Interview (Telephonic)
Apr 07, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+6.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 771 resolved cases by this examiner. Grant probability derived from career allow rate.

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