Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 11/25/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 1, 2, 6, 9, 10, 12, 14, 15, and 20 have been amended, claims 3, 17, and 18 have been canceled. Accordingly, pending in this application are claims 1-2, 4-16, and 19-20. Claims 1-2, 4-16, and 19-20 have been examined on the merits in this Office action.
Applicant’s amendment to title has overcome the objection to the Specification.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4-13, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 6, 7, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 101696705 B1 et al. (hereinafter “Shim”) in view of Ecton et al. (US 20240063127 A1; hereinafter “Ecton”).
In re claim 1, Shim discloses in figs. 4-14, a manufacturing method of a semiconductor package, comprising:
preparing a glass substrate 110 having a first side (e.g., top surface side; hereinafter “S1”) and a second side (e.g., bottom surface side; hereinafter “S2”) opposite to the first side (figs. 4-5; page 3),
the glass substrate 110 including a groove C recessed from the first side S1 and a hole TH extending from the first side S1 to the second side S2 of the glass substrate 110 and positioned at a side of the groove C (figs. 4-5; page 3, 5th paragraph),
the hole TH being exposed at the first side S1 and the second side S2 of the glass substrate 110 (fig. 5; page 3, 5th paragraph),
forming a conductive connection member 120 to fill inside the hole TH of the glass substrate (fig. 6; page 3, 8th paragraph);
attaching a semiconductor chip 140 inside the groove C on the glass substrate 110 (fig. 7; page 4, 3rd paragraph);
forming a first redistribution structure 150, 160 for connection with the semiconductor chip 140 and the conductive connection member 120 on the first side of the glass substrate S1 (figs. 9-11; page 4, 4th-5th paragraphs); and
after forming the first redistribution structure 150, 160, forming a second redistribution structure 170, 180 for connection (e.g., electrical connection through circuit element 160 on the second side) with the conductive connection member on the second side of the glass substrate S2 (figs. 12-14; page 4, 6th-7th paragraphs).
Shim does not expressly disclose:
the glass substrate having a thickness in a portion adjacent to the hole in a range between 300 µm and 500 µm and a thickness below the groove is between 50 µm and 100 µm.
In the same field of endeavor, Ecton discloses a semiconductor package (figs. 4A-4J) wherein:
the glass substrate 401 having a thickness in a portion adjacent to a hole 405 in a range is between approximately 50 μm and approximately 1,000 μm (¶43), which encompasses the claimed range of between 300 µm and 500 µm, and
wherein a thickness below the groove is more than 0 μm and less than 950 μm (“the depth of the cavity 220 may be between approximately 50 μm and approximately 500 μm”; ¶33. Therefore, a thickness of a portion of the glass substrate 110 below the groove C is more than 0 μm and less than 950 μm), which encompasses the claimed range of between 50 µm and 100 µm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ecton and Shim and arrive at claimed ranges for the substrate thickness and depth of the cavity such that fine die-to-die interconnections for die tiling can be accomplished through this architecture (¶2-4 of Ecton).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
In re claim 2, Shim as modified by Ecton discloses the manufacturing method of the semiconductor package of claim 1.
Shim further discloses in figs. 4-14, wherein the hole TH is one of a plurality of holes that are positioned on both sides of the groove C, respectively,
wherein a width of each of the plurality of holes TH is 30 µm or less (page 3, 7th paragraph), which overlaps the claimed range of between 20 µm and 200 µm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Shim and arrive at claimed range for the width of the through holes to increase the density of the through holes and to improve electrical characteristics of the semiconductor package (page 3, 7th paragraph).
Shim does not expressly disclose:
wherein a depth of each of the plurality of holes is about 300 pm or more and about 500 pm or less.
In the same field of endeavor, Ecton discloses a semiconductor package (figs. 4A-4J) wherein:
a depth of each of a plurality of holes 405 is between approximately 50 μm and approximately 1,000 μm (¶32, ¶44; “the glass substrate 201 may have a thickness between approximately 50 μm and approximately 1,000 μm”, “the vias 405 may pass through an entire thickness of the glass substrate 401”), which encompasses the claimed range of between 300 µm and 500 µm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ecton and Shim and arrive at claimed ranges for depths of the through holes such that fine die-to-die interconnections for die tiling can be accomplished through this architecture (¶2-4 of Ecton).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
In re claim 6, same as claim 2 above.
In re claim 7, Shim as modified by Ecton discloses the manufacturing method of the semiconductor package of claim 1.
Shim further discloses in figs. 4-14, wherein the semiconductor chip 14 is attached to a bottom surface of the glass substrate inside the groove C, and wherein an adhesive member is positioned between the semiconductor chip 140 and the glass substrate 110 (page 4, 3rd paragraph).
In re claim 20, Shim discloses in fig. 14, a semiconductor package comprising:
a glass substrate 110 having a first side (e.g., top surface side; hereinafter “S1”) and a second side (e.g., bottom surface side; hereinafter “S2”) opposite to the first side (page 3, 5th paragraph),
the glass substrate 110 including a groove C recessed from the first side S1 and a plurality of holes TH extending from the first side S1 to the second side S2 of the glass substrate 110 and positioned around the groove C (page 3, 5th paragraph);
a semiconductor chip 140 positioned inside the groove C on the glass substrate 110 and attached to the glass substrate 110 (page 4, 3rd paragraph);
a plurality of conductive connection members 120 positioned inside the plurality of holes TH of the glass substrate, respectively (page 3, 8th paragraph);
a first redistribution structure 150, 160 positioned on the first side of the glass substrate S1 and connected to the semiconductor chip 140 and the plurality of conductive connection members 122 (page 4, 4th-5th paragraphs);
a connection member 180 positioned on the first redistribution structure 150, 160 (page 4, 6th-7th paragraphs); and
a second redistribution structure 170, 180 positioned on the second side of the glass substrate S2 and connected to the plurality of conductive connection members 122 (page 4, 6th-7th paragraphs),
wherein a width of each of the plurality of holes TH is 30 µm or less (page 3, 7th paragraph), which overlaps the claimed range of between 20 µm and 200 µm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Shim and arrive at claimed range for the width of the through holes to increase the density of the through holes and to improve electrical characteristics of the semiconductor package (page 3, 7th paragraph).
Shim does not expressly disclose:
wherein a depth of each of the plurality of holes is between 300 µm and 500 µm,
wherein a thickness of a portion of the glass substrate adjacent to the plurality of holes is between 300 µm and 500 µm, and
wherein a thickness of a portion of the glass substrate below the groove is between 50 µm and 100 µm.
In the same field of endeavor, Ecton discloses a semiconductor package (figs. 4A-4J) wherein:
a depth of each of a plurality of holes 405 is between approximately 50 μm and approximately 1,000 μm (¶32, ¶44; “the glass substrate 201 may have a thickness between approximately 50 μm and approximately 1,000 μm”, “the vias 405 may pass through an entire thickness of the glass substrate 401”), which encompasses the claimed range of between 300 µm and 500 µm,
wherein a thickness of a portion of the glass substrate 401 adjacent to the plurality of holes is between approximately 50 μm and approximately 1,000 μm (¶43), which encompasses the claimed range of between 300 µm and 500 µm, and
wherein a thickness of a portion of the glass substrate below the groove is more than 0 μm and less than 950 μm (“the depth of the cavity 220 may be between approximately 50 μm and approximately 500 μm”; ¶33. Therefore, a thickness of a portion of the glass substrate 110 below the groove C is more than 0 μm and less than 950 μm), which encompasses the claimed range of between 50 µm and 100 µm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ecton and Shim and arrive at claimed ranges for the substrate thickness, depths of the through holes and depth of the cavity such that fine die-to-die interconnections for die tiling can be accomplished through this architecture (¶2-4 of Ecton).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim/Ecton, as applied to claim 1 above and further in view of Sato et al. (US 20220102310 A1; hereinafter “Sato”).
In re claim 4, Shim as modified by Ecton discloses the manufacturing method of the semiconductor package of claim 1.
Shim as modified by Ecton does not expressly disclose wherein an angle of inclination between a bottom surface and a side surface of the glass substrate inside the groove is about 90 degrees or more and about 95 degrees or less.
In the same field of endeavor, Sato discloses a method of making a semiconductor package (figs. 7a-7j) wherein an angle of inclination between a bottom surface 11a and a side surface 11b of a glass substrate 10 inside a groove 11 is about 90 degrees or more and about 95 degrees or less (e.g., 92 to 95 degrees; ¶43, 41).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Sato into the package of Shim as modified by Ecton to ensure suppressing the occurrence of a positional shift of a semiconductor chip in the groove during resin sealing and forming a redistribution layer easily and accurately on the chip surface (¶6-7 of Sato).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Ecton, as applied to claim 1 above and further in view of Nakamura et al. (US 20220148956 A1; hereinafter “Nakamura”).
In re claim 5, Shim as modified by Ecton discloses the manufacturing method of the semiconductor package of claim 1 outlined above.
Shim as modified by Ecton does not expressly disclose wherein in the forming of the conductive connection member, the conductive connection member is formed by filling a conductive material in the form of paste inside the hole.
In the same field of endeavor, Nakamura discloses a method of making a semiconductor package (figs. 3A-3C) wherein in the forming of a conductive connection member 14, the conductive connection member is formed by filling a conductive material in the form of paste inside a via hole (¶30).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Nakamura into the package of Shim as modified by Ecton to uniformly fill the via hole and increase the bonding strength with the insulating substrate (¶30 of Nakamura).
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Ecton, as applied to claim 1 above and further in view of Rho et al. (US 20230307304 A1; hereinafter “Rho”).
In re claim 8, Shim as modified by Ecton discloses the manufacturing method of the semiconductor package of claim 1 outlined above.
Shim as modified by Ecton does not expressly disclose wherein the semiconductor chip comprises an electrode, and wherein the first redistribution structure is connected to the electrode of the semiconductor chip.
In the same field of endeavor, Rho discloses in figs. 3-4, a manufacturing method of a semiconductor package, wherein the semiconductor chip 40 comprises an electrode 283 (¶54, 128, 132), and wherein a first redistribution structure 25 (¶102-103) is connected to the electrode of the semiconductor chip 283.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Rho into the package of Shim as modified by Ecton to make heat emitting of an internal element be easier and improve mechanical and electrical properties (¶32 of Rho).
In re claim 9, Shim as modified by Ecton and Rho discloses the manufacturing method of the semiconductor package of claim 8.
Shim further discloses in figs. 4-14,
wherein the first redistribution structure comprises:
at least one wiring layer (e.g., top horizontal portions of layer 160) connected to the conductive connection member 120 and the semiconductor chip 140;
a pad portion (e.g., bottom portion of 160 which is in direct contact with 121) connected to the at least one wiring layer 160; and
an insulation layer 150 positioned between the at least one wiring layer 160 and the glass substrate 110, between wiring layers 160 of at least one wiring layer, and
between the at least one wiring layer (i.e., top horizontal portions of layer 160) and the pad portion (i.e., bottom portion of 160 which is in direct contact with 121).
In re claim 10, Shim as modified by Ecton and Rho discloses the manufacturing method of the semiconductor package of claim 9.
Shim further discloses in figs. 4-14, wherein the second redistribution structure comprises:
at least one wiring layer 180 connected to the conductive connection member 120; and
an insulation layer 190 positioned between the at least one wiring layer 180 and the glass substrate 110 and between wiring layers 180 of the at least one wiring layer.
In re claim 11, Shim as modified by Ecton and Rho discloses the manufacturing method of the semiconductor package of claim 9.
Shim further discloses in figs. 4-14, the method further comprising:
forming a connection member 180 (on side 110a) connected with the pad portion on the first redistribution structure 160.
In re claim 12, Shim as modified by Ecton and Rho discloses the manufacturing method of the semiconductor package of claim 1.
Shim as modified by Ecton does not expressly disclose wherein the glass substrate comprises a plurality of grooves, and a plurality of holes positioned around the respective grooves, and wherein a semiconductor chip is attached to the inside of each of the plurality of grooves.
Rho further discloses (figs. 3-4) wherein the glass substrate 21 comprises a plurality of grooves (e.g., plurality of grooves 232 in the space 281), and a plurality of holes 231 positioned around the respective grooves 232, and wherein a semiconductor chip 40 is attached to the inside of each of the plurality of grooves 232 (semiconductor chip 40 is attached to the inside of each of the plurality of grooves 232 via 283).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Rho into the package of Shim as modified by Ecton to accommodate plurality of chips into plurality of spaces and thereby can make heat emitting of an internal element be easier and improve mechanical and electrical properties (¶32 of Rho).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim as modified by Ecton and Rho, as applied to claim 12 above and further in view of Bryks et al. (US 20240113072 A1; hereinafter “Bryks”).
In re claim 13, Shim as modified by Ecton and Rho discloses the manufacturing method of the semiconductor package of claim 12 outlined above.
Shim as modified by Ecton and Rho does not expressly disclose separating the glass substrate into a plurality of semiconductor packages through a cutting process.
In the same field of endeavor, Bryks discloses a method of making a semiconductor package (figs. 15-16) comprising: separating a glass substrate 1003 into a plurality of semiconductor packages through a cutting process (¶157).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Bryks into the package of Shim as modified by Ecton and Rho to efficiently singulate glass substrate-based IC packages (¶1-3 of Bryks).
Allowable Subject Matter
Claims 15-16 and 19 are allowed.
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 14, none of the closest prior art, alone or in combination, discloses all the method steps including after providing the glass substrate including the groove and the hole, attaching a carrier substrate to the glass substrate; and separating the carrier substrate from the glass substrate after forming the first redistribution structure, wherein the second redistribution structure is formed after separating the carrier substrate from the glass substrate, in combination with all other limitations of claim 1.
In re claim 15, Shim discloses in figs. 4-14, a manufacturing method of a semiconductor package, comprising:
preparing a glass substrate 110 that includes a groove C and a hole TH positioned at a side of the groove C (figs. 4-5);
forming a conductive connection member 122 to fill the inside of the hole TH of the glass substrate (fig. 6);
attaching a semiconductor chip 140 to the inside of the groove C of the glass substrate (fig. 8);
forming a first redistribution structure 150, 160 for connection with the semiconductor chip 140 and the conductive connection member 122 on a first side of the glass substrate 110 (e.g., top surface side; hereinafter “S1”); and
forming a second redistribution structure 170, 180 for connection (e.g., electrical connection through circuit element 160 on the second side) with the conductive connection member 122 on a second side of the glass substrate (e.g., bottom surface side; hereinafter “S2”),
wherein the first distribution structure 150, 160 is formed to extend to the inside of the groove C, and
Wherein the semiconductor chip 140 is positioned on the first distribution structure 150, 160 inside the groove C.
Shim does not teach:
attaching a carrier substrate to the glass substrate;
separating the carrier substrate from the glass substrate;
forming a conductive connection member to fill the inside of the hole of the glass substrate using an electroplating process;
wherein the forming the conductive connection member and the forming at least a part of the first distribution structure are carried out in a single process,
wherein the semiconductor chip is attached after the forming the at least the part of the first distribution structure.
None of the closest prior art, alone or in combination, discloses all the method steps including attaching a carrier substrate to the glass substrate; separating the carrier substrate from the glass substrate; forming a conductive connection member to fill the inside of the hole of the glass substrate using an electroplating process; wherein the forming the conductive connection member and the forming at least a part of the first distribution structure are carried out in a single process, wherein the semiconductor chip is attached after the forming the at least the part of the first distribution structure, in combination with all other limitations of claim 15.
Claims 16 and 19 are indicated allowable based on their dependency on claim 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NILUFA RAHIM/ Primary Examiner, Art Unit 2893