DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 11/7/25 is acknowledged. The traversal is on the ground(s) that the species are not independent and distinct and do not have mutually exclusive characteristics. This is not found persuasive because an exhaustive search has been conducted on elected species 1 and the best prior art has been determined and applied as cited below to the elected claims. Sakurada et al (US 20130344658) which anticipates the elected species does not read upon nor anticipates the non-elected species. A second and burdensome search would be required to address the unelected patentably distinct species in efforts to find and determine the most relevant art. Applicant is entitled to invention/ one search per application. However, Applicant is reminded that should future prosecution determine allowable subject matter, and such subject matter be properly incorporated into the claims, rejoinder may be possible.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Sakurada et al (US 20130344658).
1. (Original) A semiconductor package, comprising:
a base semiconductor chip (Fig.1 (20) and [0030]);
a chip structure (Fig.1 (10b/10a) and [0030]) mounted on the base semiconductor chip (Fig.1 (20) and [0029]);
a connection terminal (Fig.1 (36) and [0042]) between the base semiconductor chip (Fig.1 (20) and [0029]) and the chip structure (Fig.1 (10b/10a) and [0030]); and
a molding layer (Fig.1 (37/32) and [0039-0040]) on the base semiconductor chip (Fig.1 (10b/10a) and [0030]), the molding layer (Fig.1 (37/32) and [0039-0040]) surrounding the chip structure (Fig.1 (10b/10a) and [0030]) and the connection terminal (Fig.1 (36) and [0042]), wherein the chip structure (Fig.1 (10b/10a) and [0030]) includes:
a first semiconductor chip (Fig.1 (10b- bottom) and [0030]) that includes a first frontside pad (Fig.1 (18b) and [0037]) and a first backside pad (Fig.1 (17b) and [0037]); and
a second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]) on the first semiconductor chip (Fig.1 (10b- bottom) and [0030]), the second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]) including a second frontside pad (Fig.1 (18b) and [0037]) and a second backside pad (Fig.1 (17b) and [0037]), wherein a lateral surface of the first semiconductor chip (Fig.1 (10b- bottom) and [0030]) is aligned with a lateral surface of the second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]), wherein the first semiconductor chip (Fig.1 (10b- bottom) and [0030]) includes a first integrated circuit (Fig.1 (14b) and [0032]) and the second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]) includes a second integrated circuit (Fig.1 (14b) and [0032]) the same as the first integrated circuit (Fig.1 (14b) and [0032]), wherein the first backside pad (Fig.1 (17b) and [0037]) and the second frontside pad (Fig.1 (18b) and [0037]) partially overlap each other when viewed in plan (Fig.2a/b) while being in direct contact with each other (Fig.1), and wherein the first backside pad (Fig.1 (17b) and [0037]) and the second frontside pad (Fig.1 (18b) and [0037]) include the same metal [0047/0052- Cu] and are formed into a single unitary piece (Fig.1).
2. (Currently Amended) The semiconductor package of claim 1 wherein each of the first (Fig.1 (10b- bottom) and [0030]) and second semiconductor chips (Fig.1 (10b- above bottom chip 10b) and [0030]) includes an active surface (Fig.1 (14b) and [0032- the face with the memory circuitry is the active surface]) and an inactive surface (Fig.1 (top of 10b)) opposite to the active surface (Fig.1 (14b) and [0032- the face with the memory circuitry is the active surface]), wherein the first integrated circuit (Fig.1 (14b) and [0032]) is on the active surface of the first semiconductor chip (Fig.1 (10b- bottom) and [0030]) and the second integrated circuit (Fig.1 (14b) and [0032]) is on the active surface of the second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]) and wherein the inactive surface of the first semiconductor chip (Fig.1 (top of 10b- bottom chip)) faces the active surface (Fig.1 (14b) and [0032]) of the second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]).
3. (Currently Amended) The semiconductor package of claim 1, wherein an integrated circuit of the base semiconductor chip (Fig.8 (10c) and [0082-logic chip]/Fig.1 (20) and [0030-wiring board])) is of a different type from the first integrated circuit (Fig.1 (14b ) and [0032- memory circuit]) of the first semiconductor chip (Fig.1 (10b- bottom) and [0030]) and the second integrated circuit (Fig.1 (14b ) and [0032- memory circuit]) of the second semiconductor chip (Fig.1 (10b- above bottom chip 10b) and [0030]).
4. (Original) The semiconductor package of claim 1, wherein a lateral surface of the molding layer (Fig.1 (37/32) and [0039-0040]) is vertically aligned with a lateral surface of the base semiconductor chip (Fig.1 (20) and [0030]).
5. (Original) The semiconductor package of claim 1, further comprising a non- conductive layer (Fig.1 (37) and [0039]) between the chip structure (Fig.1 (10b) and [0030]) and the base semiconductor chip (Fig.1 (20) and [0030]).
6. (Original) The semiconductor package of claim 1, wherein a distance between the chip structure and the base semiconductor chip is in a range of 10 um to 15 um [0035].
7. (Original) The semiconductor package of claim 1, wherein the connection terminal (Fig.1 (36) and [0042]) is between the base semiconductor chip (Fig.1 (20) and [0030]) and a bottom surface of the first frontside pad (Fig.1 (17b) and [0037]) of the first semiconductor chip (Fig.1 (10b- bottom chip) and [0030]), and wherein the connection terminal including a solder ball or a solder bump (Fig.1 (36) and [0042]).
8. (Original) The semiconductor package of claim 1, wherein the chip structure (Fig.1 (10b) and [0030]) includes a plurality of chip structures (Fig.110b/10a) and [0030]), and the plurality of chip structures are stacked in a vertical direction (Fig.1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 11056432); Park et al (US 2020/0098719); and Jang et al (US 20220415741) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M MENZ/Primary Examiner, Art Unit 2813
1/9/26
Prosecution Insights