DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statemen t(s) (IDS) submitted on 06/26/2023 have been considered by the E xaminer. Claim Objections Claim 17 id objected to because of the following informalities: Claim 17 recite s a term “ inputting an electrical signal to a first input pad connected a first pad ” in paragraph 3 . Examiner suggests amending the term to recite “ inputting an electrical signal to a first input pad connected to a first pad ” to restore clarity . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Regarding claim 12 , a limitation " electrical signal input to the first output pad " renders the claim indefinite because it is unclear how a pad designated as output pad is capable of receiving input signal. See MPEP § 2173.05(d). Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 8-11, 13-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jacobson et al. (US 20160254658 ; hereinafter Jacobson ) in view of Hirata et al. (US 20060001101 ). Regarding claim 1, Jacobson teaches in figure(s) 1-9 a substrate (para. 18- solid-state semiconductor circuit 100; fig. 4A - commonly known to be built on a substrate) comprising: a first input/output region (top section of 100; fig. 4A ) ; a first input pad (top input terminal of 102a) provided in the first input/output region; a first output pad (bottom output terminal of 102a) provided in the first input/output region; a first mounting region (left section of 100 ) ; a first positive pad (Vin+ pin) provided in the first mounting region and connected to the first input pad (@102a ) ; a first negative pad (Vin- pin) provided in the first mounting region connected to the first output pad (@102a ) ; a second positive pad (Cin+ terminal) provided in the first mounting region; a second negative pad (Cin- terminal) provided in the first mounting region; a second mounting region (right section of 100 ) ; a third positive pad (Co+ terminal) provided in the second mounting region and connected to the second positive pad (Cin+ terminal ) ; a third negative pad (Co- terminal) provided in the second mounting region and connected to the second negative pad (Cin- terminal ) ; a fourth positive pad (108a pin) provided in the second mounting region; a fourth negative pad (108b pin) provided in the second mounting region; a second input/output region (bottom section of 100 ) ; a second input pad (106a input terminal) provided in the second input/output region and connected to the fourth positive pad (108a pin) ; and a second output pad (106a output terminal) provided in the second input/output region and connected to the fourth negative pad (108b pin) . Jacobson does not teach explicitly substrate. However, Hirata teaches in figure(s) 1-4 substrate (substrate 10; fig. 2). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Jacobson by having substrate as taught by Hirata in order to provide solid-state semiconductor circuit. It is an obvious feature for the skilled man, as it is commonly known that solid-state semiconductor devices are built on a substrate as evidenced by " A semiconductor device has a supply pad to which a supply voltage is fed, a supply conductor that is electrically connected to the supply pad, an input/output pad via which a signal is fed in from outside or fed out to outside, an electrostatic protection device that is electrically connected to the input/output pad and that is electrically connected via the supply conductor to the supply pad, and an internal circuit that is electrically connected via a signal conductor to the input/output pad" (abstract of Hirata ) . Regarding claim 2, Jacobson teaches in figure(s) 1-9 the substrate of claim 1, further comprising: a base substrate (solid state of 100 implied substrate of Jacobson ; substrate 10 of fig. 2 of Hirata ) ; a first interconnection pattern, a second interconnection pattern, a third interconnection pattern, a fourth interconnection pattern, a fifth interconnection pattern and a sixth interconnection pattern that are provided on the base substrate, wherein the first interconnection pattern (104a) connects the first input pad (top input terminal of 102a) to the first positive pad (Vin+ pin) , wherein the second interconnection pattern (104b) connects the first output pad (bottom output terminal of 102a) to the first negative pad (Vin- pin) , wherein the third interconnection pattern ( Vout positive) connects the fourth positive pad (108a pin) to the second input pad (106a input terminal) , wherein the fourth interconnection pattern ( Vout negative) connects the fourth negative pad (108b pin) to the second output pad (106a output terminal) , wherein the fifth interconnection pattern connects the second positive pad (Cin+ terminal) to the third positive pad (Co+ terminal) , and wherein the sixth interconnection pattern connects the second negative pad (Cin- terminal) to the third negative pad (Co- terminal) . Regarding claim 8, Jacobson teaches in figure(s) 1-9 a device comprising: a substrate (para. 18- solid-state semiconductor circuit 100; fig. 4A - commonly known to be built on a substrate) comprising: a plurality of mounting regions (left and right regions of 100; figs. 4 ) ; a plurality of four-terminal capacitors (105, 110) that are mounted in the plurality of mounting regions; a first input/output region (top section of 100) electrically connected to a first mounting region from among the plurality of mounting regions (left and right sections of 100 ) ; a second input/output region (top section of 100) electrically connected to a second mounting region from among the plurality of mounting regions (left and right sections of 100) ; and a controller (para. 5 - electronic circuit breaker control module is in signal communication with the positive-side resonant capacitor cell and the negative-side resonant capacitor cell. The circuit breaker control module is configured to monitor a current level of at least one of the first and second drive currents. The circuit breaker control module is further configured to initiate at least one of the positive-side and negative-side controllable inductors from the passive mode into the full inductance mode in response to a current level of the first and second drive current, respectively, exceeding a current level threshold) configured to determine whether mounting faults (SC fault currents for 105, 110) of the plurality of four-terminal capacitors occur when the plurality of four-terminal capacitors are mounted in the plurality of mounting regions, by applying an electrical signal (signal @ 104a, IDC2) to each of the first input/output region and the second input/output region. Jacobson does not teach explicitly substrate. However, Hirata teaches in figure(s) 1-4 substrate (substrate 10; fig. 2). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Jacobson by having substrate as taught by Hirata in order to provide solid-state semiconductor circuit. It is an obvious feature for the skilled man, as it is commonly known that solid-state semiconductor devices are built on a substrate as evidenced by " A semiconductor device has a supply pad to which a supply voltage is fed, a supply conductor that is electrically connected to the supply pad, an input/output pad via which a signal is fed in from outside or fed out to outside, an electrostatic protection device that is electrically connected to the input/output pad and that is electrically connected via the supply conductor to the supply pad, and an internal circuit that is electrically connected via a signal conductor to the input/output pad" (abstract) . Regarding claim 9, Jacobson teaches in figure(s) 1-9 the device of claim 8, further comprising, in each of the plurality of mounting regions: a first positive pad ( Vin+ pin ) and a second positive pad (108a pin) that are electrically isolated from each other (capacitor 102a) ; and a first negative pad (Vin- pin) and a second negative pad (108b pin) that are electrically isolated (102b) from each other. Regarding claim 10, Jacobson teaches in figure(s) 1-9 the device of claim 9, a first input pad (top input terminal of 102a) provided in the first input/output region and connected to one from among the first positive pad (Vin+ pin) and the second positive pad in the first mounting region; and a first output pad (bottom output terminal of 102a) provided in the first input/output region and connected to one from among the first negative pad (Vin- pin) and the second negative pad in the first mounting region, and a second input pad (106a input terminal) provided in the second input/output region and connected to one from among the first positive pad and the second positive pad (108a) in the second mounting region; and a second output pad (106a output terminal) provided in the second input/output region and connected to one from among the first negative pad (Vin- ) and the second negative pad in the second mounting region. Regarding claim 11, Jacobson teaches in figure(s) 1-9 the device of claim 10, wherein the controller is further configured to determine that an open-circuit fault (para. 29 - first and second resonant capacitor cells 102 a -102 b appear as virtual open circuits during a portion of the load current cycle) has occurred while at least one from among the plurality of four-terminal capacitors is mounted on the substrate, based on the electrical signal input to the first input pad not being detected from the second input pad (106a input terminal) . Regarding claim 13, Jacobson teaches in figure(s) 1-9 the device of claim 10, wherein the controller is further configured to determine that a short-circuit fault has occurred while at least one from among the plurality of four-terminal capacitors is mounted on the substrate, based on the electrical signal input to the first input pad being detected from the first output pad (para. 6 - detecting a short-circuit fault condition and/or an overload condition between the source voltage and the load) . Regarding claim 14, Jacobson teaches in figure(s) 1-9 the device of claim 10, wherein the controller is further configured to determine that a short-circuit fault has occurred while at least one from among the plurality of four-terminal capacitors is mounted on the substrate, based on the electrical signal input to the second input pad being detected from the second output pad (para. 6 - detecting a short-circuit fault condition and/or an overload condition between the source voltage and the load) . Regarding claim 17, Jacobson teaches in figure(s) 1-9 a method comprising: mounting capacitors (capacitors 105, 110; figs. 4) in a first mounting region (top section of 100) and a second mounting region (bottom section of 100) of a substrate (para. 18- solid-state semiconductor circuit 100 implies substrate ; fig. 4A) , wherein a plurality of pads are provided in each of the first mounting region and the second mounting region; inputting an electrical signal to a first input pad (top input terminal of 102a) connected a first pad (Vin+ pin) from among the plurality of pads provided in the first mounting region; detecting the electrical signal from a first output pad (bottom output terminal of 102a) connected to a second pad (108a pin) from among the plurality of pads provided in the first mounting region, and a second input pad (106a input terminal) connected to a third pad (Co+ terminal) from among the plurality of pads provided in the second mounting region; and determining whether a fault has occurred in the mounting the capacitors, based on the electrical signal (SC fault currents for 105, 110) being detected from the first output pad (bottom output terminal of 102a) or the electrical signal not being detected from the second input pad. Jacobson does not teach explicitly substrate. However, Hirata teaches in figure(s) 1-4 substrate (substrate 10; fig. 2). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Jacobson by having substrate as taught by Hirata in order to provide solid-state semiconductor circuit. It is an obvious feature for the skilled man, as it is commonly known that solid-state semiconductor devices are built on a substrate as evidenced by " A semiconductor device has a supply pad to which a supply voltage is fed, a supply conductor that is electrically connected to the supply pad, an input/output pad via which a signal is fed in from outside or fed out to outside, an electrostatic protection device that is electrically connected to the input/output pad and that is electrically connected via the supply conductor to the supply pad, and an internal circuit that is electrically connected via a signal conductor to the input/output pad" (abstract) . Regarding claim 18, Jacobson teaches in figure(s) 1-9 the method of claim 17, wherein the determining whether the fault has occurred in the mounting the capacitors comprises determining that a short-circuit fault (para. 6 - detecting a short-circuit fault condition and/or an overload condition between the source voltage and the load) has occurred in the mounting the capacitors, based on the electrical signal being detected from the first output pad (para. 29 - first and second resonant capacitor cells 102 a -102 b appear as virtual open circuits during a portion of the load current cycle) . Regarding claim 19, Jacobson teaches in figure(s) 1-9 the method of claim 17, wherein the determining whether the fault has occurred in the mounting the capacitors comprises determining that an open-circuit fault (para. 29 - first and second resonant capacitor cells 102 a -102 b appear as virtual open circuits during a portion of the load current cycle) has occurred in the mounting the capacitors, based on the electrical signal not being detected from the second input pad (106a input terminal) . Regarding claim 20, Jacobson teaches in figure(s) 1-9 the method of claim 17, wherein the electrical signal has a predetermined level of voltage, and wherein the determining whether the fault has occurred in the mounting the capacitors comprises determining whether the fault has occurred in the mounting the capacitors by detecting a voltage of each of the first output pad and the second input pad (para. 37 - Based on the monitored conditions and threshold voltages, the circuit breaker control module 202 (i.e., the microcontroller) is configured to output one or more control signals for controlling various components of the ZCS circuit breaker 100) . Claim(s) 4 are rejected under 35 U.S.C. 103 as being unpatentable over Jacobson in view of Hirata , and further in view of Khazhinsky et al. (US 7593202 ). Regarding claim 4, Jacobson teaches in figure(s) 1-9 the substrate of claim 1, Jacobson does not teach wherein the first positive pad is electronically isolated from the second positive pad, wherein the first negative pad is electronically isolated from the second negative pad, wherein the third positive pad is electronically isolated from the fourth positive pad, and wherein the third negative pad is electronically isolated from the fourth negative pad. However, Khazhinsky teaches in figure(s) 3-5 explicitly wherein the first positive pad (OVDD2; fig. 3) is electronically isolated from the second positive pad (OVDD1) , wherein the first negative pad (OVSS2) is electronically isolated from the second negative pad (OVSS1) , wherein the third positive pad (OVDD1) is electronically isolated from the fourth positive pad (OVDD2) , and wherein the third negative pad (OVSS1) is electronically isolated from the fourth negative pad (OVSS2) . It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Jacobson by having wherein the first positive pad is electronically isolated from the second positive pad, wherein the first negative pad is electronically isolated from the second negative pad, wherein the third positive pad is electronically isolated from the fourth positive pad, and wherein the third negative pad is electronically isolated from the fourth negative pad as taught by Khazhinsky in order to provide some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention as evidenced by " each of the plurality of input/output cells has a bonding pad for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element for a respective second power domain" (abstract) . Allowable Subject Matter Claim(s) 3, 5-7 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3 , the prior arts of record do not fairly teach or suggest “ wherein the first input/output region, the second input/output region, the first mounting region, and the second mounting region are provided on a surface of the base substrate, and wherein the base substrate comprises a redistribution layer, and wherein the redistribution layer comprises the first interconnection pattern, the second interconnection pattern, the third interconnection pattern, the fourth interconnection pattern, the fifth interconnection pattern, and the sixth interconnection pattern ” including all of the limitations of the base claim and any intervening claims. Regarding claim (s) 5 and 15 , the prior arts of record do not fairly teach or suggest “ wherein the first positive pad and the second positive pad are arranged in a first direction, and wherein the first negative pad and the second negative pad are arranged in a second direction intersecting the first direction ” including all of the limitations of the base claim and any intervening claims. C laim(s) 6-7 , 16 are objected for depend ent upon objected base claim (s) . Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See the List of References cited in the US PT0-892. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664 . The examiner can normally be reached on 8-5 PM (PST) . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AKM ZAKARIA/ Primary Examiner, Art Unit 28 5 8