DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/04/2026 have been fully considered but they are not persuasive. Specifically, claim 1 has been amended to additionally recite wherein the contact region is executed to lead the contact region to be in contact with the base region, language previously present in claims 10 and 11. However, previously relied upon Kyogoku teaches wherein the contact region (32) is in contact with the base region (28). Therefore the obviousness rejection of claim 1 is maintained as detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,3,5-6,12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0083101 A1 to Kyogoku et al., “Kyogoku”, in view of U.S. Patent Application Publication Number 2019/0229013 A1 to Huesken et al., “Huesken”.
Regarding claim 1, Kyogoku discloses a method of manufacturing a semiconductor device comprising:
forming (FIG. 7) a first trench (21, ¶ [0057]-[0060]) from an upper surface side of a semiconductor substrate (24) of a first conductivity-type (n-type);
burying (e.g. FIG. 14) the first trench with an insulating gate electrode structure (oxide 60, gate 61, ¶ [0127],[0128]);
forming (FIG. 4) a base region (28, ¶ [0082]-[0086]) of a second conductivity-type (p-type) at an upper part of the semiconductor substrate so as to be in contact with the first trench (when the first trench is formed);
forming a first main electrode region (e.g. region of 30 near 22, ¶ [0087]-[0090]) of the first conductivity-type (n-type) at an upper part of the base region (28) so as to be in contact with the first trench (when the first trench 21 is formed);
forming (FIG. 7) a second trench (22, ¶ [0061]-[0066]) by removing a part of the first main electrode region (30);
implanting (FIG. 11, ¶ [0121],[0122]) first impurity ions (“N”) of the first conductivity-type entirely into a side wall surface of the second trench (22) from a diagonally upper side;
implanting (FIG. 10, ¶ [0119],[0120]) second impurity ions (“Al”) of the second conductivity-type into a bottom surface of the second trench (22) so as to form a contact region (32) of the second conductivity-type at a bottom of the second trench; and
forming a second main electrode region (14, ¶ [0078]) on a bottom surface side of the semiconductor substrate,
wherein the implanting (FIG. 11) of the first impurity ions is executed to include a corner defined by the bottom surface of the second trench (22) and the side wall surface of the second trench (22, since the implant is executed to implant at angle θ2 through the corner, ¶ [0121]-[0124]),
the forming the contact region (FIG. 10 region 32) is executed to lead the contact region (32) to be in contact (as pictured, side of 32 contacts side of 28) with the base region (28).
Kyogoku fails to clearly teach wherein the second main electrode region (14) is of the second conductivity-type. More generally, Kyogoku teaches a MOSFET with a drain (14) rather than an insulated gate bipolar transistor (IGBT) with a second conductivity-type region on the bottom of the substrate.
Huesken teaches (e.g. FIG 6) an insulated gate bipolar transistor (¶ [0002],[0009],[0020],[0022],[0031],[0050]) wherein a second main electrode (134, ¶ [0112]-[0115]) is of a second conductivity-type (p-type). More generally, Huesken teaches both MOSFET (FIG 5) and IGBTs (FIG 6).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Kyogoku as applied to an IGBT as exemplified by Huesken in order to form an IGBT which benefits from low on-state voltage and high robustness against avalanche and over-current turn-off (Huesken ¶ [0002]) with the implanted regions within the trench as taught by Kyogoku in order to suppress the extension of a depletion layer extending from the implanted region within the trench thereby reducing on-resistance (Kyogoku ¶ [0103]) and since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case it would have been obvious to one having ordinary skill in the art to have applied (B) Simple substitution of the n-type rear contact of a MOSFET with a p-type rear contact forming an IGBT with the predictable and desired result of forming a suitable contact for a high voltage transistor device.
Examiner’s Note: the language “wherein the implanting of the first impurity ions is executed to include a corner defined by the bottom surface of the second trench and the side wall surface of the second trench” is interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) to include executing an implantation where the impurities pass through the corner and not necessarily present at the corner.
Regarding claim 3, Kyogoku in view of Huesken yields the method of manufacturing the semiconductor device of claim 1, and Kyogoku further teaches (FIG. 11) wherein the implanting the first impurity ions (“N”) is executed to avoid a middle part of the bottom surface of the second trench (33 is only formed at sides as pictured).
Regarding claim 5, Kyogoku in view of Huesken yields the method of manufacturing the semiconductor device of claim 1, and Kyogoku further teaches (FIG. 11) wherein the implanting the first impurity ions (“N”) is executed to implant the impurity ions into side wall surfaces on both sides of the second trench (33 is formed on both sides of trench 22).
Regarding claim 6, Kyogoku in view of Huesken yields the method of manufacturing the semiconductor device of claim 1, and Kyogoku further teaches (FIG. 11) wherein the implanting the first impurity ions (“N”) is executed to implant the impurity ions into one of side wall surfaces of the second trench (both sidewalls comprises “one of the side wall surfaces” since the term “comprising” is open-ended and may include additional elements such as implanting into both sidewalls, MPEP 2111.03).
Regarding claim 12, Kyogoku in view of Huesken yields the method of manufacturing the semiconductor device of claim 1, and Kyogoku in view of Huesken further yields the wherein the insulated gate electrode structure (Kyogoku 16 and 18, ¶ [0049], from 60 and 61, ¶ [0127]-[0129]), the base region (Kyogoku 28), the first main electrode region (Kyogoku near 30), and the second main electrode region (Kyogoku near 24,Huesken region 134) implement an insulated gate bipolar transistor (Huesken ¶ [0002],[0009],[0020],[0022],[0031],[0050]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0083101 A1 to Kyogoku et al., “Kyogoku”, in view of U.S. Patent Application Publication Number 2019/0229013 A1 to Huesken et al., “Huesken”, as applied to claim 1 above, and further in view of U.S. Patent Application Publication Number 2011/0233606 A1 to Hsieh, “Hsieh”.
Regarding claim 4, although Kyogoku in view of Huesken yields the method of manufacturing the semiconductor device of claim 1, Kyogoku and Huesken fail to clearly teach wherein an opening width of the second trench is greater than a width of the bottom surface of the second trench.
Hsieh teaches modifying a second trench with straight sidewalls (FIG. 1) by forming a second trench (Fig. 4) with an opening width greater than a width at the bottom surface of the second trench (due to tapered sidewalls of α1 and α2, ¶ [0015]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Kyogoku in view of Huesken with the second trench having tapered sidewalls as taught by Hsieh in order to ensure the body contact covers the entire sidewalls of the opening thereby further enhancing unclamp inductive switching (UIS) performance (Hsieh ¶ [0009],[0015]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0083101 A1 to Kyogoku et al., “Kyogoku”, in view of U.S. Patent Application Publication Number 2019/0229013 A1 to Huesken et al., “Huesken”, as applied to claim 1 above, and further in view of U.S. Patent Application Publication Number 2011/0193100 A1 to Tsuchiya et al., “Tsuchiya”.
Regarding claim 9, although Kyogoku in view of Huesken yields the method of manufacturing the semiconductor device of claim 1, Kyogoku fails to clearly teach wherein the first impurity ions (n-type) are phosphorus, and the second impurity ions (p-type) are boron.
Tsuchiya teaches wherein first impurity ions (n-type) maybe be phosphorus (¶ [0065]) and second impurity ions (p-type) are boron (¶ [0066]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Kyogoku in view of Huesken by selecting phosphorus and boron as the first and second impurity type ions as exemplified by Tsuchiya
since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case it would have been obvious to one having ordinary skill in the art to have applied (B) simple substitution of a known n-type and known p-type dopants with the predictable and desired result of forming suitably doped regions, or similarly (E ) obvious to try a finite number of known and identified n-type (Group 4, i.e. nitrogen, phosphorus, arsenic) and p-type (Group 2, i.e. boron, aluminum, gallium) with the predictable and desirable result of forming suitable doped regions.
Allowable Subject Matter
Claims 7-8 are allowed.
Claims 10-11,13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Kyogoku teaches implanting first and second impurity ions into a second trench as discussed above. Prior art e.g. U.S. Patent Application Publication Number 2007/0093019 A1 to Rieger et al. teaches a method of manufacturing a semiconductor device comprising:
forming (FIG 1a) a first trench (trench filled with 21/22/23, ¶ [0031]) from an upper surface side of a semiconductor substrate (100) of a first conductivity-type (drift 13, ¶ [0030]);
burying the first trench with an insulated (22) gate electrode (21) structure (¶ [0074],[0075]);
forming a base region (12, ¶ [0033]) of a second conductivity-type at an upper part of the semiconductor substrate so as to be in contact with the first trench (i.e. the resulting structure has 12 in contact with the gate trench 22/21);
forming (FIG 1b) a first main electrode region (regions covered with 11) of the first conductivity-type at an upper part of the base region so as to be in contact with the first trench (i.e. the resulting structure has 11 in contact with the gate trench 22/21);
forming (FIG 1b) a second trench (15, ¶ [0033],[0034]) by removing a part of the first main electrode region (11);
implanting (FIG 1e region 17, ¶ [0056]) first impurity ions of the first conductivity-type (n-type, same as drift 13) entirely into a side wall surface of the second trench from a diagonally upper side (“suitable implantation angle” ¶ [0066]);
implanting (FIG. 1e, region 16) second impurity ions (p-type) of the second conductivity-type into a bottom surface of the second trench (15) so as to form a contact region (16) of the second conductivity-type at a bottom of the second trench; and
forming a second main electrode region (14) of the second conductivity-type (complementary doping for IGBT, ¶ [0030]) on a bottom surface side of the semiconductor substrate, as discussed previously.
However, prior art fails to reasonably teach or suggest additionally wherein a dose of the first impurity ions to be implanted is 1% or greater and 10% or smaller of a dose of the second impurity regions, together with all of the other limitations of claim 8.
Additionally, prior art fails to reasonably teach or suggest wherein an acceleration energy upon the implanting of the first impurity ions is higher than an acceleration energy upon the implanting the second impurity ions, together with all of the other limitations of claim 8 as claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Eric A. Ward/ Primary Examiner, Art Unit 2891
Prosecution Insights