DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 8-10, 13, 14 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (US 2016/0042960), (hereinafter, KIM).
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RE Claim 1, KIM discloses a 3D semiconductor integrated circuit device a method of making the same. KIM discloses in FIGS. 1-13 a semiconductor structure, comprising a vertical transistor, the vertical transistor [0008] comprising:
a semiconductor body 110a extending in a first direction “vertical direction”, the semiconductor body 110a comprising a source/drain, referring to FIG. 11 at one end of the semiconductor body;
a gate structure 120/115 “surrounding structure” coupled to at least one side of the semiconductor body 110a, the gate structure comprising a gate dielectric 115 and a gate electrode 120;
an epitaxial structure 142 “selective epitaxial (SEG) layer” coupled to the source/drain of the semiconductor body 110a, referring to FIG. 11: and
a silicide layer 150 coupled to the epitaxial structure 142, and the epitaxial structure 142 “selective epitaxial (SEG) layer” being between the source/drain and the silicide layer 150 in the first direction “vertical direction”, wherein the epitaxial structure 142 comprises more than one side surface extending in the first direction “vertical direction”, and the silicide layer 150 at least partially covers at least one side surface “top side” of the epitaxial structure 142;
an area of a top surface of the epitaxial structure 150 is larger than an area of a top surface of the source/drain, since the width of the (SEG) layer 142 is wider than the source/drain and the contact area of the SEG layer is increased [0031], and the top surface of the epitaxial structure 142 and the top surface of the source/drain extend in a first plane perpendicular to the first direction, referring to FIG. 11: and
an area of a top surface of the silicide layer 150 is larger than the area of the top surface of the source/drain, referring to FIG. 11 [0026 and 0031].
RE Claim 2, KIM discloses a semiconductor structure, wherein
the source/drain comprises more than one side surface “top-side, left-sidewall and right-sidewall” extending in the first direction “vertical direction”, and the epitaxial structure 142 at least partially covers at least one side second surface of the source/drain, the at least one second side surface being vertical to the first surface plane, referring to FIG. 11. Since the epitaxial structure 142 is in direct contact with “top-side, left-sidewall and right-sidewall”, the claimed limitation is met.
RE Claim 4, KIM discloses a semiconductor structure, wherein the epitaxial structure 142 comprises more than one side surface extending in the first direction “vertical direction”, and the more than one side surface of the epitaxial structure 142 is exposed from the silicide layer 150, referring to FIG. 11.
RE Claim 5, KIM discloses a semiconductor structure, further comprising a first isolation layer 135 “ILD” surrounding the semiconductor body 110a, wherein
the source/drain comprises more than one side surface extending in the first direction “vertical direction”, and the top surface and at least part of a second at least one side surface of the source/drain is exposed from the first isolation layer 135, referring to FIG. 11; and
the epitaxial structure 142 covers the first top surface and at least part of the side surface of the source/drain.
RE Claim 8, KIM discloses a semiconductor structure, wherein
a dielectric structure 115 is disposed between the silicide layer 150 and the gate structure 115, and electrically isolates is the silicide layer 150 from the gate structure [0021].
RE Claim 9, KIM discloses a semiconductor structure, further comprising:
a landing layer covered the silicide layer 150, referring to annotated FIG. 11 above; and
a metal contact 155 “lower electrode” extended through the landing layer and in contact with a second the top surface of the silicide layer 150, wherein
an area of a surface of the metal contact in touch with the silicide layer is smaller than or equal to the area of the top surface of the silicide layer 150, referring to FIGS. 2 and 11, since the opening H of FIG. 2, in which the SEG layer 142, the silicide layer 150 and lower metal electrode 155 are formed has a trapezoidal shape wherein the lower portion has a narrower width a1 than the upper portion width a2, hence meeting the claimed limitation.
RE Claims 10, KIM does not disclose a semiconductor structure, wherein the silicide layer comprises elements of Titanium (Ti), Cobalt (Co), or nickel platinum alloy (NiPt). Since the metal layer 145 deposited to react with epitaxial layer 142 to form the metal silicide layer 150 comprising a stack of titanium and titanium nitride layers [0025], hence meeting the claimed limitation.
RE Claim 13, KIM discloses a 3D semiconductor integrated circuit device a method of making the same. KIM discloses in FIGS. 1-13 a method for forming a semiconductor structure, comprising:
forming a semiconductor body 110a of the semiconductor structure extending in a first direction “vertical direction” from a substrate 100;
forming a gate structure 115/120 on at least one side of the semiconductor body 110a;
forming a source/drain “S/D”, referring to FIGS. 2, 8 and 11 at a distal end of the semiconductor body 110a away from the substrate 100;
forming a first isolation layer 135 “ILD” surrounding the semiconductor body 110a and the gate structure 115/120;
forming an epitaxial structure 142 “SEG, selective epitaxillay grown layer” coupled to the source/drain “S/D” of the semiconductor body; and
forming a silicide layer 150 coupled to the epitaxial structure 142, and the epitaxial structure 142 being between the source/drain “S/D” and the silicide layer 150 in the first direction “vertical direction”; wherein
at least part of the silicide 150 is above the source/drain “S/D”, referring to FIGS. 8 and 11; and
wherein the epitaxial structure 142 comprises more than one side surface extending in the first direction “vertical direction”, and wherein the silicide layer 150 at least partially covers at least one side surface “top side” of the epitaxial structure 142;
an area of a top surface of the epitaxial structure 142 is larger than an area of a top surface of the source/drain “S/D”, and the top surface of the epitaxial structure 142 and the top surface of the source/drain “S/D” extend in a first plane perpendicular to the first direction, referring to FIGS. 8 and 11. Since the epitaxial structure 142 is in direct contact with “top-side, left-sidewall and right-sidewall”, the claimed limitation is met; and
an area of a top surface of the silicide layer 150 is larger than the area of the top a first surface of the source/drain “S/D”, referring to FIGS. 8 and 11. Since the opening H of FIG. 2, in which the SEG layer 142, the silicide layer 150 and lower metal electrode 155 are formed has a trapezoidal shape wherein the lower portion has a narrower width a1 than the upper portion width a2, hence meeting the claimed limitation.
RE Claim 14, KIM discloses a method, wherein a first surface “top” and at least part of a second surface “upper sidewall surfaces” of the source/drain “S/D” are exposed from the first isolation layer 135, the second surface being vertical to the first surface “upper sidewall surfaces”, and the silicide layer 150 is formed on the first surface “top surface” and at least part of a second surface of the source/drain “S/D”, referring to FIG. 8.
RE Claim 16, KIM discloses a method, wherein forming the silicide layer 150 comprises:
depositing a metal layer 145 covering the top surface and the at least part of a side surface of the source/drain exposed from the first isolation layer 135, referring to FIG. 5; and
heating the metal layer 145 to form the silicide layer 150m referring to FIGS. 4-6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 6, 7, 11 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable KIM et al. (US 2016/0042960), (hereinafter, KIM) in view of Hung et al. (US 2016/0013104), (hereinafter, Hung).
RE Claim 6 and 7, KIM does not disclose a semiconductor structure, further comprising a second isolation layer surrounding the epitaxial structure, wherein
the epitaxial structure comprises more than one side surface extending in the first direction and being surrounded by the second isolation layer; and
a first the top surface of the epitaxial structure is exposed from the second isolation layer and covered by the silicide layer; or further comprising a second isolation layer surrounding the silicide layer, wherein a second top surface of the silicide layer is exposed from the second isolation layer.
However, in the same field of endeavor, Hung discloses a semiconductor, including vertical transistors, and a method of making the same, wherein a first and second dielectric layers 32 and 30 surrounding an epitaxially grown layer 28 and silicide layer 52, while the top surfaces of the epitaxially grown layer 28 and silicide layer 52 are exposed from the first and second isolations layers 32 and 30.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use a similar interconnect structure to Hung’s disclosure for KIM as a well-known interconnect structure in order to achieve a better connectivity while minimizing cross-talk.
RE Claims 11, KIM does not disclose a semiconductor structure, wherein wherein the silicide layer comprises titanium disilicide layer (TiSi2) in a face-centered orthorhombic structure (C54 phase).
However, in the same field of endeavor, Hung discloses a semiconductor device, including vertical transistor, and a method of making the same, wherein silicide layer 52 comprises Titanium, cobalt [0028], wherein the silicide layer comprises titanium disilicide layer (TiSi2) in a face-centered orthorhombic structure (C54 phase) [0027].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use the titanium disilicide (TiSi2) “C54 phase” of Hung disclosure as the silicide for KIM’s vertical transistor contact, as a well-known low resistivity silicide material in order to achieve better connectivity with much lower electrical resistivity.
RE Claim 17, KIM disclose a method, wherein heating the metal layer comprises:
depositing a metal nitride “TiN” on the metal layer “Ti”, forming the metal stack layer 145 [0025];
KIM does not disclose a method,
performing a first rapid thermal annealing (RTA) on the metal layer and the metal nitride at a first temperature, configured to form the silicide layer having a body-centered tetragonal crystal structure (C49 phase); and
performing a second RTA on the metal layer at a second temperature higher than the first temperature.
However, in the same field of endeavor, Hung discloses a semiconductor device, including vertical transistor, and a method of making the same, wherein silicide layer 52 comprises Titanium, cobalt, wherein in forming the metal silicide layer 52 comprising:
depositing a metal nitride 50 “TiN” on the metal layer 48 “Ti or Co or Ni” [0028];
performing a first rapid thermal annealing (RTA) “10 second” on the metal layer and the metal nitride at a first temperature, 500-600 oC configured to form the silicide layer having a body-centered tetragonal crystal structure (C49 phase) 52; and
performing a second RTA on the metal layer at a second temperature 600-900 oC higher than the first temperature [0022].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use the well-known process of Hung in order to form a body-centered tetragonal crystal structure (C49 phase) as the metal silicide layer of KIM vertical transistor in or order to control the crystalline phase silicide layer and hence its resistivity.
RE Claim 18, KIM discloses a method, wherein
a first surface of the source/drain “S/D” “top surface” is exposed from the first isolation layer 135, referring to FIG. 5:
the epitaxial structure 142 is formed on the top surface of the source/drain “S/D” before forming the silicide layer 150; and
the silicide layer 150 is formed based on the epitaxial structure 142.
RE Claim 19, KIM discloses a method, further comprising:
after forming a first isolation layer 135, etching the first isolation layer to expose at least part of a side surface of the source/drain “S/D”, the side surface of the source/drain being vertical to the top surface of the source/drain, referring to FIG. 2; wherein
the epitaxial structure 142 is grown from the at least part of the second side surface of the source/drain “S/D” exposed from the first isolation layer, referring to FIG. 11.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable KIM et al. (US 2016/0042960), (hereinafter, KIM) in view of Kim et al. (US 2015/0214289), (hereinafter, Kim).
RE Claim 12, KIM discloses a semiconductor integrated circuit, comprising:
a semiconductor structure comprising a plurality of vertical transistors, referring to FIGS. 8 and 11; wherein
each vertical transistor of at least part of the plurality of vertical transistors comprises:
a semiconductor body extending 110a in a first direction “vertical direction”, the semiconductor body 110a comprising a source/drain “S/D”at one end of the semiconductor body 110a;
a gate structure 115/120 coupled to at least one side of the semiconductor body 110a, the gate structure 115/120 comprising a gate dielectric 115 and a gate electrode 120;
an epitaxial structure 142 coupled to the source/drain “S/D” of the semiconductor body 110a; and
a silicide layer 150 coupled to the epitaxial structure 142, and the epitaxial structure 142 being between the source/drain “S/D” and the silicide layer 150 in the first direction “vertical direction”, wherein the epitaxial structure 142 comprises more than one side surface extending in the first direction “vertical direction”, and wherein the silicide layer 150 at least partially covers at least one side surface “top side” of the epitaxial structure 142;
an area of a top surface of the epitaxial structure 142 is larger than an area of a top surface of the source/drain “S/D”. Since the opening H of FIG. 2, in which the SEG layer 142, the silicide layer 150 and lower metal electrode 155 are formed has a trapezoidal shape wherein the lower portion has a narrower width a1 than the upper portion width a2, hence meeting the claimed limitation, and
the top surface of the epitaxial structure 142 and the top surface of the source/drain “S/D” extend in a first plane perpendicular to the first direction “vertical direction”, referring to FIGS. 8 and 11; and
an area of a top surface of the silicide layer 150 is larger than the area of the top surface of the source/drain “S/D”. Since the opening H of FIG. 2, in which the SEG layer 142, the silicide layer 150 and lower metal electrode 155 are formed has a trapezoidal shape wherein the lower portion has a narrower width a1 than the upper portion width a2, hence meeting the claimed limitation.
KIM does not disclose a system, comprising a memory controller coupled to the semiconductor structure and configured to control the semiconductor structure.
However, in the same field of endeavor, Kim discloses a semiconductor device, a method of making the same, and an electronic system including non- planar transistors such as vertical transistor, wherein the electronic system includes a memory controller 2140 coupled to the semiconductor structure and configured to control the semiconductor structure [0157].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the memory controller to control the memory and integrated circuit of KIM in order to control the memory function of KIM's integrated circuits.
Allowable Subject Matter
Claims 15, 20 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to Claim(s) 1, 12, and 13 have been considered but are persuasive. It is the examiner position that the silicide layer 150 has an inverted U-shape with downward protrusions, which partially cover sides of the vertically extended epitaxial layer 110a. Applicant claim covers partial and not a full side coverage, which is shown in at least FIG. 8. Furthermore, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Additionally, applicant's arguments against the references individually in not persuasive, since one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Therefore, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, SUNG et al. (US 2009/0236656) discloses a semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898