Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 11/14/2025, with respect to the rejections and objections of the claims 1-23 have been fully considered and are persuasive. Therefore, the rejections and objections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating Wu.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-8 and 12-15, and 21 are rejected under 35 U.S.C. 103 as being obvious over US 20240105613 A1 Xie et al hereafter “Xie” in further view of US 20240105609 A1 Wu et al here after “Wu”
Claim 1 Xie teaches a semiconductor device comprising: a 1st source/drain region ( 270 contacting 500 Fig. 20) and a 1st backside contact structure (500 fig 20), vertically below the 1st source/drain region, connected to the 1st source/drain region [illustrated fig. 20];
a 2ndsource/drain region (270 contacting 400 fig. 20) and a 1st placeholder isolation structure (400 fig. 20) vertically below the 2nd source/drain region;
a backside isolation structure (comprising 380, 410 and 506 fig. 20), on a back side of the semiconductor device [illustrated fig. 20], surrounding the 1st backside contact structure and the 1st placeholder isolation structure [met under broadest reasonable interpretation at least partially surrounding a left and right side of the 1st placeholder isolation structure and backside contact structure cross-sections X and Y2 of fig. 20]; and
Xie does not explicitly teach and/or illustrate a 3rd source/drain region and a 2nd placeholder isolation structure vertically below the 3rd source/drain region,
wherein the 2nd source/drain region is between the 1st source/drain region and the 3rd source/drain region, and
wherein a horizontal distance between the 1st backside contact structure and the 1st placeholder isolation structure is equal to a horizontal distance between the 1st placeholder isolation structure and the 2nd placeholder isolation structure.
Wu teaches a semiconductor device comprising:
a 1st source/drain region (620-1 fig. 10) and a 1st backside contact structure (925-1 fig. 10), vertically below the 1st source/drain region [see annotation below sufficiently illustrated fig. 10 and met under broadest reasonable interpretation wherein 1050 is a “back side metal (BSM) layer” paragraph 0064 and/or bottom side metal layer], connected to the 1st source/drain region [sufficiently illustrated fig. 10];
a 2nd source/drain region (620-2 fig. 10) and a 1st placeholder isolation structure (615-2 fig. 10) vertically below the 2nd source/drain region [see annotation below sufficiently illustrated fig. 10 and met under broadest reasonable interpretation wherein 1050 is a “back side metal (BSM) layer” paragraph 0064 and/or bottom side metal layer]; a backside isolation structure (115 fig. 10 met under broadest reasonable interpretation), on a back side of the semiconductor device [illustrated fig. 10], surrounding the 1st backside contact structure and the 1st placeholder isolation structure [illustrated fig. 10]; and
a 3rd source/drain region (620-3 fig. 10) and a 2nd placeholder isolation structure (615-3 fig. 10) vertically below the 3rd source/drain region [see annotation below sufficiently illustrated fig. 10 and met under broadest reasonable interpretation wherein 1050 is a “back side metal (BSM) layer” paragraph 0064 and/or bottom side metal layer],
wherein the 2nd source/drain region is between the 1st source/drain region and the 3rd source/drain region [sufficiently illustrated fig. 10], and
wherein a horizontal distance between the 1st backside contact structure and the 1st placeholder isolation structure is equal to a horizontal distance between the 1st placeholder isolation structure and the 2nd placeholder isolation structure [illustrated with sufficiently specificity fig. 10].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the 2nd source/drain region and the 1st placeholder structure of Xie in view of Wu and/or in the alternative combine the device of Xie with the device of Wu such that there is “a 3rd source/drain region and a 2nd placeholder isolation structure vertically below the 3rd source/drain region, wherein the 2nd source/drain region is between the 1st source/drain region and the 3rd source/drain region, and wherein a horizontal distance between the 1st backside contact structure and the 1st placeholder isolation structure is equal to a horizontal distance between the 1st placeholder isolation structure and the 2nd placeholder isolation structure” to enable a significant decrease in the foot print of on-chip capacitors and inductors without reducing their size, thereby maintaining the necessary performance requirements of the passive elements integrated with the back side power delivery network [Wu Paragraph 0025] and/or combining Equivalents known for the same purpose is prima facie type obviousness [see MPEP 2144.06 I.] in this case transistor device that function as logic and/or memory circuits and/or duplication of parts is prima facie type obviousness [See MPEP 2144.04 VI. B.] in this case the source/drain and placeholder structure.
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Wu Annotated fig. 10: highlighting a perspective in which the contacts and placeholder structures are vertically below
Claim 2 Xie in view of Wu teaches as shown above the semiconductor device of claim 1, wherein the 1st placeholder isolation structure and the backside isolation structure have different material compositions [Sufficiently disclosed Paragraph 0095 “The BDI 400 can include a material that is different than the material selected form BILD 380”].
Claim 3 Xie in view of Wu teaches as shown above the semiconductor device of claim 2, wherein the 1st placeholder isolation structure comprises silicon nitride [sufficiently disclosed Paragraph 0095 “SiN, SiBCN”], and the backside isolation structure comprises silicon oxide [Sufficiently disclosed Paragraph 0089 “SiOCN, SiOC”, “SiO2”].
Claim 4 Xie in view of Wu teaches the semiconductor device of claim 1, wherein an interface is formed between the backside isolation structure and the placeholder isolation structure [Paragraph 0089 “The BILD layer 380 can be, e.g., SiN, SiBCN, SiOCN, SiOC, SiC, etc. The BILD layer 380 can be SiO.sub.2, or low-k dielectrics.” And Paragraph 0095 “the BDI 400 can be, e.g., SiN, SiBCN, SiOCN, SiOC, SiC, etc. The BDI 400 can be SiO.sub.2, or low-k dielectrics.” the range of disclosed materials are identical for the backside isolation structure and the place holder isolation structure; thus, an embodiment is disclosed with sufficiently specificity that the features are materially the same illustrated fig. 20, See MPEP 2131.03].
Claim 5 Xie in view of Wu as shown above teaches the semiconductor device of claim 4, wherein the backside isolation structure and the placeholder isolation structure comprise the same material composition [Paragraph 0089 “The BILD layer 380 can be, e.g., SiN, SiBCN, SiOCN, SiOC, SiC, etc. The BILD layer 380 can be SiO.sub.2, or low-k dielectrics.” And Paragraph 0095 “the BDI 400 can be, e.g., SiN, SiBCN, SiOCN, SiOC, SiC, etc. The BDI 400 can be SiO.sub.2, or low-k dielectrics.” the range of disclosed materials are identical for the backside isolation structure and the place holder isolation structure; thus, an embodiment is disclosed with sufficiently specificity that the features are materially the same illustrated fig. 20, See MPEP 2131.03].
Claim 7 Modified Xie in view of Wu teaches as shown above the semiconductor device of claim 1, wherein the 1st placeholder isolation structure comprises a different material from the backside isolation structure [Sufficiently disclosed Paragraph 0095 “The BDI 400 can include a material that is different than the material selected form BILD 380”].
Claim 8 Modified Xie in view of Wu teaches as shown above the semiconductor device of claim 7, wherein each of the 1st and 2nd placeholder isolation structures comprises silicon nitride [sufficiently disclosed Paragraph 0095 “SiN, SiBCN”], and the backside isolation structure comprises silicon oxide [Sufficiently disclosed Paragraph 0089 “SiOCN, SiOC”, “SiO2”], and wherein a width of an uppermost portion of the 1st placeholder isolation structure is less than or equal to a width of a lowermost portion of the 2nd source/drain region [sufficiently illustrated fig. 20 the embodiment of “equal to”].
Claim 12 Xie a semiconductor device comprising:
a 1st device comprising [see annotation below] at least one 1st transistor [sufficiently illustrated fig. 20] forming a logic device or a memory device [met under broadest reasonable interpretation wherein “a transistor” qualifies as “a logic device” and comprises “a logic gate” wherein 230 and/or 320 is the gate electrode]; a 2nd device [see annotation below] comprising at least one 2nd transistor [sufficiently illustrated fig. 20] forming another logic device or another memory device [met under broadest reasonable interpretation wherein “a transistor” qualifies as “a logic device” and comprises “a logic gate” wherein 230 and/or 320 is the gate electrode]; and a backside isolation structure (comprising 380, 410 and 506 fig. 20) at a back side of each of the 1st and 2nd devices, wherein the 1st device adjacent to the 2nd device in a horizontal direction, wherein no shallow trench isolation (STI) structure is formed between the 1st device the 2nd device in the backside isolation structure [met under broadest reasonable interpretation, there is no STI formed between the 1st device from the 2nd device in the backside isolation structure within cross section X, which matches the disclosed cross section provide in fig. 2A of the instant application];
Wherein The first transistor comprises at least a 1st source/drain (right most 270 fig. 20 cross section X) and a 1st channel structure (right most 150 fig. 20 cross section x, illustrated not labeled, labeled fig. 8);
And the second transistor comprises at least a 2nd source/drain (left most 270 fig. 20 cross section X) and a 2nd channel structure (left most 150 fig. 20 cross section x, illustrated not labeled, labeled fig. 8) and are spaced apart from the 1st source/drain region in the horizontal direction [sufficiently illustrated fig. 20].
Xie does not explicitly illustrate wherein the 1st transistor comprises a 1st pair of source/drain regions that are electrically connected via a 1st channel structure, and wherein the 2nd transistor comprises a 2nd pair of source/drain regions that are electrically connected via a 2nd channel structure.
Wu teaches a similar device comprising a 1st transistor (left fig. 10) comprises a 1st pair of source/drain regions (620-1 and 620-2 fig. 10) that are electrically connected via a 1st channel structure (the corresponding element 315 therebetween, illustrated fig. 10 not labeled, labeled fig. 3A), and wherein the 2nd transistor (right fig. 10) comprises a 2nd pair of source/drain regions (620-3 and 620-4 fig. 10) that are electrically connected via a 2nd channel structure (the corresponding element 315 therebetween, illustrated fig. 10 not labeled, labeled fig. 3A) and are spaced apart from the 1st pair of source/drain regions in the horizontal direction [sufficiently illustrated fig. 10].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Xie in view of Wu such that “the 1st transistor comprises a 1st pair of source/drain regions that are electrically connected via a 1st channel structure, and wherein the 2nd transistor comprises a 2nd pair of source/drain regions that are electrically connected via a 2nd channel structure” to necessarily form complete transistors and/or duplication of parts is prima facie type obviousness [See MPEP 2144.04 VI. B.].
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Annotated fig. 20 cross section X: Highlighting the 1st and 2nd device
Claim 13 Xie in view of Wu teaches as shown above the semiconductor device of claim 12, wherein a placeholder isolation structure (400 fig. 20) is formed vertically below at least one of the pair of source/drain regions in the backside isolation structure [sufficiently illustrated fig. 20].
Claim 14 Xie in view of Wu teaches as shown above the semiconductor device of claim 13, wherein the placeholder isolation structure and the backside isolation structure comprise different materials [Sufficiently disclosed Paragraph 0095 “The BDI 400 can include a material that is different than the material selected form BILD 380”].
Claim 15 Xie in view of Wu teaches as shown above the semiconductor device of claim 14, wherein the placeholder isolation structure comprises silicon nitride [sufficiently disclosed Paragraph 0095 “SiN, SiBCN”], and the backside isolation structure comprises silicon oxide [Sufficiently disclosed Paragraph 0089 “SiOCN, SiOC”, “SiO2”].
Claim 16 Xie in view of Wu teaches as shown above the semiconductor device of claim 13, wherein an interface is formed between the backside isolation structure and the placeholder isolation structure [sufficiently illustrated fig. 16].
Claim 21 Xie in view of Wu teaches as shown above the semiconductor device of claim 1, wherein the 1st placeholder isolation structure and the 2nd placeholder isolation structure are horizontally spaced apart, with the backside isolation structure therebetween and without any shallow trench isolation (STI) structure therebetween [met under broadest reasonable interpretation no STI structure is illustrated within the cross section of the horizontal direction of Xie fig. 20].
Claim 22 Xie in view of Wu teaches as shown above the semiconductor device of claim 12, wherein the 1st device comprises a 1st CMOS device, and wherein the 2nd device comprises a 2nd CMOS device different from the 1st CMOS device [met under broadest reasonable interpretation CMOS and/or Complementary Metal Oxide Semiconductor, illustrated fig. 20 Xie].
Claim(s) 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Wu as applied to the claims above, and further in view of US 20240162229 A1 Xie et al hereafter “2nd Xie”
Claim 9 Xie teaches as shown above the semiconductor device of claim 1, the 1st and 2nd source/drain regions a source/drain region of a stacked field-effect transistor [illustrated fig. 20].
Xie does not teach wherein at least one of the 1st and 2nd source/drain regions is a lower source/drain region of a stacked field-effect transistor comprising the lower source/drain region and an upper source/drain region stacked above the lower source/drain region.
2nd Xie teaches a similar device wherein at least one of a 1st and 2nd source/drain regions (135A, 135B and/or 135 fig. 41 and/or 43) is a lower source/drain region [illustrated fig. 41] of a stacked field-effect transistor [illustrated fig. 41 and/or 43] comprising the lower source/drain region and an upper source/drain region (180A, 180B and/or 180 fig. 41 and/or 43) stacked above the lower source/drain region [illustrated fig. 41 and/or 43].
It would have been obvious to one of ordinary skill in the art to combine the device of Xie with the device of 2nd Xie such that “at least one of the 1st and 2nd source/drain regions is a lower source/drain region of a stacked field-effect transistor comprising the lower source/drain region and an upper source/drain region stacked above the lower source/drain region” to increase the device density [2nd Xie Paragraph 0002].
Claim 10 Xie in view of 2nd Xie teaches as shown above the semiconductor device of claim 9, wherein the lower source/drain region and the upper source/drain region form different field-effect transistors [met in view of 2nd Xie illustrated fig. 41 and/or 43].
Allowable Subject Matter
Claims 17-20, and 23 allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 17 recites the limitation “wherein no STI structure is formed in contact with the backside contact structure in the backside isolation structure”.
The prior art of record does not teach the limitation nor has the examiner found reason to modify prior art of record such that it teaches the limitation in view of the rest of the claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893