DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an application filed on 06/26/2023.
Currently, claims 1-20 are examined as below.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 08/29/2024 and 10/24/2025. The IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Integrated Capacitor Including Metal Plate Covering Alternating First and Second Metal Lines
(Clean Version) Integrated Capacitor Including Metal Plate Covering Alternating First and Second Metal Lines
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 is indefinite, because the abbreviation “GPS” has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “GPS.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2010/0127347 A1 to Quinn.
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Regarding independent claim 1, Quinn in Figs. 2A-2B teaches an integrated capacitor structure 220 (Figs. 2A-2B, ¶ 30, integrated capacitor 220), comprising:
alternating first metal lines T1-T4 (Figs. 2A-2B, ¶ 28, ¶ 30, conductive strips T1-T4 formed from metal layer M3) and second metal lines B1-B3 (Figs. 2A-2B, ¶ 28, ¶ 30, conductive trips B1-B3 formed from metal layer M3) in a dielectric layer ILD/IMD (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD in the metal layer M3) of a metallization layer M3 (Fig. 2B, ¶ 30, metal layer M3) in a stack of metallization layers 222 (Fig. 2B, ¶ 30, backend stack 222 including metal layers M1-M5), the first metal lines T1-T4 coupled together (Fig. 2B, ¶ 28, conductive strips T1-T4 are coupled together through plate layer T), and the second metal lines B1-B3 coupled together (Fig. 2B, ¶ 27, conductive strips B1-B3 are coupled together through plate layer B);
a metal plate B (Figs. 2A-2B, ¶ 25, ¶ 30, bottom plate layer B formed from metal layer M4) over the alternating first metal lines T1-T4 and second metal lines B1-B3; and
a dielectric liner layer ILD/IMD (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD) between the alternating first metal lines T1-T4 and second metal lines B1-B3 and the metal plate B (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD, which is interposed between plate B and the metal strips T1-T4 and B1-B3, is treated as a liner layer).
Regarding claim 5, Quinn in Fig. 2B further teaches the alternating first metal lines T1-T4 and second metal lines B1-B3 and the dielectric layer ILD/IMD form a finger capacitor structure 220 (¶ 28, ¶ 30, integrated capacitor 220 including conductive strips T1-T4, B1-B3; ¶ 4, conductive strips are conductive fingers).
Regarding independent claim 6, Quinn in Figs. 2A-2B teaches an integrated capacitor structure 220 (Figs. 2A-2B, ¶ 30, integrated capacitor 220), comprising:
alternating first metal lines T1-T4 (Figs. 2A-2B, ¶ 28, ¶ 30, conductive strips T1-T4 formed from metal layer M3) and second metal lines B1-B3 (Figs. 2A-2B, ¶ 28, ¶ 30, conductive trips B1-B3 formed from metal layer M3) in a dielectric layer ILD/IMD (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD in the metal layer M3) of a metallization layer M3 (Fig. 2B, ¶ 30, metal layer M3) in a stack of metallization layers 222 (Fig. 2B, ¶ 30, backend stack 222 including metal layers M1-M5), the first metal lines T1-T4 coupled together (Fig. 2B, ¶ 28, conductive strips T1-T4 are coupled together through plate layer T), and the second metal lines B1-B3 coupled together (Fig. 2B, ¶ 27, conductive strips B1-B3 are coupled together through plate layer B);
a metal plate T (Figs. 2A-2B, ¶ 28, top late layer T formed from metal layer M2) beneath the alternating first metal lines T1-T4 and second metal lines B1-B3; and
a dielectric liner layer ILD/IMD (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD) between the alternating first metal lines T1-T4 and second metal lines B1-B3 and the metal plate T (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD, which is interposed between plate T and the metal strips T1-T4 and B1-B3, is treated as a liner layer).
Regarding claim 10, Quinn in Fig. 2B further teaches the alternating first metal lines T1-T4 and second metal lines B1-B3 and the dielectric layer ILD/IMD form a finger capacitor structure 220 (¶ 28, ¶ 30, integrated capacitor 220 including conductive strips T1-T4, B1-B3; ¶ 4, conductive strips are conductive fingers).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Quinn.
Regarding claim 2, Quinn does not explicitly disclose the dielectric liner ILD/IMD has a dielectric constant greater than a dielectric constant of the dielectric layer ILD/IMD.
However, Quinn teaches a general condition in which the dielectric liner ILD/IMD has a dielectric constant and the dielectric layer ILD/IMD has a dielectric constant (dielectric materials have dielectric constants).
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Quinn teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the dielectric liner having a dielectric constant greater than a dielectric constant of the dielectric layer produce unexpected results that are different in kind and not different in degree, said general conditions taught by Quinn renders claim 2 obvious.
Regarding claim 7, Quinn does not explicitly disclose the dielectric liner ILD/IMD has a dielectric constant greater than a dielectric constant of the dielectric layer ILD/IMD.
However, Quinn teaches a general condition in which the dielectric liner ILD/IMD has a dielectric constant and the dielectric layer ILD/IMD has a dielectric constant (dielectric materials have dielectric constants).
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Quinn teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the dielectric liner having a dielectric constant greater than a dielectric constant of the dielectric layer produce unexpected results that are different in kind and not different in degree, said general conditions taught by Quinn renders claim 7 obvious.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Quinn in view of US 2020/0279908 A1 to Siprak et al. (“Siprak”).
Regarding claim 3, Quinn does not explicitly disclose the first metal lines T1-T4 are coupled to a first polarity, and the second metal lines B1-B3 are coupled to a second polarity opposite the first polarity.
Siprak recognizes a need for further reducing the inductance of two conductive lines and achieving a high capacitance (¶ 29-¶ 30). Siprak satisfies the need by providing the first metal lines 422 (Figs. 4A-4B, ¶ 50-¶ 51, ¶ 22, first finger elements 422 including metal) coupled to a first polarity (¶ 51, positive), and the second metal lines 424 (Figs. 4A-4B, ¶ 50-¶ 51, ¶ 22, second finger elements 424 including metal) coupled to a second polarity (¶ 51, negative) opposite the first polarity.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the first and second metal lines taught by Quinn with the polarities taught by Siprak, so as to further reduce the inductance of two conductive lines and achieve a high capacitance (Siprak: ¶ 29-¶ 30).
Regarding claim 8, Quinn does not explicitly disclose the first metal lines T1-T4 are coupled to a first polarity, and the second metal lines B1-B3 are coupled to a second polarity opposite the first polarity.
Siprak recognizes a need for further reducing the inductance of two conductive lines and achieving a high capacitance (¶ 29-¶ 30). Siprak satisfies the need by providing the first metal lines 422 (Figs. 4A-4B, ¶ 50-¶ 51, ¶ 22, first finger elements 422 including metal) are coupled to a first polarity (¶ 51, positive), and the second metal lines 424 (Figs. 4A-4B, ¶ 50-¶ 51, ¶ 22, second finger elements 424 including metal) are coupled to a second polarity (¶ 51, negative) opposite the first polarity.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the first and second metal lines taught by Quinn with the polarities taught by Siprak, so as to further reduce the inductance of two conductive lines and achieve a high capacitance (Siprak: ¶ 29-¶ 30).
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Quinn in view of US 2020/0219861 A1 to Kamgaing et al. (“Kamgaing”).
Regarding independent claim 11, Quinn in Figs. 2A-2B teaches a component 220 (Figs. 2A-2B, ¶ 30, integrated capacitor 220) including an integrated capacitor structure 220 (¶ 30), comprising:
alternating first metal lines T1-T4 (Figs. 2A-2B, ¶ 28, ¶ 30, conductive strips T1-T4 formed from metal layer M3) and second metal lines B1-B3 (Figs. 2A-2B, ¶ 28, ¶ 30, conductive trips B1-B3 formed from metal layer M3) in a dielectric layer ILD/IMD (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD in the metal layer M3) of a metallization layer M3 (Fig. 2B, ¶ 30, metal layer M3) in a stack of metallization layers 222 (Fig. 2B, ¶ 30, backend stack 222 including metal layers M1-M5), the first metal lines T1-T4 coupled together (Fig. 2B, ¶ 28, conductive strips T1-T4 are coupled together through plate layer T), and the second metal lines B1-B3 coupled together (Fig. 2B, ¶ 27, conductive strips B1-B3 are coupled together through plate layer B);
a metal plate B, T (Figs. 2A-2B, ¶ 25, ¶ 30, bottom plate layer B formed from metal layer M4; Figs. 2A-2B, ¶ 28, top late layer T formed from metal layer M2) over or beneath the alternating first metal lines T1-T4 and second metal lines B1-B3; and
a dielectric liner layer ILD/IMD (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD) between the alternating first metal lines T1-T4 and second metal lines B1-B3 and the metal plate B, T (Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD, which is interposed between plate B and the metal strips T1-T4 and B1-B3, is treated as a liner layer; Fig. 2B, ¶ 24, ¶ 30, ¶ 33-¶ 34, dielectric layer ILD/IMD, which is interposed between plate T and the metal strips T1-T4 and B1-B3, is treated as a liner layer).
However, Quinn does not explicitly disclose a computing device, comprising: a board; and a component coupled to the board.
Kamgaing recognizes a need for providing a computer system that utilizes an integrated system including capacitor and resonator (¶ 57, ¶ 14, ¶ 16, ¶ 18). Kamgaing satisfies the need by providing a computing device 700 (Fig. 7, ¶ 57, computing device 700), comprising: a board 702 (¶ 57, motherboard 702); and a component (¶ 57, ¶ 14, ¶ 16, ¶ 18, integrated system including capacitor and resonator; ¶ 57-¶ 60, components) coupled to the board 702.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the component taught by Quinn with the computer system taught by Kamgaing, so as to provide a computer system that utilizes an integrated system including capacitor and resonator (Kamgaing: ¶ 57, ¶ 14, ¶ 16, ¶ 18).
Regarding claim 12, Quinn in Fig. 2B further teaches the metal plate B is over the alternating first metal lines T1-T4 and second metal lines B1-B3.
Regarding claim 13, Quinn in Fig. 2B further teaches the metal plate T is beneath the alternating first metal lines T1-T4 and second metal lines B1-B3.
Regarding claim 14, the combination of Quinn and Kamgaing further teaches a memory (Kamgaing: ¶ 58) coupled to the board 702.
Regarding claim 15, the combination of Quinn and Kamgaing further teaches a communication chip 706 (Kamgaing: Fig. 7, ¶ 59, communication chip 706) coupled to the board 702.
Regarding claim 16, the combination of Quinn and Kamgaing further teaches a camera (Kamgaing: ¶ 58) coupled to the board 702.
Regarding claim 17, the combination of Quinn and Kamgaing further teaches a battery (Kamgaing: ¶ 58) coupled to the board 702.
Regarding claim 18, the combination of Quinn and Kamgaing further teaches a GPS (Kamgaing: ¶ 58) coupled to the board 702.
Regarding claim 19, the combination of Quinn and Kamgaing further teaches a display (Kamgaing: ¶ 58) coupled to the board 702.
Regarding claim 20, the combination of Quinn and Kamgaing further teaches the component is a packaged integrated circuit die (Kamgaing: ¶ 60-¶ 62).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 4 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 4, wherein the metal plate is electrically floating.
Claim 9 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 9, wherein the metal plate is electrically floating.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2018/0041193 A1 to Chen et al. relates to an acoustic filtering circuitry including a piezoelectric layer, a dielectric layer, a plurality of acoustic resonators, and a capacitor. The dielectric layer is over a surface of the piezoelectric layer. The plurality of acoustic resonators each includes a transducer on the surface of the piezoelectric layer such that the transducer is between the piezoelectric layer and the dielectric layer. The capacitor includes a first plate on the surface of the piezoelectric layer such that the first plate is between the piezoelectric layer and the dielectric layer and a second plate over the first plate such that the second plate and the first plate are separated by at least a portion of the dielectric layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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