Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (Pub. No.: US 2010/0123213 A1).
Regarding Claim 1, Chen et al. discloses an integrated capacitor structure, comprising: alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together (Par. 0043-0047; Figs. 1, 5-7 – first metal lines 62 (of layer M4); second metal lines 64 (of layer M4); first metal lines 62 are coupled together by first terminal 67; second metal lines 64 are coupled together by second terminal 65); and a first metal plate over the alternating first metal lines and second metal lines, the first metal plate coupled to the first metal lines by first vias (Par. 0043-0047; Figs. 1, 5-7 – one
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metal plate 68 (of layer M3) is shown; but this prior art teaches “In capacitors 60 that are formed across more than three metal interconnect layers metal plates such as plate 68 of FIG. 5 may be formed in alternate metal interconnect layers each interposed between a respective pair of metal-line layers. Metal plate 68 is shown as being of polarity B, but may, if desired, be of polarity A. Moreover, plates may be of different polarities in different metal interconnect layers” (Par. 0044); this implies that there could be another metal plate 68 (labeled here as the first metal plate) in metal layer M5 and it could have the same polarity (A) as the polarity of the first metal line (A); first metal plate 68 is coupled to the first metal lines 62 by vias between layers M4 and M5).
Regarding Claim 2, Chen et al., as applied to claim 1, discloses the integrated capacitor structure, further comprising: a second metal plate beneath the alternating first metal lines and second metal lines, the second metal plate coupled to the second metal lines by second vias (Par. 0043-0047; Figs. 1, 5-7 – metal plate 68 shown in metal layer M3 could be considered as the second metal plate; it has the same polarity (B) as the second metal line (B) and connected together by second vias between metal layers M4 and M3).
Regarding Claim 3, Chen et al., as applied to claim 2, discloses the integrated capacitor structure, wherein the first metal lines and the first metal plate are coupled to a first polarity, and the second metal lines and the second metal plate are coupled to a second polarity opposite the first polarity (Par. 0043-0047; Figs. 1, 5-7 – please see the rejection of claim 2).
Regarding Claim 4, Chen et al., as applied to claim 1, discloses the integrated capacitor structure, wherein the dielectric layer is a low-k dielectric layer (Par. 0031).
Regarding Claim 5, Chen et al., as applied to claim 1, discloses the integrated capacitor structure, wherein the alternating first metal lines and second metal lines and the dielectric layer form a finger capacitor structure (Fig. 7).
Regarding Claim 6, Chen et al. discloses an integrated capacitor structure, comprising: alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together (Par. 0043-0047; Figs. 1, 5-7 – first metal lines 64 (of layer M4); second metal lines 62 (of layer M4); first metal lines 64 are coupled together by first terminal 65; second metal lines 62 are coupled together by second terminal 67); and
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a first metal plate beneath the alternating first metal lines and second metal lines, the first metal plate coupled to the first metal lines by first vias (Par. 0043-0047; Figs. 1, 5-7 – first metal plate 68 shown in metal layer M3; it has the same polarity (B) as the first metal line (B) and connected together by first vias between metal layers M4 and M3).
Regarding Claim 7, Chen et al., as applied to claim 6, discloses the integrated capacitor structure, further comprising alternating third metal lines and fourth metal lines above the alternating first metal lines and second metal lines, the third metal lines coupled to the first metal lines, and the fourth metal lines coupled to the second metal lines (Par. 0043-0047; Figs. 1, 5-7 – this prior art shows first metal lines 64 and second metal lines 62 in metal layer M4; this prior art further teaches “In capacitors 60 that are formed across more than three metal interconnect layers metal plates such as plate 68 of FIG. 5 may be formed in alternate metal interconnect layers each interposed between a respective pair of metal-line layers… For line-plate-line capacitors 60 that are formed across more metal interconnect layers than are shown in FIG. 6, parallel metal lines 62 and 64 may alternate in orientation for each metal interconnect layer that contains parallel metal lines (if desired) (Par. 0044-0045); this implies that there could be alternating third metal lines and fourth metal lines above the alternating first metal lines and second metal lines with the third metal lines coupled to the first metal lines, and the fourth metal lines coupled to the second metal lines).
Regarding Claim 8, Chen et al., as applied to claim 6, discloses the integrated capacitor structure, wherein the first metal lines and the first metal plate are coupled to a first polarity, and the second metal lines are coupled to a second polarity opposite the first polarity (Par. 0043-0047; Figs. 1, 5-7).
Regarding Claim 9, Chen et al., as applied to claim 6, discloses the integrated capacitor structure, wherein the dielectric layer is a low-k dielectric layer (Par. 0031).
Regarding Claim 10, Chen et al., as applied to claim 6, discloses the integrated capacitor structure, wherein the alternating first metal lines and second metal lines and the dielectric layer form a finger capacitor structure (Fig. 7).
Regarding Claim 11, Chen et al. discloses
a computing device, comprising: a board (Par. 0001-0010; 0068-0072); and a component coupled to the board, the component including an integrated capacitor structure (Par. 0001-0010; 0068-0072), comprising:
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alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together (Par. 0043-0047; Figs. 1, 5-7 – first metal lines 62 (of layer M4); second metal lines 64 (of layer M4); first metal lines 62 are coupled together by first terminal 67; second metal lines 64 are coupled together by second terminal 65); and a metal plate over or beneath the alternating first metal lines and second metal lines, the metal plate coupled to the first metal lines or the second metal lines by vias (Par. 0043-0047; Figs. 1, 5-7 – first metal plate 68 shown in metal layer M3; it has the same polarity (B) as the second metal line 64 (B) and connected together by vias between metal layers M4 and M3).
Regarding Claim 12, Chen et al., as applied to claim 11, discloses the computing device, wherein the metal plate is over the alternating first metal lines and second metal lines (Par. 0043-0047; Figs. 1, 5-7 – one metal plate 68 (of layer M3) is shown; but this prior art teaches “In capacitors 60 that are formed across more than three metal interconnect layers metal plates such as plate 68 of FIG. 5 may be formed in alternate metal interconnect layers each interposed between a respective pair of metal-line layers. Metal plate 68 is shown as being of polarity B, but may, if desired, be of polarity A. Moreover, plates may be of different polarities in different metal interconnect layers” (Par. 0044); this implies that there could be another metal plate 68 in metal layer M5).
Regarding Claim 13, Chen et al., as applied to claim 11, discloses the computing device, wherein the metal plate is beneath the alternating first metal lines and second metal lines (Par. 0043-0047; Figs. 1, 5-7 – metal plate 68 shown in metal layer M3 beneath the alternating first metal lines 62 and second metal lines 64 formed in metal layer M4).
Regarding Claim 14, Chen et al., as applied to claim 11, discloses the computing device, further comprising: a memory coupled to the board (Par. 0001-0010; 0068-0072).
Regarding Claim 15, Chen et al., as applied to claim 11, discloses the computing device, further comprising: a communication chip coupled to the board (Par. 0001-0010; 0068-0072).
Regarding Claim 20, Chen et al., as applied to claim 11, discloses the computing device, wherein the component is a packaged integrated circuit die (Par. 0001-0010; 0068-0072 – not stated explicitly but implied).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16-19 are rejected under 35 U.S.C. 103 as obvious over Chen et al. (Pub. No.: US 2010/0123213 A1), as applied to claim 11.
Regarding Claim 16, Chen et al., as applied to claim 11, does not explicitly disclose the computing device, further comprising: a camera coupled to the board. The Examiner takes OFFICIAL NOTICE that the computing device, further comprising: a camera coupled to the board is widely known in the art. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the computing device, further comprising: a camera coupled to the board of Chen et al. in order to fabricate a state-of-the-art device.
Regarding Claim 17, Chen et al., as applied to claim 11, does not explicitly disclose the computing device, further comprising: a battery coupled to the board. The Examiner takes OFFICIAL NOTICE that the computing device, further comprising: a battery coupled to the board is widely known in the art. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the computing device, further comprising: a battery coupled to the board of Chen et al. in order to fabricate a state-of-the-art device.
Regarding Claim 18, Chen et al., as applied to claim 11, does not explicitly disclose the computing device, further comprising: a GPS coupled to the board. The Examiner takes OFFICIAL NOTICE that the computing device, further comprising: a GPS coupled to the board is widely known in the art. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the computing device, further comprising: a GPS coupled to the board of Chen et al. in order to fabricate a state-of-the-art device.
Regarding Claim 19, Chen et al., as applied to claim 11, does not explicitly disclose the computing device, further comprising: a display coupled to the board. The Examiner takes OFFICIAL NOTICE that the computing device, further comprising: a display coupled to the board is widely known in the art. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the computing device, further comprising: a display coupled to the board of Chen et al. in order to fabricate a state-of-the-art device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Anthony (Pub. No.: US 2009/0109597 A1) – This prior art teaches a integrated capacitor structure, comprising: alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together (Par. 0035-0038; Figs. 2A-2B – first metal lines 27; second metal lines 28; first metal lines 27 are coupled together to first terminal 21; second metal lines 28 are coupled together to second terminal 22); and a first metal plate over the alternating first metal lines and second metal lines, the first metal plate coupled to the first metal lines by first vias (Par. 0035-0038; Figs. 2A-2B – first metal plate 23; first metal plate 23 is coupled to the first metal lines 27 by first vias 29).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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08/07/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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