DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/214,262 filed June 26, 2023. Claims 1-20 are currently pending and have been considered below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 4-7, 9-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-2, 4-7 & 9-20 of copending Application No. 18/126,857 in view of Yang (Pre-Grant Publication 2022/0262958). Claim 1 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 1 of co-pending application 18/126,857, such as an integrated circuit structure, comprising: a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires; a gate stack over the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires; a first epitaxial source or drain structure at an end of the first plurality of horizontally stacked nanowires, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact; and a second epitaxial source or drain structure at an end of the second plurality of horizontally stacked nanowires, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact, and the second hardmask material having a composition different than a composition of the first hardmask material. Co-pending 18/126,857 application does not claim the second conductive source or drain contact having a same composition as the first conductive source or drain contact. However Yang discloses a semiconductor device comprising:
A transistor device in a NFET region (202N) and a PFET region (202P) wherein first and second epitaxial source/drain regions (Fig. 18b, 230N/ 230P) are form adjacent to channel regions of the transistors and a source/drain contacts (250) is formed on the first and second epitaxial source/drain regions and can be the same material/composition (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Claim 2 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 2 of co-pending application 18/126,857, such as the second hardmask material has a bottommost surface at a same level as a bottommost surface of the first hardmask material.
Claim 4 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 4 of co-pending application 18/126,857, such as one of the first hardmask material or the second hardmask material comprises silicon and carbon, and the other one of the first hardmask material or the second hardmask material comprises silicon and nitrogen.
Claim 5 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 5 of co-pending application 18/126,857, such as at least one of the first or second conductive source or drain contact comprises tungsten. Co-pending
Claim 2 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 2 of co-pending application 18/126,857, such as Co-pending 18/126,857 application does not claim the first and second conductive source or drain comprises tungsten. However Yang further discloses:
The source/drain conductive contacts (250) coupled to the source/drain regions can comprise tungsten/W (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Claim 6 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 6 of co-pending application 18/126,857, such as an integrated circuit structure, comprising: a first fin laterally spaced apart from a second fin; a gate stack over the first fin and the second fin; a first epitaxial source or drain structure at an end of the first fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact; and a second epitaxial source or drain structure at an end of the second fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact, and the second hardmask material having a composition different than a composition of the first hardmask material. Co-pending 18/126,857 application does not claim the second conductive source or drain contact having a same composition as the first conductive source or drain contact. However Yang discloses a semiconductor device comprising:
A transistor device in a NFET region (202N) and a PFET region (202P) wherein first and second epitaxial source/drain regions (Fig. 18b, 230N/ 230P) are form adjacent to channel regions of the transistors and a source/drain contacts (250) is formed on the first and second epitaxial source/drain regions and can be the same material/composition (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Claim 7 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 7 of co-pending application 18/126,857, such as the second hardmask material has a bottommost surface at a same level as a bottommost surface of the first hardmask material.
Claim 9 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 9 of co-pending application 18/126,857, such as one of the first hardmask material or the second hardmask material comprises silicon and carbon, and the other one of the first hardmask material or the second hardmask material comprises silicon and nitrogen.
Claim 10 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 10 of co-pending application 18/126,857, such as at least one of the first or second conductive source or drain contact comprises tungsten. Co-pending
Claim 10 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 2 of co-pending application 18/126,857, such as Co-pending 18/126,857 application does not claim the first and second conductive source or drain comprises tungsten. However Yang further discloses:
The source/drain conductive contacts (250) coupled to the source/drain regions can comprise tungsten/W (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Claim 11 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 11 of co-pending application 18/126,857, such as A computing device, comprising:a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first plurality of horizontally stacked nanowires or a first fin laterally spaced apart from a second plurality of horizontally stacked nanowires or a second fin; a gate stack over the first plurality of horizontally stacked nanowires or the first fin and the second plurality of horizontally stacked nanowires or the second fin; a first epitaxial source or drain structure at an end of the first plurality of horizontally stacked nanowires or the first fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact; and a second epitaxial source or drain structure at an end of the second plurality of horizontally stacked nanowires or the second fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact and the second hardmask material having a composition different than a composition of the first hardmask material. Co-pending 18/126,857 application does not claim the second conductive source or drain contact having a same composition as the first conductive source or drain contact. However Yang discloses a semiconductor device comprising:
A transistor device in a NFET region (202N) and a PFET region (202P) wherein first and second epitaxial source/drain regions (Fig. 18b, 230N/ 230P) are form adjacent to channel regions of the transistors and a source/drain contacts (250) is formed on the first and second epitaxial source/drain regions and can be the same material/composition (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Claim 12 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 12 of co-pending application 18/126,857, such as the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires.
Claim 13 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 13 of co-pending application 18/126,857, such as the first fin and the second fin.
Claim 14 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 14 of co-pending application 18/126,857, such as a memory coupled to the board.
Claim 15 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 15 of co-pending application 18/126,857, such as a communication chip coupled to the board.
Claim 16 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 16 of co-pending application 18/126,857, such as a battery coupled to the board.
Claim 17 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 17 of co-pending application 18/126,857, such as a camera coupled to the board.
Claim 18 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 18 of co-pending application 18/126,857, such as a display coupled to the board.
Claim 19 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 19 of co-pending application 18/126,857, such as the component is a packaged integrated circuit die.
Claim 20 of the present application is rejected under nonstatutory double patenting because it claims substantially the same subject matter of claim 20 of co-pending application 18/126,857, such as the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Claim 3 & 8 are also rejected under non-statutory double patenting based on their dependency from claims 1 & 6 respectively.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mills (Pre-Grant Publication 2024/0332377) in view of Yang (Pre-Grant Publication 2022/0262958).
Regarding claim 1, Mills discloses an integrated circuit comprising:
a first plurality of horizontally stacked nanowires (Fig. 1-9, 202) laterally spaced apart from a second plurality of horizontally stacked nanowires (202);
a gate stack (206) over the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires;
a first epitaxial source or drain structure (222) at an end of the first plurality of horizontally stacked nanowires, with a first conductive source or drain contact (214a) vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material (226) beneath and in contact with the first conductive source or drain contact; and
a second epitaxial source or drain structure (222) at an end of the second plurality of horizontally stacked nanowires, with a second conductive source or drain contact (218a) vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material (228) beneath and in contact with the second conductive source or drain contactand the second hardmask material having a composition different than a composition of the first hardmask material (Claim 1).
Mills does not disclose the second conductive source or drain contact having a same composition as the first conductive source or drain contact. However Yang discloses a semiconductor device comprising:
A transistor device in a NFET region (202N) and a PFET region (202P) wherein first and second epitaxial source/drain regions (Fig. 18b, 230N/ 230P) are form adjacent to channel regions of the transistors and a source/drain contacts (250) is formed on the first and second epitaxial source/drain regions and can be the same material/composition (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Regarding claim 2, Mills further discloses:
the second hardmask material has a bottommost surface at a same level as a bottommost surface of the first hardmask material (Claim 2)
Regarding claim 4, Mills further discloses:
one of the first hardmask material or the second hardmask material comprises silicon and carbon, and the other one of the first hardmask material or the second hardmask material comprises silicon and nitrogen (Claim 4).
Regarding claim 5, Mills further discloses:
at least one of the first or second conductive source or drain contact comprises tungsten (Claim 5).
Mills does not disclose the first and second conductive source or drain comprises tungsten. However Yang further discloses:
The source/drain conductive contacts (250) coupled to the source/drain regions can comprise tungsten/W (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Regarding claim 6, Mills disclose an integrated circuit comprising:
a first fin (Fig. 1-9, 202; Paragraph [0043]) laterally spaced apart from a second fin (202);
a gate stack (206) over the first fin and the second fin;
a first epitaxial source or drain structure (222) at an end of the first fin, with a first conductive source or drain contact (214a) vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material (226) beneath and in contact with the first conductive source or drain contact; and
a second epitaxial source or drain structure (222) at an end of the second fin, with a second conductive source or drain contact (218a) vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material (228) beneath and in contact with the second conductive source or drain contact, and the second hardmask material having a composition different than a composition of the first hardmask material (Claim 6).
Mills does not disclose the second conductive source or drain contact having a same composition as the first conductive source or drain contact. However Yang discloses a semiconductor device comprising:
A transistor device in a NFET region (202N) and a PFET region (202P) wherein first and second epitaxial source/drain regions (Fig. 18b, 230N/ 230P) are form adjacent to channel regions of the transistors and a source/drain contacts (250) is formed on the first and second epitaxial source/drain regions and can be the same material/composition (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Regarding claim 7, Mills further discloses:
the second hardmask material has a bottommost surface at a same level as a bottommost surface of the first hardmask material (Claim 7).
Regarding claim 9, Mills further discloses:
one of the first hardmask material or the second hardmask material comprises silicon and carbon, and the other one of the first hardmask material or the second hardmask material comprises silicon and nitrogen (Claim 9).
Regarding claim 10, Mills further discloses:
at least one of the first or second conductive source or drain contact comprises tungsten (Claim 5).
Mills does not disclose the first and second conductive source or drain comprises tungsten. However Yang further discloses:
The source/drain conductive contacts (250) coupled to the source/drain regions can comprise tungsten/W (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Regarding claim 11, Mills discloses a computing device comprising:
a board (Fig. 13, 1302); and a component (Paragraph [0114]) coupled to the board, the component including an integrated circuit structure, comprising:
a first plurality of horizontally stacked nanowires (Fig. 1-9, 202) laterally spaced apart from a second plurality of horizontally stacked nanowires (202);
a gate stack (206) over the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires;
a first epitaxial source or drain structure (222) at an end of the first plurality of horizontally stacked nanowires, with a first conductive source or drain contact (214a) vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material (226) beneath and in contact with the first conductive source or drain contact; and
a second epitaxial source or drain structure (222) at an end of the second plurality of horizontally stacked nanowires, with a second conductive source or drain contact (218a) vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material (228) beneath and in contact with the second conductive source or drain contactand the second hardmask material having a composition different than a composition of the first hardmask material (Claim 1).
Mills does not disclose the second conductive source or drain contact having a same composition as the first conductive source or drain contact. However Yang discloses a semiconductor device comprising:
A transistor device in a NFET region (202N) and a PFET region (202P) wherein first and second epitaxial source/drain regions (Fig. 18b, 230N/ 230P) are form adjacent to channel regions of the transistors and a source/drain contacts (250) is formed on the first and second epitaxial source/drain regions and can be the same material/composition (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second source/drain contacts to be the same material/composition because it will allow the source/drain contacts to be formed simultaneously thereby minimizing manufacturing steps and time.
Regarding claim 12, Mills further discloses:
the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires (Claim 12).
Regarding claim 13, Mills further discloses:
the first fin and the second fin (Claim 13)
Regarding claim 14, Mills further discloses:
a memory coupled to the board (Claim 14)
Regarding claim 15, Mills further discloses:
a communication chip coupled to the board (Claim 15)
Regarding claim 16, Mills further discloses:
a battery coupled to the board (Claim 16).
Regarding claim 17, Mills further discloses:
a camera coupled to the board (Claim 17).
Regarding claim 18, Mills further discloses:
a display coupled to the board (Claim 18)
Regarding claim 19, Mills further discloses:
the component is a packaged integrated circuit die (Claim 19).
Regarding claim 20, Mills further discloses:
the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Claim 20).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Noh (Pre-Grant Publication 2026/0026030) disclose a semiconductor device comprising a first and second source/drain wherein a spacer layer is formed on a backside of the source/drain and a contact plug recessed within a surface of the source/drain.
Xie (Pre-Grant Publication 2024/0162118) disclose a backside skip level through via for backside signal line connection.
Xie (Pre-Grant Publication 2023/0369217) disclose a buried via to backside power rail for stacked field effect transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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