DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The two information disclosure statements (IDS) submitted on 26 Jun 2023 and 15 Sep 2025 have been considered by the examiner.
Response to Amendment
Examiner acknowledges that Applicant has amended claims 5, 10, 17, and 25 in the reply filed on 6 Jan 2026 in response to the Requirement for Restriction/Election dated 12 Dec 2025.
The amendments to claims 5 and 17 added punctuation (a comma and a colon, respectively). The amendment to claim 10 added “plurality of” in “the plurality of vertical connection conductors”. The amendment to claim 25 corrects a typographical error so that the claim now begins, “A semiconductor package comprising”.
Claims 14 and 21–24 were cancelled in a previous amendment to the claims filed on the same day of the filing date of the application, 26 Jun 2023. Therefore, the pending claims are 1–13, 15–20, and 25.
Election/Restrictions
Applicant’s election without traverse of Species D (Fig. 6) in the reply filed on 6 Jan 2026 is acknowledged. In the reply, Applicant stated: “Claims 1–6, 9–13, 15–20, and 25 are understood to correspond to this election.” Accordingly, claims 7–8 stand as withdrawn from consideration as being drawn to a nonelected species.
Additionally, the examiner asserts that claim 9 is drawn to the nonelected Species G (Fig. 9). Specifically, claim 9 includes the following features: “the heat dissipation pad structure comprises: a plurality of heat dissipation pad layers vertically spaced apart from each other; and a plurality of heat dissipation vias vertically extending in spaces between two adjacent heat dissipation pad layers of the plurality of heat dissipation pad layers”. The embodiment of the semiconductor package 16 of Fig. 9 is the only embodiment in which the heat dissipation pad structure 171 of the other embodiments has been replaced with a heat dissipation pad structure 172 comprising a plurality of heat dissipation pad layers 1721 and heat dissipation via patterns 1723.
Additionally, the examiner asserts that claim 11 is drawn to the nonelected Species I (Fig. 11). Specifically, claim 11 includes the following feature: “the first conductive via has a narrowing horizontal width toward the connection pad of the first semiconductor device”. The embodiment of the semiconductor package 18 of Fig. 11 is the only embodiment wherein the first conductive via 1133 has a narrowing horizontal width toward the connection pad 1213 of the first semiconductor device 120.
Additionally, the examiner asserts that claim 12 is drawn to the nonelected Species K (Fig. 13). Specifically, claim 12 includes the following feature: “a stiffener disposed on the second redistribution structure”. The embodiment of the semiconductor package 20 of Fig. 13 is the only embodiment having a stiffener 193 disposed on the second redistribution structure 160.
Additionally, the examiner asserts that claim 16 is drawn to the nonelected Species B or C (Figs. 4 or 5). Specifically, claim 16 includes the following feature: “a plurality of conductive pads disposed on an upper surface of the molding layer and connected to the plurality of vertical connection conductors; one or more dummy pads disposed on the upper surface of the molding layer and not connected to the plurality of vertical connection conductors”. The embodiments of the semiconductor package 11 of Fig. 4 or the semiconductor package 12 of Fig. 5 are the only embodiments having a plurality of conductive pads 1911 disposed on an upper surface 1511 of the molding layer 151 and connected to the plurality of vertical connection conductors 155; one or more dummy pads 1913 disposed on the upper surface 1511 of the molding layer 151 and not connected to the plurality of vertical connection conductors 155.
Additionally, the examiner asserts that claim 19 is drawn to the nonelected Species G (Fig. 9). Specifically, claim 19 includes the following features: “a plurality of heat dissipation pad layers disposed within the second redistribution insulating layer and vertically spaced apart from each other; and a plurality of heat dissipation vias disposed in the second redistribution insulating layer and extending vertically in spaces between two adjacent heat dissipation pad layers of the plurality of heat dissipation pad layers”. The embodiment of the semiconductor package 16 of Fig. 9 is the only embodiment having a plurality of heat dissipation pad layers 1721 disposed within the second redistribution insulating layer 161 and vertically spaced apart from each other; and a plurality of heat dissipation vias 1723 disposed in the second redistribution insulating layer 161 and extending vertically in spaces between two adjacent heat dissipation pad layers of the plurality of heat dissipation pad layers 1721.
Therefore, claims 7–9, 11–12, 16, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6 Jan 2026.
Given that claims 14 and 21–24 were previously cancelled, this leaves claims 1–6, 10, 13, 15, 17–18, 20, and 25 to be examined in the present office action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “pad of the third semiconductor device” (claim 7 [a withdrawn claim], lines 4–5) must be shown to “extend in the molding layer” or this italicized limitation must be cancelled or modified in claim 7. That is, Fig. 7 shows that the pads 1313 of the third semiconductor device 131a are flush with the upper surface of the third semiconductor device 131a and therefore the pads 1313 do not extend in the molding layer 151. Perhaps the claim could be amended to specify that it is the conductive via pattern 1633 of the second redistribution pattern 163 that extends in the molding layer 151, which would overcome this drawing objection without requiring any modification to Fig. 7.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be cancelled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 25 is objected to because of the following informalities: “a straight line extending in horizontal direction” should be “a straight line extending in a horizontal direction” (page 10, lines 6–7). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5–6, 15, 18, 20, and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated1 by US-20240321839-A1 (“Mun” hereafter).
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Regarding claim 1, Mun teaches:
A semiconductor package 10 (Fig. 1, “semiconductor package 10” ¶[0028]) comprising:
a first redistribution structure 110 (“first redistribution structure 110” ¶[0030]) including a first redistribution insulating layer 111 (“first redistribution insulating layers 111” ¶[0032]) and a first redistribution pattern 113 (“first conductive redistribution pattern 113” ¶[0032]);
a first semiconductor device 121 (“first lower semiconductor device 121” ¶[0030]) mounted on the first redistribution structure 110;
a molding layer 151 (“molding layer 151” ¶[0030]) surrounding the first semiconductor device 121 on the first redistribution structure 110;
a second redistribution structure 160 (“second redistribution structure 160” ¶[0030]) disposed on the molding layer 151 and the first semiconductor device 121 and including a second redistribution insulating layer 161 (“second redistribution insulating layers 161” ¶[0052]) and a second redistribution pattern 163 (“second conductive redistribution pattern 163” ¶[0052]);
a plurality of vertical connection conductors 155 (“vertical connection conductors 155” ¶[0030]) vertically extending in the molding layer 151 and electrically connecting the first redistribution pattern 113 to the second redistribution pattern 163;
a second semiconductor device 181 (“upper semiconductor device 181” ¶[0061]) mounted on the second redistribution structure 160, wherein the second semiconductor device 181 and the first semiconductor device 121 vertically and partially overlap each other (as shown in Fig. 1);
a heat dissipation pad structure 171 (“heat dissipation pad structure 171 (e.g., a heat plate contact)” ¶[0030]) contacting an upper surface 129 of the first semiconductor device 121 (“The heat dissipation pad structure 171 may vertically penetrate the second redistribution insulating layer 161 and directly contact the upper surface 129 of the first lower semiconductor device 121” ¶[0057]); and
a heat dissipation plate 185 (“heat dissipation plate 185” ¶[0060]) disposed on the heat dissipation pad structure 171 and spaced apart (see Fig. 1 and ¶[0061]) from the second semiconductor device 181 along a first straight line extending in a horizontal direction X that is parallel to the upper surface 129 of the first semiconductor device 121.
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Regarding claim 5, Mun teaches:
The semiconductor package 13 (Fig. 6) of claim 1, further comprising:
a third semiconductor device 131 mounted on the first redistribution structure 110 and spaced apart from the first semiconductor device 121 along a second straight line extending in the horizontal direction X,
wherein an entire upper surface of the third semiconductor device 131 vertically overlaps the second semiconductor device 181.
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Regarding claim 6, Mun teaches:
The semiconductor package 13 (Fig. 6) of claim 5, further comprising:
a plurality of chip connection bumps 145 disposed in a space between the third semiconductor device 131 and the first redistribution structure 110.
Regarding claim 15, Mun teaches:
A semiconductor package 13 (Fig. 6) comprising:
a first redistribution structure 110 including a first redistribution insulating layer 111 and a first redistribution pattern 113;
a first semiconductor device 121 mounted on the first redistribution structure 110;
a molding layer 151 surrounding the first semiconductor device 121 on the first redistribution structure 110 without covering an upper surface 129 of the first semiconductor device 121;
a plurality of vertical connection conductors 155 extending vertically in the molding layer 151 and electrically connected to the first redistribution pattern 113;
a second semiconductor device 181 disposed on the molding layer 151 and electrically connected to the first redistribution pattern 113 through the plurality of vertical connection conductors 155; and
a heat dissipation plate 185 attached to the upper surface 129 of the first semiconductor device 121 and adjacent to the second semiconductor device 181 along a first straight line extending in a horizontal direction X that is parallel to the upper surface 129 of the first semiconductor device 121.
Regarding claim 18, Mun teaches:
The semiconductor package 13 (Fig. 6) of claim 15, further comprising:
a second redistribution structure 160 disposed on the molding layer 151 and the first semiconductor device 121 and including a second redistribution insulating layer 161 and a second redistribution pattern 163; and
a heat dissipation pad structure 171 disposed between the heat dissipation plate 185 and the upper surface 129 of the first semiconductor device 121 and provided in a through hole of the second redistribution insulating layer 161.
Regarding claim 20, Mun teaches:
The semiconductor package 13 (Fig. 6) of claim 15, further comprising:
a third semiconductor device 131 mounted on the first redistribution structure 110,
wherein a portion of the second semiconductor device 181 vertically overlaps the first semiconductor device 121, and
wherein another portion of the second semiconductor device 181 vertically overlaps the third semiconductor device 131.
Regarding claim 25, Mun teaches:
A semiconductor package 10 (Fig. 1) comprising:
a first redistribution structure 110 including a first redistribution insulating layer 111 and a first redistribution pattern 113;
a first semiconductor device 121 mounted on the first redistribution structure 110;
a plurality of chip connection bumps 143 disposed between the first semiconductor device 121 and the first redistribution structure 110;
a molding layer 151 surrounding the first semiconductor device 121 on the first redistribution structure 110 and having an upper surface 1511 that is coplanar with an upper surface 129 of the first semiconductor device 121;
a second redistribution structure 160 disposed on the molding layer 151 and the first semiconductor device 121 and including a second redistribution insulating layer 161 and a second redistribution pattern 163;
a plurality of vertical connection conductors 155 vertically penetrating the molding layer 151 and electrically connecting the first redistribution pattern 113 to the second redistribution pattern 163;
a second semiconductor device 181 mounted on the second redistribution structure 160;
a heat dissipation pad structure 171 disposed within the second redistribution insulating layer 161 and contacting the upper surface 129 of the first semiconductor device 121; and
a heat dissipation plate 185 disposed on the heat dissipation pad structure 171 and spaced apart from the second semiconductor device 181 along a straight line extending in horizontal direction X that is parallel to the upper surface 129 of the first semiconductor device 120,
wherein the first semiconductor device 121 comprises a logic chip (“the first lower semiconductor device 121 may include a logic chip” ¶[0068]),
wherein the second semiconductor device 181 comprises a memory chip (“the plurality of upper semiconductor devices 181 may include memory chips” ¶[0068]),
wherein the heat dissipation plate 185 is thermally coupled to the first semiconductor device 121 through the heat dissipation pad structure 171,
wherein a first portion of the first semiconductor device 121 vertically overlaps the second semiconductor device 181,
wherein a second portion of the first semiconductor device 121 vertically overlaps the heat dissipation plate 185,
wherein a ratio between a first length of the first portion of the first semiconductor device 121 to a total length of the first semiconductor device 121 is selected from a range between 10% to 45% (see Fig. 1 and ¶[0074]), and
wherein the first length and the total length are measured in the horizontal direction (“the ratio (i.e., L2/L1) of the length L2 along the first lateral direction (e.g., X direction) of the first overlapping region of the first lower semiconductor device 121 overlapping a single upper semiconductor device 181 to the total length L1 of the first lower semiconductor device 121 along the first lateral direction (e.g., the X direction) may be between about 20% and about 40%” ¶[0074]).
Claims 15 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US-20240040806-A1 (“Kim” hereafter).
Regarding claim 15, Kim teaches:
A semiconductor package 12 (Fig. 6) comprising:
a first redistribution structure 110 including a first redistribution insulating layer 111 and a first redistribution pattern 113;
a first semiconductor device 120 mounted on the first redistribution structure 110;
a molding layer 151 surrounding the first semiconductor device 120 on the first redistribution structure 110 without covering an upper surface (as shown in Fig. 6) of the first semiconductor device 120;
a plurality of vertical connection conductors 153 extending vertically in the molding layer 151 and electrically connected (see Fig. 6 and ¶[0042]) to the first redistribution pattern 113;
a second semiconductor device UP (“upper package UP” ¶[0073]) disposed on the molding layer 151 and electrically connected (see Fig. 6, ¶[0042], ¶[0066]) to the first redistribution pattern 113 through the plurality of vertical connection conductors 153; and
a heat dissipation plate 147 attached to the upper surface 129 of the first semiconductor device 120 (“The heat dissipation plate 147 may be attached to the top surface 129 of the first semiconductor chip 120 through a thermal conductive adhesive layer 149” ¶[0075]) and adjacent (as shown in Fig. 6) to the second semiconductor device UP along a first straight line extending in a horizontal direction X that is parallel to the upper surface 129 of the first semiconductor device 120.
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Regarding claim 17, Kim teaches:
The semiconductor package 12 (Fig. 6) of claim 15, further comprising:
a heat dissipation pad structure 149 (“thermal conductive adhesive layer 149” ¶[0075]) disposed between the heat dissipation plate 147 and the upper surface 129 of the first semiconductor device 120 and extending along the upper surface 129 of the first semiconductor device 120,
wherein the heat dissipation plate 147 is thermally coupled to the first semiconductor device 120 through the heat dissipation pad structure 149 (“The thermal conductive adhesive layer 149 may include a material, which is thermally conductive” ¶[0075]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over US-20230116326-A1 (“Yang” hereafter).
Regarding claim 1, Yang teaches:
A semiconductor package 2 (Fig. 2, “semiconductor package 2” ¶[0053]) comprising:
a first redistribution structure 100 (“the substrate 100 may be a re-distribution layer (RDL) substrate” ¶[0044]) including a first redistribution insulating layer RIL1 (see annotated Fig. 2) and a first redistribution pattern 100t (“comprise a plurality of conductive traces 100t” ¶[0044]);
a first semiconductor device 101 (“semiconductor die 101” ¶[0042]) mounted on the first redistribution structure 100;
a molding layer 120 (“molding compound 120” ¶[0042]) surrounding the first semiconductor device 101 on the first redistribution structure 100;
a second redistribution structure 200 (“middle re-distribution layer (RDL) structure 200” ¶[0046]) disposed on the molding layer 120 and the first semiconductor device 101 and including a second redistribution insulating layer 210 (“dielectric layers 210” ¶[0046]) and a second redistribution pattern 220 (“interconnect structures 220” ¶[0046]);
a plurality of vertical connection conductors 122 (“a plurality of through mold vias (TMVs) 122” ¶[0046]) vertically extending in the molding layer 120 and electrically connecting the first redistribution pattern 100t to the second redistribution pattern 220 (“signals transmitted to or from the semiconductor die 101 may be implemented through the connection path comprised of … the interconnect structures 220 of the middle RDL structure 200, the TMVs 122, the conductive traces 100t of the substrate 100 …” ¶[0052]);
a second semiconductor device 300 (“memory component 300” ¶[0055]) mounted on the second redistribution structure 200, wherein the second semiconductor device 300 and the first semiconductor device 101 vertically and partially overlap each other (as shown in Fig. 2);
a heat dissipation pad structure HDPS (see annotated Fig. 2 in which the region labeled “HDPS” encloses a portion of the second redistribution structure 200 vertically overlapped by the dummy die 400, a corresponding portion of the underfill material UF, and a corresponding portion of the conducting elements BP) contacting an upper surface of the first semiconductor device 101; and
a heat dissipation plate 400 (“the dummy die 400 … improves the thermal performance of the semiconductor package 2” ¶[0062]) disposed on the heat dissipation pad structure HDPS and spaced apart (as shown in Fig. 2) from the second semiconductor device 300 along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first semiconductor device 101.
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However, the examiner notes the following differences between Yang’s Fig. 2 and the semiconductor device described in the present claim (reading on Fig. 6 of the present application, which is the elected species of the semiconductor device): (1) Yang does not explicitly refer to the region of Fig. 2 that the examiner has annotated as HDPS as a heat dissipation pad structure; and (2) Yang does not explicitly refer to the dummy die 400 as a heat dissipation plate.
From the present application’s Fig. 6 and specification, the examiner understands the heat dissipation pad structure to be a heat plate contact—i.e., a structure made of thermally conductive material to facilitate heat transfer from the underlying first semiconductor device to the overlying heat dissipation plate, wherein said structure also acts as a platform or “pad” to attach the overlying heat dissipation plate.
Note that Yang states that “The memory component 300 and the dummy die 400 are mounted on the middle RDL structure 200 in a side-by-side manner. When viewed from above, the dummy die 400 may partially overlaps with the underlying semiconductor die 101. The off-center configuration of the memory component 300 relative to the underlying semiconductor die 101 allows the placement of the dummy die 400 directly on the semiconductor die 101, which improves the thermal performance of the semiconductor package 2” ¶[0062]. From this text, it would be understood by a person of ordinary skill in the art that the purpose of the dummy die 400 is to dissipate heat from the underlying semiconductor die 101, as facilitated by the dummy die 400 being placed “directly on” the semiconductor die 101, thereby improving the “thermal performance of the semiconductor package 2”. That is, the dummy die 400 functions as a heat dissipation plate. Furthermore, the use of “directly on” in this context (referring in ¶[0062] to the specific embodiment of the semiconductor package 2 shown in Fig. 2) implies that the first semiconductor die 101 and the dummy die 400 are in thermal contact with one another so that heat is conducted from the former to the latter; thus, the contact medium that spans the vertical gap between the upper surface of the first semiconductor device 101 and the lower surface of the dummy die 400 (i.e., the region of Fig. 2 that the examiner has annotated as HDPS), must perform the function of conducting heat from the former to the latter.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the region of Yang’s Fig. 2 that the examiner has annotated as HDPS acts as a heat dissipation pad structure by conducting heat from the underlying first semiconductor device 101 to the overlying dummy die 400, which acts as a heat dissipation plate which “improves the thermal performance of the semiconductor package 2” ¶[0062].
Regarding claim 4, Yang teaches:
The semiconductor package 2 (Fig. 2) of claim 1,
wherein a ratio (L1 ∕ L2) of a first length L1 of a first portion of the first semiconductor device 101 to a total length L2 (refer to Measurements Diagram below, in which the examiner has used PowerPoint to graphically measure lengths L1 and L2 in arbitrary length units of “inches”) of the first semiconductor device 101 is a value selected from a range between 10% to 45% (L1∕L2 = 1.55/3.46 = 35%),
wherein the first portion of the first semiconductor device 101 vertically overlaps the second semiconductor device 300, and
wherein the first length L1 of the first portion and the total length L2 are measured in the horizontal direction.
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US-20230116326-A1 (“Yang” hereafter) in view of US-20240321839-A1 (“Mun” hereafter).
Regarding claim 2, Yang teaches the semiconductor package of claim 1, as shown above.
However, Yang fails to teach that the heat dissipation pad structure HDPS vertically penetrates the second redistribution insulating layer 210. Penetrate is defined2 as “to pass into or through”. That is, this claim requires the heat dissipation pad structure to be a separate object from the second redistribution structure 200 so that the heat dissipation pad structure passes into or through the second redistribution insulating layer 210 of the second redistribution structure 200, whereas the heat dissipation pad structure HDPS annotated in Fig. 2 comprises a part of the second redistribution insulating layer 210. It would not make sense to say that the part of the second redistribution insulating layer 210 that is inside the region annotated as HDPS penetrates the rest of the second redistribution insulating layer 210 because both the part and the rest are referring to a single object.
Mun’s semiconductor package 10 (Fig. 1) shares many features in common with Yang’s semiconductor package 2 (Fig. 2), such as both semiconductor packages having upper and lower redistribution structures connected by vertical connection conductors, a lower semiconductor device located between the upper and lower redistribution structures, and at least one upper semiconductor device located on and above the upper redistribution structure.
In Mun’s semiconductor package 10 (Fig. 1), a heat dissipation pad structure 171 vertically penetrates the second redistribution insulating layer 161. Mun states: “The heat dissipation pad structure 171 (e.g., the heat plate contact) may contact the upper surface 129 of the first lower semiconductor device 121. The heat dissipation pad structure 171 is thermally coupled to the first lower semiconductor device 121 … The heat dissipation pad structure 171 may vertically penetrate the second redistribution insulating layer 161 and directly contact the upper surface 129 of the first lower semiconductor device 121. The heat dissipation pad structure 171 may be a thermally conductive contact or block having an enlarged pad shape” ¶[0057].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s semiconductor package 2 (Fig. 2) by replacing the region the examiner has annotated as HDPS with a thermally conductive contact or block having an enlarged pad shape similar to Mun’s heat dissipation pad structure 171 (Fig. 1) in order to thermally couple the first semiconductor device 101 to the heat dissipation plate 400. In this way, rather than heat being transferred through the region annotated as HDPS (including a portion of the second redistribution structure 200 vertically overlapped by the dummy die 400, a corresponding portion of the underfill material UF, and a corresponding portion of the conducting elements BP), heat would be transferred through the thermally conductive contact or block having an enlarged pad shape which would vertically penetrate the second redistribution insulating layer 210. Furthermore, Mun states:
“[0060] The heat dissipation pad structure 171 may include a material having excellent thermal conductivity, for example, metal. In embodiments, the heat dissipation pad structure 171 may include copper (Cu) or aluminum (Al). The heat dissipation pad structure 171 may function to transfer heat generated from the first lower semiconductor device 121 to the outside of the semiconductor package 10 and/or to the heat dissipation plate 185. In embodiments, the heat dissipation pad structure 171 may be formed together with the second conductive redistribution pattern 163 of the second redistribution structure 160 through the same metal interconnect process. In this case, the material and/or material composition of the heat dissipation pad structure 171 may be substantially the same as the material and/or material composition of the second conductive redistribution pattern 163. In embodiments, the heat dissipation pad structure 171 may be formed through a process different from the process of forming the second conductive redistribution pattern 163 of the second redistribution structure 160. In embodiments, a material and/or material composition of the heat dissipation pad structure 171 may be different from a material and/or material composition of the second conductive redistribution pattern 163.”
The examiner understands the above quotation to mean that the heat dissipation pad structure 171 can either be a portion of the metallic, thermally conductive second redistribution pattern 163 of the second redistribution structure 160 (i.e., the portion that is vertically overlapped by the heat distribution plate 185), or the heat dissipation pad structure 171 can be a separate object (likewise including a highly thermally conductive material such as Cu or Al metal) that is formed in a separate process from that used to form the second redistribution structure 160. The former option is that which is already in Yang’s Fig. 2 in the region annotated as HDPS, and the latter option is that which is required by the present claim, in which the heat dissipation pad structure is a separate object from the second redistribution structure such that the heat dissipation pad structure vertically penetrates the second redistribution insulating layer of the second redistribution structure.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US-20230116326-A1 (“Yang” hereafter) in view of US-20230015721-A1 (“Chia” hereafter).
Regarding claim 3, Yang teaches the semiconductor package of claim 1, as shown above.
However, Yang fails to teach that an upper surface of the molding layer 120 is coplanar with the upper surface of the first semiconductor device 101.
Chia’s electronic package 2 (Fig. 2D) shares many features in common with Yang’s semiconductor package 2 (Fig. 2), such as both packages having upper and lower redistribution structures connected by vertical connection conductors, a lower semiconductor device located between the upper and lower redistribution structures, and at least one upper semiconductor device located on and above the upper redistribution structure.
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Note that in Chia’s electronic package 2 (Fig. 2D), the upper surface of the molding layer 22 (“encapsulation layer 22” ¶[0020]) is coplanar with the upper surface of the first semiconductor device 21 (“The first electronic element 21 is an active element (such as a semiconductor chip)” ¶[0023]). Chia states: “a planarization process is performed, such that a surface 22a of the encapsulation layer 22 is flush with the non-active surface 21b of the first electronic element 21 and end surfaces 23a of the conductive pillars 23” ¶[0025]. Fig. 2D shows that this arrangement places the upper surface of the first semiconductor device 21 in direct contact3 with the first metal layer 24. The first metal layer 24 performs the same function as the heat dissipation pad structure of the present application in that the first metal layer 24 conducts heat from the first semiconductor device 21 to a heat dissipation plate 29: “The first metal layer 24, the thermally conductive circuit 252,4 the thermally conductive pillar 26 and the second metal layer 29 serve as heat dissipation paths of the first electronic element 21” ¶[0036].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s semiconductor package 2 (Fig. 2) to have an upper surface of the molding layer 120 be coplanar with the upper surface of the first semiconductor device 101 similar to the arrangement shown in Chia’s Fig. 2D because Chia teaches that such an arrangement conducts heat from the first (i.e., lower) semiconductor device (Chia’s 21 or Yang’s 101) directly to an upwardly adjacent metal layer of the redistribution structure above (i.e., Chia’s first metal layer 24 of the circuit structure 25 or a lowest metal layer of Yang’s second redistribution pattern 220 of the second redistribution structure 200). This is in agreement with the idea that the region of Yang’s Fig. 2 annotated by the examiner as HDPL functions as a heat dissipation pad layer to transfer heat from the underlying first semiconductor device 101 to the overlying heat transfer plate 400.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US-20230116326-A1 (“Yang” hereafter) in view of US-9613931-B2 (from the IDS, “Lin” hereafter).
Regarding claim 5, Yang teaches the semiconductor package of claim 1, as shown above.
However, Yang fails to teach that there is:
a third semiconductor device mounted on the first redistribution structure 100 and spaced apart from the first semiconductor device 101 along a second straight line extending in the horizontal direction,
wherein an entire upper surface of the third semiconductor device vertically overlaps the second semiconductor device 300.
Lin’s device package 200 (Fig. 4) shares many features in common with Yang’s semiconductor package 2 (Fig. 2), such as both packages having upper and lower redistribution structures connected by vertical connection conductors, a first semiconductor device located between the upper and lower redistribution structures, and at least one second semiconductor device located on and above the upper redistribution structure.
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Note that Lin’s device package 200 includes a third semiconductor device 106 (i.e., the left one of the two “dummy dies 106”) mounted on the first redistribution structure 108A (“RDL 108A”) and spaced apart from the first semiconductor device 102 (“die 102”) along a second straight line extending in the horizontal direction,
wherein an entire upper surface of the third semiconductor device 106 vertically overlaps (as shown in Fig. 4) the second semiconductor device 104 (i.e., the left of the two “die 104”).
Lin states: “in package 200, die 102 may occupy a smaller footprint than dies 104. Thus, absent dummy dies 106, an effective CTE of tier 101A may be lower than an effective CTE of tier 101B. Thus, dummy dies 106 comprising a relatively low CTE material (e.g., silicon or glass) may be included in tier 101A to lower its effective CTE, reducing CTE mismatch and warpage” (column 8, lines 3–13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s semiconductor package 2 (Fig. 2) to include a dummy die as a third semiconductor device horizontally in line with the first semiconductor device 101 in a similar arrangement to Lin’s (Fig. 4) dummy die 106 and first semiconductor device 102 for the purpose of reducing warpage by reducing a mismatch in the coefficient of thermal expansion (CTE) between the upper and lower tiers of the stacked semiconductor devices, wherein Yang’s (Fig. 2) modified lower tier comprises the first semiconductor device and an added dummy die (i.e., the third semiconductor device) and the upper tier comprises the second semiconductor device 300 and the heat dissipation plate 400.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US-20230116326-A1 (“Yang” hereafter) in view of US-20240040806-A1 (“Kim” hereafter).
Regarding claim 10, Yang teaches the semiconductor package 2 (Fig. 2) of claim 1,
wherein the first redistribution pattern 100t comprises:
a first conductive layer CL1 (see annotated Fig. 2 in which “CL1” points to a lowermost layer of the first redistribution pattern 100t) disposed within the first redistribution insulating layer RIL1 (see annotated Fig. 2);
an external connection pad 100s to which an external connection terminal SB provided below the first redistribution structure 100 is attached (“Solder balls SB are disposed on the ball pads 100s, respectively” ¶[0044]);
wherein the second redistribution pattern 220 comprises:
a second conductive layer CL2 (see annotated Fig. 2 in which “CL2” points to a lowermost layer of the second redistribution pattern 220) disposed within the second redistribution insulating layer 210.
However, Yang’s Fig. 2 fails to show:
a first conductive via extending in a vertical direction between the first conductive layer CL1 and the external connection pad 100s, and
a second conductive via extending in the vertical direction from the second conductive layer CL2 toward one of the plurality of vertical connection conductors 122,
wherein the first conductive via has a narrowing horizontal width toward the external connection pad 100s, and
wherein the second conductive via has a narrowing horizontal width toward one of the plurality of vertical connection conductors 122.
Kim’s semiconductor package 15 (Fig. 9) shares many features in common with Yang’s semiconductor package 2 (Fig. 2), such as both packages having upper and lower redistribution structures connected by vertical connection conductors, a first semiconductor device located between the upper and lower redistribution structures, a second semiconductor device located on and above the upper redistribution structure, and external connection terminals on the bottom side of the lower redistribution structure.
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Kim’s semiconductor package 15 (Fig. 9) includes:
a first conductive via 1133 (“first conductive via patterns 1133” ¶[0028]) extending in a vertical direction between the first conductive layer 1131 (“first conductive layers 1131” ¶[0028]) and the external connection pad 1135 (“external connection pads 1135” ¶[0028]), and
a second conductive via 1833 (“second conductive via patterns 1833” ¶[0085]) extending in the vertical direction from the second conductive layer 1831 (“second conductive layers 1831” ¶[0085]) toward one of the plurality of vertical connection conductors 153 (“conductive posts 153” ¶[0085]),
wherein the first conductive via 1133 has a narrowing horizontal width5 (as shown in Fig. 9) toward the external connection pad 1135, and
wherein the second conductive via has a narrowing horizontal width6 (as shown in Fig. 9) toward one of the plurality of vertical connection conductors 153.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s semiconductor package 2 (Fig. 2) to include a first conductive via and a second conductive via in the particular locations specified in this claim because Kim’s semiconductor package 15 (Fig. 9) has conductive vias in analogous locations in the first and second redistribution structures, respectively. Also, the tapered shape of Kim’s first conductive via 1133 and second conductive via 1833, with the bottom end of each via being narrower than the top end, clearly satisfies the “narrowing” requirement of the present claim. Furthermore, conductive vias are known to be common features within redistribution structures (RDLs) that provide vertical interconnection between different horizontal metallization layers of the redistribution pattern disposed within the redistribution insulating layers of a redistribution structure.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US-20230116326-A1 (“Yang” hereafter) in view of US-10170456-B2 (from the IDS, “Sung” hereafter).
Regarding claim 13, Yang teaches the semiconductor package of claim 1, as shown above.
However, Yang fails to teach that a thermal conductivity of the heat dissipation plate 400 is greater than a thermal conductivity of silicon.
In the same field of endeavor, Sung teaches that a heat dissipation layer 5600 (Fig. 8) “may be formed to include a metal material having a relatively high thermal conductivity. For example, the heat dissipation layer 5600 may be formed of an aluminum material or a copper material” (column 18, lines 28–32). Also, Sung states: “A copper material may have a thermal conductivity of about 385 W/mK which is higher than twice that of a silicon material.”
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s semiconductor package 2 (Fig. 2) by replacing the dummy die 400 with a heat dissipation layer made of a metal such as copper similar to Sung’s heat dissipation layer 5600 (Fig. 8). It was argued in the rejection of claim 1 that Yang’s dummy die 400 performs the same function (i.e., dissipating heat from an underlying semiconductor device) as the heat dissipation plate of the present application. Therefore, replacing Yang’s dummy die 400, which is a “dummy silicon die” ¶[0073], with a copper block would result in a more effective heat dissipation plate than the dummy die 400 because copper has a higher thermal conductivity than silicon, and thus a copper block would be more effective in transferring heat away from the first semiconductor device 101 and radiating that heat away from the semiconductor package 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US-20240105689-A1—see Fig. 2 and ¶[0066]: “The dummy chip 700 may be provided between the memory semiconductor chips 600 and may be configured to absorb heat that is emitted from the memory semiconductor chips 600, and may release the heat to the outside of the semiconductor package 10. The dummy chip 700 may absorb the heat that is emitted from the upper redistribution wiring layer 500, and may release the heat to the outside of the semiconductor package 10.”
US-20240055394-A1—see Fig. 12 and ¶[0105]: “When the ninth semiconductor chip 350 includes a thermal radiation member, heat may be outwardly discharged through the ninth semiconductor chip 350 from the first semiconductor chip 210 and the seventh semiconductor chip 260.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
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/A.J.M./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
1 US 2024/0321839 A1 claims foreign priority to KR10-2023-0039308, filed on 24 Mar 2023, before the present application’s US filing date of 26 Jun 2023 but after the present application’s claimed foreign priority date of 6 Oct 2022.
2 “penetrate,” Merriam-Webster.com Dictionary, https://www.merriam-webster.com/dictionary/penetrate. Accessed 2/6/2026.
3 “As shown in FIG. 2B, a first metal layer 24 is in contact with and bonded on the non-active surface 21b of the first electronic element 21” Chia ¶[0027]
4 Refer to Chia’s Fig. 2B.
5 Kim: “[0087] In embodiments, each of the second conductive via patterns 1833 may have a tapered shape having a horizontal width decreasing from the top thereof toward the bottom thereof. In other words, the horizontal width of each of the second conductive via patterns 1833 may decrease toward the first redistribution structure 110.”
6 Kim: “[0031] In embodiments, each of the first conductive via patterns 1133 may have a tapered shape having a horizontal width decreasing from the top thereof toward the bottom thereof. The horizontal width of each of the first conductive via patterns 1133 may decrease toward the top surface of an external connection pad 1135.”