DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the amendment filed on 12/19/2025. This Action is made FINAL.
Claims 1-20 are pending and they are presented for examination.
Response to Amendment
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 14, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al. (Pub 20230004417) (hereafter Narayanan) in view of Wagle et al. (Pub 20160371194) (hereafter Wagle).
As per claim 1, Narayanan teaches:
A processor, comprising:
circuitry to, in response to receiving an application programming interface (API) call, return an indication of which of one or more non-uniform memory access (NUMA) storages and one or more graphics processing unit (GPU) storages correspond to one or more storages indicated by the API call. ([Paragraph 1], Virtualization allows system software called a virtual machine monitor (VMM), also known as a hypervisor, to create multiple isolated execution environments called virtual machines (VMs) in which operating systems (OSs) and applications can run. [Paragraph 65], user priority inputs (high/medium/low) are read from the VM configuration file, the selection policy is intelligent and the NUMA preferred node of the running VM and input device class for which an ADI is to be selected are determined. [Paragraph 81], The Graphics Processor Unit (GPU) module 810 may include one or more GPU cores and a GPU cache which may store graphics related data for the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. Additionally, the Graphics Processor Unit (GPU) module 810 may contain other graphics logic units that are not shown in FIG. 8, such as one or more vertex processing units, rasterization units, media processing units, and codecs. [Paragraph 52], In addition, in order to preserve priorities that may be determined at the application level by users, an optional user configuration file can be used to specify a priority High, Medium, Low) for a VM and an option to incorporate priorities in the selection policy, or override the selection policy with priorities. If there is a conflict in resource allocation, the priority assigned to each VM is used to determine the best ADI to assign. For example, if two VMs request a VDEV composition, based upon the VM's priority (High/Med/Low), the ADI is assigned to the VM with the higher priority. [Paragraph 24], System software can use an API to request intelligent selection of an ADI for a device class by traversing the ADI selection tree to select the ADI for the device class. The traverse of the ADI selection tree is performed in response to the request from an application through an application programming interface (API) call.)
Narayanan teaches issuing an API call and having a user preferred nodes which includes NUMA storages and GPUs. [Narayanan paragraph 43, 65, 81].
However, Narayanan does not explicitly disclose return an indication of which of one or more non-uniform memory access (NUMA) storages and one or more graphics processing unit (GPU) storages correspond to one or more storages indicated by the API call.
Wagle teaches return an indication of which of one or more non-uniform memory access (NUMA) storages and one or more graphics processing unit (GPU) storages correspond to one or more storages indicated by the API call. ([Paragraph 27], The NUMA API currently supports four different policy flavors: default: Allocate on the local node (the node the thread is running on)… bind: Allocate on a specific set of nodes… preferred: Try to allocate on a node first… [Paragraph 32], FIG. 3, NUMA policy is set for virtual memory addresses using APIs from the ‘libnuma’ library. FIG. 4 illustrates use of a new API “ALLOC_ON_NUMA_NODE (<N>)” which wraps these libnuma APIs in order to set NUMA policy for virtual memory addresses. [Paragraph 39], First, at S535, the memory manager sets the NUMA policy to ‘preferred’ by calling a libnuma API (e.g., numa_set_bind_policy(0)). Next, at S540, the allocation bit mask is set to the first node (e.g., numa_bitmask_setbit(mask, 7)). The reserved memory is bound to the first node at S545 using, e.g., the numa_tonodemask_memory(ptr, <size>, mask) API call. S550 then includes setting a second NUMA policy to act as a fallback policy in a low memory or out-of-memory condition. In the present example, the second NUMA policy is the interleaved policy but embodiments are not limited thereto. [Paragraph 41], The portion may have a size corresponding to the Small, Medium or Big sub-allocators. The address pointer of the identified portion is then returned to the worker thread at S565 (e.g., RESPONSE of FIG. 6).
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users and prefetch buffers exist to store prefetched data, into teachings of Wagle wherein an indication of preferred storages are returned via address pointers, because this would enhance the teachings of Narayanan wherein by returning an indication of storages based on preference and fallback policy allows flexibility of requesting and subsequently allocating/assigning a storage in an order of preference/priority based on availability. [Wagle paragraph 39-40]
As per claim(s) 8 is/are system claim(s) corresponding to processor claim(s) 1. Therefore, rejected based on similar rationale.
As per claim(s) 14 is/are method claim(s) corresponding to processor claim(s) 1. Therefore, rejected based on similar rationale.
As per claim 18, rejection of claim 14 is incorporated:
Narayanan teaches wherein the one or more NUMA storages are physical memories included in one or more NUMA nodes that each include one or more central processing units (CPUs). ([Paragraph 31], With software-based Input/Output (I/O) virtualization, the VMM exposes a virtual device (such as network interface controller (NIC) functionality, for example) to a VM. Some examples of a NIC are part of an Infrastructure Processing Unit (IPU) or data processing unit (DPU) or utilized by an IPU or DPU. An IPU or DPU can include a network interface, memory devices, and one or more programmable or fixed function processors (e.g., CPU or XPU) to perform offload of operations that could have been performed by a host CPU or XPU or remote CPU or XPU. In some examples, the IPU or DPU can perform virtual switch operations, manage storage transactions (e.g., compression, cryptography, virtualization), and manage operations performed on other IPUs, DPUs, servers, or devices. [Paragraph 76], The SoC 804 includes at least one Central Processing Unit (CPU) module 808, a memory controller 814, and a Graphics Processor Unit (GPU) module 810. In other embodiments, the memory controller 814 may be external to the SoC 804 and the GPU module may be external to the SoC 804. The CPU module 808 includes at least one processor core 802 and a level 2 (L2) cache 806.)
As per claim 20, rejection of claim 14 is incorporated:
Narayanan teaches A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method of claim 14. ([Paragraph 86], A non-transitory machine-readable storage medium can cause a machine to perform the functions or operations described, and includes any mechanism that stores information in a form accessible by a machine (for example, computing device, electronic system, etc.), such as recordable/non-recordable media (for example, read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).)
Claim(s) 2-7, 9-13, 15-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan in view of Wagle and further in view of Roberts (Pub 20220342568).
As per claim 2, rejection of claim 1 is incorporated:
Although Narayanan teaches prefetch buffers ([Paragraph 77], Although not shown, the processor core 802 may internally include one or more instruction/data caches (L1 cache), execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating point units, retirement units, etc.)
Narayanan and Wagle do not explicitly disclose wherein the API is to indicate a NUMA node to which data was last prefetched by another API.
Roberts teaches wherein the API is to indicate a NUMA node to which data was last prefetched by another API. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected by another API, because this would enhance the teachings of Narayanan and Wagle wherein by indicating a tier of memory/storage which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim 3, rejection of claim 1 is incorporated:
Narayanan teaches preferred location of one or more memory addresses by API(s) ([Paragraph 1], Virtualization allows system software called a virtual machine monitor (VMM), also known as a hypervisor, to create multiple isolated execution environments called virtual machines (VMs) in which operating systems (OSs) and applications can run. [Paragraph 65], user priority inputs (high/medium/low) are read from the VM configuration file, the selection policy is intelligent and the NUMA preferred node of the running VM and input device class for which an ADI is to be selected are determined. [Paragraph 81], The Graphics Processor Unit (GPU) module 810 may include one or more GPU cores and a GPU cache which may store graphics related data for the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. Additionally, the Graphics Processor Unit (GPU) module 810 may contain other graphics logic units that are not shown in FIG. 8, such as one or more vertex processing units, rasterization units, media processing units, and codecs. [Paragraph 52], In addition, in order to preserve priorities that may be determined at the application level by users, an optional user configuration file can be used to specify a priority High, Medium, Low) for a VM and an option to incorporate priorities in the selection policy, or override the selection policy with priorities. If there is a conflict in resource allocation, the priority assigned to each VM is used to determine the best ADI to assign. For example, if two VMs request a VDEV composition, based upon the VM's priority (High/Med/Low), the ADI is assigned to the VM with the higher priority.)
Roberts teaches wherein the API is to indicate a NUMA node set as a preferred location of one or more memory addresses by another API. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected by another API, because this would enhance the teachings of Narayanan and Wagle wherein by indicating a tier of memory/storage (preferred location) which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim 4, rejection of claim 1 is incorporated:
Narayanan teaches wherein the API is to indicate a location type and a location identity of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. ([Paragraph 1], Virtualization allows system software called a virtual machine monitor (VMM), also known as a hypervisor, to create multiple isolated execution environments called virtual machines (VMs) in which operating systems (OSs) and applications can run. [Paragraph 65], user priority inputs (high/medium/low) are read from the VM configuration file, the selection policy is intelligent and the NUMA preferred node of the running VM and input device class for which an ADI is to be selected are determined. [Paragraph 81], The Graphics Processor Unit (GPU) module 810 may include one or more GPU cores and a GPU cache which may store graphics related data for the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. Additionally, the Graphics Processor Unit (GPU) module 810 may contain other graphics logic units that are not shown in FIG. 8, such as one or more vertex processing units, rasterization units, media processing units, and codecs. [Paragraph 52], In addition, in order to preserve priorities that may be determined at the application level by users, an optional user configuration file can be used to specify a priority High, Medium, Low) for a VM and an option to incorporate priorities in the selection policy, or override the selection policy with priorities. If there is a conflict in resource allocation, the priority assigned to each VM is used to determine the best ADI to assign. For example, if two VMs request a VDEV composition, based upon the VM's priority (High/Med/Low), the ADI is assigned to the VM with the higher priority. [Paragraph 35], Virtual Device (VDEV) 104 is the abstraction through which a shared physical device is exposed to software in guest VM 122. VDEVs 104 are exposed to guest VM 122 as virtual PCI Express enumerated devices, with virtual resources such as virtual Requester-ID, virtual configuration space registers, virtual memory Base Address Registers (BARs), )
Roberts teaches wherein the API is to indicate a location type and a location identity of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected by another API, because this would enhance the teachings of Narayanan and Wagle wherein by indicating a tier of memory/storage (identity) which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim 5, rejection of claim 1 is incorporated:
However, Narayanan and Wagle do not explicitly disclose wherein the API is to receive one or more inputs that indicate a range of memory.
Roberts teaches wherein the API is to receive one or more inputs that indicate a range of memory. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected by another API, because this would enhance the teachings of Narayanan and Wagle wherein by indicating a tier of memory/storage (range of memory) which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim 6, rejection of claim 1 is incorporated:
Wagle discloses returning an address (i.e. virtual memory). [Paragraph 23]
However, Narayanan and Wagle do not explicitly disclose wherein the one or more storages indicated by one or more users is a range of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs.
Roberts teaches wherein the one or more storages indicated by one or more users is a range of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
Narayanan also teaches ([Paragraph 65], user priority inputs (high/medium/low) are read from the VM configuration file, the selection policy is intelligent and the NUMA preferred node of the running VM and input device class for which an ADI is to be selected are determined. [Paragraph 81], The Graphics Processor Unit (GPU) module 810 may include one or more GPU cores and a GPU cache which may store graphics related data for the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. Additionally, the Graphics Processor Unit (GPU) module 810 may contain other graphics logic units that are not shown in FIG. 8, such as one or more vertex processing units, rasterization units, media processing units, and codecs. [Paragraph 35], Virtual Device (VDEV) 104 is the abstraction through which a shared physical device is exposed to software in guest VM 122. VDEVs 104 are exposed to guest VM 122 as virtual PCI Express enumerated devices, with virtual resources such as virtual Requester-ID, virtual configuration space registers, virtual memory Base Address Registers (BARs), [Paragraph 43], For example, the ACPI STRAT allows the operating system to associate processors, memory ranges and generic initiators (for example, heterogenous processors and accelerators, GPUs and I/O devices with integrated compute or DMA engines) with system locality/proximity domains and clock domains.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected by another API, because this would enhance the teachings of Narayanan and Wagle wherein by indicating a tier of memory/storage (range of virtual memory) which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim 7, rejection of claim 1 is incorporated:
Wagle discloses returning an address.
However, Narayanan and Wagle do not explicitly disclose wherein the API is to return an identifier of a location type and an identifier of a location identity based, at least in part, on one or more inputs that indicate a range of memory.
Roberts teaches wherein the API is to return an identifier of a location type and an identifier of a location identity based, at least in part, on one or more inputs that indicate a range of memory. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
Narayanan also teaches ( [Paragraph 65], user priority inputs (high/medium/low) are read from the VM configuration file, the selection policy is intelligent and the NUMA preferred node of the running VM and input device class for which an ADI is to be selected are determined. [Paragraph 81], The Graphics Processor Unit (GPU) module 810 may include one or more GPU cores and a GPU cache which may store graphics related data for the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. Additionally, the Graphics Processor Unit (GPU) module 810 may contain other graphics logic units that are not shown in FIG. 8, such as one or more vertex processing units, rasterization units, media processing units, and codecs. [Paragraph 35], Virtual Device (VDEV) 104 is the abstraction through which a shared physical device is exposed to software in guest VM 122. VDEVs 104 are exposed to guest VM 122 as virtual PCI Express enumerated devices, with virtual resources such as virtual Requester-ID, virtual configuration space registers, virtual memory Base Address Registers (BARs), [Paragraph 43], For example, the ACPI STRAT allows the operating system to associate processors, memory ranges and generic initiators (for example, heterogenous processors and accelerators, GPUs and I/O devices with integrated compute or DMA engines) with system locality/proximity domains and clock domains.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected by another API, because this would enhance the teachings of Narayanan wherein by indicating a tier of memory/storage (identifier) which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim 11, rejection of claim 8 is incorporated:
Narayanan does not explicitly disclose wherein the API is to indicate a NUMA node to which a range of virtual memory indicated by the one or more users was last prefetched.
Roberts teaches wherein the API is to indicate a NUMA node to which a range of virtual memory indicated by the one or more users was last prefetched. ([Paragraph 20], BLOCK_PREFETCH(addr_src, size, tier) can represent a processor instruction with parameters addr_src, size, and tier, where the processor instruction causes generation of one or more memory instructions to a memory sub-system to prefetch (e.g., copy) data (e.g., data block), beginning at a source memory address (e.g., source virtual memory address) specified by a add_src parameter and having a size specified (e.g., in number of bytes) by a size parameter, to a target memory tier specified by a tier parameter.. The BLOCK_PREFETCH(addr_src, size, tier) can be performed, for example, to prefetch data from a first memory tier being used for persistent or long-term data storage, while a second memory tier specified by the tier parameter can be used for caching data.. [Paragraph 13], For example, data movement/migration/placement across memory tiers often involves a software application invoking the operating system (e.g., via Application Program Interface (API) calls), manipulating page table, using translational lookaside buffers (TLBs), or walking a page table. An existing example of this is non-uniform memory access (NUMA), which when supported by an operating system (e.g., LINUX) permits a software application to use calls to the operating system to specify a preference for allocated memory to reside locally or remotely relative to a central processing unit (CPU). [Paragraph 49], As described herein, the memory instruction received at operation 202 can be part of a plurality of memory instructions received from the host system (e.g., 120), where the plurality of memory instructions is generated and sent by the host system in response to a processor instruction (for copying data across memory tiers) received by the hardware processor of the host system. [Paragraph 28], As used herein, a tier (or memory tier) of a memory sub-system can refer to a logical memory performance level of the memory sub-system, where two different memory locations (e.g., physical memory locations) or two different memory devices of the memory sub-system can be associated with a different tier.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Narayanan and Wagle wherein an API(s) is/are utilized to indicate an API corresponds to a NUMA node (with processor and storage), priority level for NUMA preference is determined at an application level by users, prefetch buffers exist to store prefetched data and return and indication of assigned/allocated preferred storage (via address), into teachings of Roberts wherein the API is to indicate NUMA node which data was last perfected (range of virtual memory) by another API, because this would enhance the teachings of Narayanan and Wagle wherein by indicating a tier of memory/storage which offers prefetching/caching it allows API/application to take advantage of performance and functional benefits associated with user application priority and preference. [Narayana paragraph 25, 52] [Roberts paragraph 28]
As per claim(s) 9, 10, 12, 13 is/are system claim(s) corresponding to processor claim(s) 2-6. Therefore, rejected based on similar rationale.
As per claim(s) 15, 16, 17, 19 is/are method claim(s) corresponding to processor claim(s) 1, 2, 5, 6. Therefore, rejected based on similar rationale.
[Claim 15 Narayanan discloses managed memory location paragraph 11, fig. 3 and Roberts paragraph 11]
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DONG U KIM/Primary Examiner, Art Unit 2197
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