DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 4 and 17 are objected to because of the following informalities: “dual-gate connection line” should read “double-gate connection line” (claim 4, lines 6 and 8; and claim 17, lines 6 and 8). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7, 13, 14 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2010/0244022 A1 (hereinafter “Takahashi”).
Regarding claim 1, Takahashi discloses in Fig. 10 and related text a driving backplane, comprising:
a substrate (1; [0127]);
a first gate (2; [0128]) disposed on the substrate;
an active layer (4, 5, 6; [0128] and [0144]) disposed on a side of the first gate away from the substrate, the active layer comprising a source region (6; [0128]), a drain region (5; [0128]), and a channel region (4; [0128]); and
a second gate (8; [0128]) disposed on a side of the active layer away from the first gate and connected (indirectly physically) to the first gate,
wherein a first orthographic projection of the first gate on the active layer has a first (right) side line and a second (left) side line opposite to each other;
a second orthographic projection of the second gate on the active layer has a third (right) side line and a fourth (left) side line opposite to each other;
at least a part of the first side line coincides with the third side line, and/or at least a part of the second side line coincides with the fourth side line (see Fig. 10 below with vertical dashed lines superimposed thereon to prove coincidence (i.e., alignment)); and
a part of the third side line intersecting the active layer constitutes a first boundary line between the source region and the channel region, and a part of the fourth side line intersecting the active layer constitutes a second boundary line between the drain region and the channel region (shown in Fig. 10 below).
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Regarding claim 6, Takahashi discloses the first gate comprises an opaque conductive material (molybdenum (Mo); [0130]-[0131]), and the second gate comprises a transparent conductive material (indium tin oxide (ITO); [0139]-[0140]).
Regarding claim 7, Takahashi discloses a method of manufacturing a driving backplane, comprising:
providing a substrate (1; Fig. 8A; [0129]);
forming a first gate (2; Fig. 8A; [0130]-[0131]) on a first side (top side) of the substrate;
forming an active layer (4, 5, 6; Figs. 8C, 9C; [0135], [0137] and [0144]) and a second gate (8; Figs. 9A-9B; [0139]-[0141]) sequentially stacked above the first gate,
wherein the second gate is connected (indirectly physically) to the first gate;
the active layer comprises a source region (6; Fig. 9C; [0144]), a drain region (5; Fig. 9C; [0144]), and a channel region (4; Fig. 9C; [0144]);
a first orthographic projection of the first gate on the active layer has a first (right) side line and a second (left) side line opposite to each other (Fig. 10);
a second orthographic projection of the second gate on the active layer has a third (right) side line and a fourth (left) side line opposite to each other (Fig. 10);
at least a part of the first side line coincides with the third side line, and/or at least a part of the second side line coincides with the fourth side line (see Fig. 10 above with vertical dashed lines superimposed thereon to prove coincidence (i.e., alignment)); and
a part of the third side line intersecting the active layer constitutes a first boundary line between the source region and the channel region, and a part of the fourth side line intersecting the active layer constitutes a second boundary line between the drain region and the channel region (shown in Fig. 10 above).
Regarding claim 13, Takahashi discloses the first gate comprises an opaque conductive material (molybdenum (Mo); [0130]-[0131]), and the second gate comprises a transparent conductive material (indium tin oxide (ITO); [0139]-[0140]).
Regarding claim 14, Takahashi discloses in Fig. 10 and related text a display panel comprising a driving backplane,
wherein the driving backplane comprises:
a substrate (1; [0127]);
a first gate (2; [0128]) disposed on the substrate;
an active layer (4, 5, 6; [0128] and [0144]) disposed on a side of the first gate away from the substrate, the active layer comprising a source region (6; [0128]), a drain region (5; [0128]), and a channel region (4; [0128]); and
a second gate (8; [0128]) disposed on a side of the active layer away from the first gate and connected (indirectly physically) to the first gate,
wherein a first orthographic projection of the first gate on the active layer has a first (right) side line and a second (left) side line opposite to each other;
a second orthographic projection of the second gate on the active layer has a third (right) side line and a fourth (left) side line opposite to each other;
at least a part of the first side line coincides with the third side line, and/or at least a part of the second side line coincides with the fourth side line (see Fig. 10 above with vertical dashed lines superimposed thereon to prove coincidence (i.e., alignment)); and
a part of the third side line intersecting the active layer constitutes a first boundary line between the source region and the channel region, and a part of the fourth side line intersecting the active layer constitutes a second boundary line between the drain region and the channel region (shown in Fig. 10 above).
Regarding claim 19, Takahashi discloses the first gate comprises an opaque conductive material (molybdenum (Mo); [0130]-[0131]), and the second gate comprises a transparent conductive material (indium tin oxide (ITO); [0139]-[0140]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 8 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of US 2015/0108481 A1 (hereinafter “Khang”).
Regarding claim 2, Takahashi discloses the driving backplane according to claim 1, further comprising: an interlayer dielectric layer (10; Fig. 10; [0142] and [0145]) disposed on a side of the second gate away from the substrate.
Takahashi does not disclose a source-drain layer disposed on a side of the interlayer dielectric layer away from the substrate, the source-drain layer comprising a source, a drain, and a double-gate connection line, wherein the source is connected to the source region of the active layer; the drain is connected to the drain region of the active layer; and both ends of the double-gate connection line are connected to the first gate and the second gate, respectively.
Khang teaches in Figs. 14A-14B and related text a source-drain layer (DCE, CE, EL1; [0224]) disposed on a side of the interlayer dielectric layer (140, 150; [0200]) away from the substrate (110; [0200]), the source-drain layer comprising a source (DCE; [0221]), a drain (EL1; [0223]), and a double-gate connection line (CE; [0222]),
wherein the source is connected to the source region (S; [0221]) of the active layer (ACT; [0221]);
the drain is connected to the drain region (D; [0223]) of the active layer; and
both ends of the double-gate connection line are connected to the first gate (BGE; [0202] and [0222]) and the second gate (TGE; [0222]), respectively.
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a source-drain layer on a side of the interlayer dielectric layer away from the substrate, the source-drain layer comprising a source, a drain, and a double-gate connection line, wherein the source is connected to the source region of the active layer; the drain is connected to the drain region of the active layer; and both ends of the double-gate connection line are connected to the first gate and the second gate, respectively, as taught by Khang, in order to form the electrical contacts required to operate a double-gate thin film transistor.
Regarding claim 3, Takahashi in view of Khang disclose the second orthographic projection is within a range of the first orthographic projection (Takahashi: Fig. 10; [0140]).
Regarding claim 4, Takahashi in view of Khang disclose the driving backplane according to claim 3.
Takahashi does not disclose the source is connected to the source region of the active layer through a first via hole in the interlayer dielectric layer; the drain is connected to the drain region of the active layer through a second via hole in the interlayer dielectric layer; a first end of the dual-gate connection line is connected to the second gate through a third via hole in the interlayer dielectric layer, and a second end of the dual-gate connection line is connected to the first gate through a fourth via hole in the interlayer dielectric layer; the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection; and the third via hole is within the first sub-orthographic projection, and the fourth via hole is within the second sub-orthographic projection.
Khang teaches in Figs. 14A-14B and related text the source (DCE; [0221]) is connected to the source region (S; [0221]) of the active layer (ACT; [0221]) through a first via hole (H1; [0221]) in the interlayer dielectric layer (140, 150; [0200]);
the drain (EL1; [0223]) is connected to the drain region (D; [0223]) of the active layer through a second via hole (H2; [0223]) in the interlayer dielectric layer;
a first end of the dual-gate connection line (CE; [0222]) is connected to the second gate (TGE; [0222]) through a third via hole (H3; [0222]) in the interlayer dielectric layer, and a second end of the dual-gate connection line is connected to the first gate (BGE; [0202]) through a fourth via hole (H4; [0222]) in the interlayer dielectric layer;
the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection (Fig. 14B); and
the third via hole is within the first sub-orthographic projection, and the fourth via hole is within the second sub-orthographic projection (Fig. 14B).
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi in view of Khang with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the source to the source region of the active layer through a first via hole in the interlayer dielectric layer; to connect the drain to the drain region of the active layer through a second via hole in the interlayer dielectric layer; to connect a first end of the dual-gate connection line to the second gate through a third via hole in the interlayer dielectric layer, and to connect a second end of the dual-gate connection line to the first gate through a fourth via hole in the interlayer dielectric layer; wherein the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection; and the third via hole is within the first sub-orthographic projection, and the fourth via hole is within the second sub-orthographic projection, as taught by Khang, in order to form the electrical contacts required to operate a double-gate thin film transistor.
Regarding claim 5, Takahashi in view of Khang disclose the driving backplane according to claim 4.
Takahashi does not disclose the second sub-orthographic projection is spaced apart from at least one of the drain region and the source region.
Khang teaches in Figs. 13, 14A-14B and related text the second sub-orthographic projection is spaced apart from at least one of the drain region (D; [0223]) and the source region (S; [0221]).
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi in view of Khang with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second sub-orthographic projection to be spaced apart from at least one of the drain region and the source region, as taught by Khang, in order to avoid a parasitic capacitance between the first gate and at least one of the source and the drain.
Regarding claim 8, Takahashi discloses the method according to claim 7.
Takahashi does not disclose the forming of the active layer and the second gate comprises: forming the active layer, a conductive layer, and a photoresist layer sequentially stacked on a side of the first gate away from the substrate; patterning the photoresist layer to form a photoresist pattern, a third orthographic projection of the photoresist pattern on the active layer having a fifth side line and a sixth side line opposite to each other, at least a part of the first side line coinciding with the fifth side line, and/or at least a part of the second side line coinciding with the sixth side line; patterning the conductive layer with the photoresist pattern as a mask, to obtain the second gate; and conductorizing the active layer with the second gate as a mask, so that a conductorized part of the active layer forms the source region and the drain region, and a non-conductorized part of the active layer forms the channel region.
Khang teaches the forming of the active layer and the second gate comprises:
forming the active layer (ACT; [0171]), a conductive layer (TGEb; [0170]), and a photoresist layer (“photoresist composition”; [0170]) sequentially stacked on a side of the first gate (BGE; [0170]) away from the substrate (110; [0157]) (Fig. 9B);
patterning the photoresist layer to form a photoresist pattern (PR2; [0170]), a third orthographic projection of the photoresist pattern on the active layer having a fifth (right) side line and a sixth (left) side line opposite to each other, at least a part of the first side line (right side line of BGE) coinciding with the fifth side line, and/or at least a part of the second side line (left side line of BGE) coinciding with the sixth side line (Fig. 9B; [0170]-[0172]);
patterning the conductive layer with the photoresist pattern as a mask, to obtain the second gate (TGE; Figs. 10B-10C; [0173]); and
conductorizing the active layer with the second gate as a mask, so that a conductorized part of the active layer forms the source region (S; Fig. 11B; [0174]-[0176]) and the drain region (D; Fig. 11B; [0174]-[0176]), and a non-conductorized part of the active layer forms the channel region (CH; Fig. 11B; [0174]-[0176]).
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the active layer, a conductive layer, and a photoresist layer sequentially stacked on a side of the first gate away from the substrate; to pattern the photoresist layer to form a photoresist pattern, a third orthographic projection of the photoresist pattern on the active layer having a fifth side line and a sixth side line opposite to each other, at least a part of the first side line coinciding with the fifth side line, and/or at least a part of the second side line coinciding with the sixth side line; to pattern the conductive layer with the photoresist pattern as a mask, to obtain the second gate; and to conductorize the active layer with the second gate as a mask, so that a conductorized part of the active layer forms the source region and the drain region, and a non-conductorized part of the active layer forms the channel region, as taught by Khang, in order to enable to second gate to be self-aligned with the first gate, thereby simplifying the manufacturing process (Khang: [0173]).
Regarding claim 15, Takahashi discloses the display panel according to claim 14, wherein the driving backplane further comprises: an interlayer dielectric layer (10; Fig. 10; [0142] and [0145]) disposed on a side of the second gate away from the substrate.
Takahashi does not disclose a source-drain layer disposed on a side of the interlayer dielectric layer away from the substrate, the source-drain layer comprising a source, a drain, and a double-gate connection line, wherein the source is connected to the source region of the active layer; the drain is connected to the drain region of the active layer; and both ends of the double-gate connection line are connected to the first gate and the second gate, respectively.
Khang teaches in Figs. 14A-14B and related text a source-drain layer (DCE, CE, EL1; [0224]) disposed on a side of the interlayer dielectric layer (140, 150; [0200]) away from the substrate (110; [0200]), the source-drain layer comprising a source (DCE; [0221]), a drain (EL1; [0223]), and a double-gate connection line (CE; [0222]),
wherein the source is connected to the source region (S; [0221]) of the active layer (ACT; [0221]);
the drain is connected to the drain region (D; [0223]) of the active layer; and
both ends of the double-gate connection line are connected to the first gate (BGE; [0202] and [0222]) and the second gate (TGE; [0222]), respectively.
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a source-drain layer on a side of the interlayer dielectric layer away from the substrate, the source-drain layer comprising a source, a drain, and a double-gate connection line, wherein the source is connected to the source region of the active layer; the drain is connected to the drain region of the active layer; and both ends of the double-gate connection line are connected to the first gate and the second gate, respectively, as taught by Khang, in order to form the electrical contacts required to operate a double-gate thin film transistor.
Regarding claim 16, Takahashi in view of Khang disclose the second orthographic projection is within a range of the first orthographic projection (Takahashi: Fig. 10; [0140]).
Regarding claim 17, Takahashi in view of Khang disclose the display panel according to claim 16.
Takahashi does not disclose the source is connected to the source region of the active layer through a first via hole in the interlayer dielectric layer; the drain is connected to the drain region of the active layer through a second via hole in the interlayer dielectric layer; a first end of the dual-gate connection line is connected to the second gate through a third via hole in the interlayer dielectric layer, and a second end of the dual-gate connection line is connected to the first gate through a fourth via hole in the interlayer dielectric layer; the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection; and the third via hole is within the first sub-orthographic projection, and the fourth via hole is within the second sub-orthographic projection.
Khang teaches in Figs. 14A-14B and related text the source (DCE; [0221]) is connected to the source region (S; [0221]) of the active layer (ACT; [0221]) through a first via hole (H1; [0221]) in the interlayer dielectric layer (140, 150; [0200]);
the drain (EL1; [0223]) is connected to the drain region (D; [0223]) of the active layer through a second via hole (H2; [0223]) in the interlayer dielectric layer;
a first end of the dual-gate connection line (CE; [0222]) is connected to the second gate (TGE; [0222]) through a third via hole (H3; [0222]) in the interlayer dielectric layer, and a second end of the dual-gate connection line is connected to the first gate (BGE; [0202]) through a fourth via hole (H4; [0222]) in the interlayer dielectric layer;
the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection (Fig. 14B); and
the third via hole is within the first sub-orthographic projection, and the fourth via hole is within the second sub-orthographic projection (Fig. 14B).
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi in view of Khang with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the source to the source region of the active layer through a first via hole in the interlayer dielectric layer; to connect the drain to the drain region of the active layer through a second via hole in the interlayer dielectric layer; to connect a first end of the dual-gate connection line to the second gate through a third via hole in the interlayer dielectric layer, and to connect a second end of the dual-gate connection line to the first gate through a fourth via hole in the interlayer dielectric layer; wherein the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection; and the third via hole is within the first sub-orthographic projection, and the fourth via hole is within the second sub-orthographic projection, as taught by Khang, in order to form the electrical contacts required to operate a double-gate thin film transistor.
Regarding claim 18, Takahashi in view of Khang disclose the display panel according to claim 17.
Takahashi does not disclose the second sub-orthographic projection is spaced apart from at least one of the drain region and the source region.
Khang teaches in Figs. 13, 14A-14B and related text the second sub-orthographic projection is spaced apart from at least one of the drain region (D; [0223]) and the source region (S; [0221]).
Takahashi and Khang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi in view of Khang with the specified features of Khang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second sub-orthographic projection to be spaced apart from at least one of the drain region and the source region, as taught by Khang, in order to avoid a parasitic capacitance between the first gate and at least one of the source and the drain.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of US 2024/0014217 A1 (hereinafter “Huang”).
Regarding claim 10, Takahashi discloses the method according to claim 7.
Takahashi does not disclose after the forming of the active layer and the second gate, forming an interlayer dielectric layer and a source-drain layer sequentially stacked on a side of the second gate away from the substrate, and patterning the source-drain layer to form a source, a drain, and a double-gate connection line, wherein the source is connected to the source region of the active layer, the drain is connected to the drain region of the active layer, and both ends of the double-gate connection line are connected to the first gate and the second gate respectively.
Huang teaches after the forming of the active layer (22, 23; Fig. 4g; [0069]) and the second gate (24; Fig. 4f; [0068]),
forming an interlayer dielectric layer (13; Fig. 4h; [0071]) and a source-drain layer (“a metal thin film”; Fig. 4i; [0072]) sequentially stacked on a side of the second gate away from the substrate (10; [0057]), and patterning the source-drain layer to form a source (25; Fig. 4i; [0072]), a drain (26; Fig. 4i; [0072]), and a double-gate connection line (40; Fig. 4i; [0072]), wherein the source is connected to the source region (222; Figs. 4g, 4i; [0072]) of the active layer, the drain is connected to the drain region (223; Figs. 4g, 4i; [0072]) of the active layer, and both ends of the double-gate connection line are connected to the first gate (21; Fig. 4i; [0072]) and the second gate respectively.
Takahashi and Huang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, after the forming of the active layer and the second gate, to form an interlayer dielectric layer and a source-drain layer sequentially stacked on a side of the second gate away from the substrate, and to pattern the source-drain layer to form a source, a drain, and a double-gate connection line, wherein the source is connected to the source region of the active layer, the drain is connected to the drain region of the active layer, and both ends of the double-gate connection line are connected to the first gate and the second gate respectively, as taught by Huang, in order to form the electrical contacts required to operate a double-gate thin film transistor.
Regarding claim 11, Takahashi in view of Huang disclose the method according to claim 10.
Takahashi does not disclose the forming of the interlayer dielectric layer and the source-drain layer and the patterning of the source-drain layer comprise: forming the interlayer dielectric layer on the side of the second gate away from the substrate; forming, in the interlayer dielectric layer, a first via hole corresponding to the source region, a second via hole corresponding to the drain region, a third via hole corresponding to the second gate, and a fourth via hole, wherein the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection, the third via hole is formed within the first sub-orthographic-projection, and the fourth via hole is formed within the second sub-orthographic-projection; forming the source-drain layer on a side of the interlayer dielectric layer away from the substrate; and patterning the source-drain layer to form the source, the drain, and the double-gate connection line, wherein each of the source and the drain is independent of the double-gate connection line, the source is connected to the source region of the active layer through the first via hole, the drain is connected to the drain region of the active layer through the second via hole, a first end of the double-gate connection line is connected to the second gate through the third via hole, and a second end of the double-gate connection line is connected to the first gate through the fourth via hole.
Huang teaches the forming of the interlayer dielectric layer and the source-drain layer and the patterning of the source-drain layer comprise:
forming the interlayer dielectric layer (13) on the side of the second gate (24) away from the substrate (10) (Fig. 4h; [0057] and [0071]);
forming, in the interlayer dielectric layer, a first via hole (131, left) corresponding to the source region (222), a second via hole (131, right) corresponding to the drain region (223), a third via hole (132) corresponding to the second gate, and a fourth via hole (133) (Fig. 4h; [0054] and [0070]-[0071]), wherein the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection, the third via hole is formed within the first sub-orthographic-projection, and the fourth via hole is formed within the second sub-orthographic-projection;
forming the source-drain layer (“a metal thin film”) on a side of the interlayer dielectric layer away from the substrate (Fig. 4i; [0072]); and
patterning the source-drain layer to form the source (25), the drain (26), and the double-gate connection line (40), wherein each of the source and the drain is independent of the double-gate connection line, the source is connected to the source region of the active layer through the first via hole, the drain is connected to the drain region of the active layer through the second via hole, a first end of the double-gate connection line is connected to the second gate through the third via hole, and a second end of the double-gate connection line is connected to the first gate (21) through the fourth via hole (Fig. 4i; [0072]).
Takahashi and Huang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi in view of Huang with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the interlayer dielectric layer on the side of the second gate away from the substrate; to form, in the interlayer dielectric layer, a first via hole corresponding to the source region, a second via hole corresponding to the drain region, a third via hole corresponding to the second gate, and a fourth via hole, wherein the first orthographic projection comprises a first sub-orthographic-projection coinciding with the second orthographic projection and a second sub-orthographic-projection non-overlapping with the second orthographic projection, the third via hole is formed within the first sub-orthographic-projection, and the fourth via hole is formed within the second sub-orthographic-projection; to form the source-drain layer on a side of the interlayer dielectric layer away from the substrate; and to pattern the source-drain layer to form the source, the drain, and the double-gate connection line, wherein each of the source and the drain is independent of the double-gate connection line, the source is connected to the source region of the active layer through the first via hole, the drain is connected to the drain region of the active layer through the second via hole, a first end of the double-gate connection line is connected to the second gate through the third via hole, and a second end of the double-gate connection line is connected to the first gate through the fourth via hole, as taught by Huang, in order to form the electrical contacts required to operate a double-gate thin film transistor.
Regarding claim 12, Takahashi in view of Huang disclose the method according to claim 11.
Takahashi does not disclose the second sub-orthographic projection is spaced apart from at least one of the drain region and the source region.
Huang teaches in Figs. 4g, 4i and related text the second sub-orthographic projection is spaced apart from the source region (222; [0072]).
Takahashi and Huang are analogous art because they both are directed to double-gate thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takahashi in view of Huang with the specified features of Huang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second sub-orthographic projection to be spaced apart from the source region, as taught by Huang, in order to avoid a parasitic capacitance between the source and the double-gate connection line.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “placing a mask plate on the exposed photoresist layer, a hollow region of the mask plate overlapping with a partial area of the first photoresist part; exposing the photoresist layer from a side of the substrate provided with the mask plate, to obtain a first sub-photoresist part masked by the mask plate and a second sub-photoresist part corresponding to the hollow region; and developing the photoresist layer to remove the second photoresist part and the second sub-photoresist part, to obtain the photoresist pattern” as recited in claim 9.
Conclusion
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811