DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9, 11, 12, 15 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shintani (US 2013/0048938).
Regarding claim 1, Shintani discloses, in FIG. 2 and in related text, a variable resistance memory device comprising:
a pillar (22);
a resistance change layer (23) provided at a side surface of the pillar;
a semiconductor layer (25) provided at a side surface of the resistance change layer;
a gate insulating layer (26 between gate electrodes 27 and semiconductor layer 25, or 16 in FIG. 1) provided at a side surface of the semiconductor layer;
a plurality of isolating layers (26 between gate electrodes 27, or 18 in FIG. 1) and a plurality of gate electrodes (27) alternately arranged along a surface of the gate insulating layer; and
an internal resistance layer (24) between the resistance change layer and the semiconductor layer (see Shintani, [0012], [0014]),
wherein a resistance of the internal resistance layer (24) is greater than a resistance of the semiconductor layer (25) when the semiconductor layer comprises conductor characteristics (current passes through semiconductor layer 25 instead of internal resistance layer 24), and
wherein the resistance of the internal resistance layer (24) is less than the resistance of the semiconductor layer (25) when the semiconductor layer comprises insulator characteristics (current passes through internal resistance layer 24 instead of semiconductor layer 25) (see Shintani, [0016]).
Regarding claims 9 and 11, Shintani discloses the device of claim 1.
Shintani discloses wherein the internal resistance layer (24, SiSb) comprises a first element (Sb) at a first content (50% atomic percentage), and
wherein the resistance change layer (23, Ge2Sb2Te5) comprises the first element (Sb) at a second content (22% atomic percentage) different from the first content, wherein the first content of the first element in the internal resistance layer is greater than the second content of the first element in the resistance change layer (see Shintani, [0021]).
Regarding claim 12, Shintani discloses the device of claim 1.
Shintani discloses wherein the internal resistance layer (24, SiSb) further comprises a second element (Sb) at a third content (50% atomic percentage), and
wherein the resistance change layer (23, Ge2Sb2Te5) comprises the second element (Sb) at a fourth content (22% atomic percentage) different from the third content (see Shintani, [0021]).
Regarding claim 15, Shintani discloses the device of claim 1.
Shintani discloses wherein an operation voltage with an absolute value of 6 V or less is applied to the semiconductor layer (see Shintani, [0100]-[0101]).
Regarding claim 19, Shintani discloses the device of claim 1.
Shintani discloses wherein the pillar (22) comprises an insulating material (SiO2) (see Shintani, [0021])
Claims 1, 3-4, 6 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 2022/0140234).
Regarding claim 1, Han discloses, in FIGS. 9-11 and in related text, a variable resistance memory device comprising:
a pillar (280);
a resistance change layer (260) provided at a side surface of the pillar;
a semiconductor layer (240) provided at a side surface of the resistance change layer;
a gate insulating layer (230) provided at a side surface of the semiconductor layer;
a plurality of isolating layers (223a, b, …) and a plurality of gate electrodes (222a, b, …) alternately arranged along a surface of the gate insulating layer; and
an internal resistance layer (250) between the resistance change layer (260) and the semiconductor layer (240) (see Han, [0046], [0104], [0108], [0112]),
wherein a resistance of the internal resistance layer is greater than a resistance of the semiconductor layer when the semiconductor layer comprises conductor characteristics (when transistor TR4 is turned on, current passed through channel of TR4), and
wherein the resistance of the internal resistance layer is less than the resistance of the semiconductor layer when the semiconductor layer comprises insulator characteristics (when transistor TR3 is turned off, current does not pass through channel of TR3) (see Han, FIG. 12, [0112]-[0126]).
Regarding claim 3, Han discloses the device of claim 1.
Han discloses wherein an oxygen deficient (oxygen vacancies) ratio of the internal resistance layer (250) is less than an oxygen deficient ratio of the resistance change layer (260) (see Han, [0114], [0118]: internal resistance layer 250 has no oxygen vacancies; resistance change layer 260 has oxygen vacancies).
Regarding claim 4, Han discloses the device of claim 1.
Han discloses wherein an oxygen deficient (oxygen vacancies) ratio of the internal resistance layer (250) is less than 10% (see Han, [0114]: internal resistance layer 250 has no oxygen vacancies).
Regarding claim 6, Han discloses the device of claim 1.
Han discloses wherein the internal resistance layer (250) comprises an oxide comprising at least one of hafnium (Hf), aluminum (AI), silicon (Si), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vanadium (V), and molybdenum (Mo) (see Han, [0048], [0114]).
Regarding claim 19, Han discloses the device of claim 1.
Han discloses wherein the pillar (280) comprises an insulating material (oxide, nitride, or oxynitride) (see Han, [0120]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Han.
Regarding claim 5, Han discloses the device of claim 1.
Han discloses wherein an oxygen deficient (oxygen vacancies) ratio of the resistance change layer (260) is greater than 0% (see Han, [0118])
Han does not explicitly disclose wherein an oxygen deficient ratio of the resistance change layer is 10 % or more.
However, Han discloses that the oxygen deficient ratio determines resistance of the resistance change layer (see Han, [0064]-[0665]). In other words, the oxygen deficient ratio is a result effective variable for varying.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to have the claimed range/value through routine experimentation and optimization. Also, applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or otherwise critical. See MPEP § 2144.05
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Lin (US 2016/0336066).
Han discloses the device of claim 1.
Han discloses wherein the resistance change layer (260) comprises a metal oxide (see Han, [0117]).
Han does not explicitly disclose wherein the resistance change layer comprises an oxide comprising at least one of tantalum (Ta), titanium (Ti), stannum (Sn), chromium (Cr), and manganese (Mn).
Lin teaches wherein the resistance change layer comprises an oxide comprising at least one of tantalum (Ta), titanium (Ti), stannum (Sn), chromium (Cr), and manganese (Mn) (see Lin, [0062]).
Han and Lin are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Han to include wherein the resistance change layer comprises an oxide comprising at least one of tantalum (Ta), titanium (Ti), stannum (Sn), chromium (Cr), and manganese (Mn), as taught by Lin, because it is simple substitution of one known element for another to obtain predictable results (as resistive memory materials). See also, MPEP § 2143.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Lin (US 2016/0336066).
Regarding claim 8, Han discloses the device of claim 1.
Han discloses wherein the internal resistance layer (250) and the resistance change layer (260) comprise a metal oxide (see Han, [0117]).
Han does not explicitly disclose wherein the internal resistance layer and the resistance change layer comprise a ternary metal oxide.
Lin teaches that a resistance change layer comprises a metal oxide including a ternary metal oxide (see Lin, [0062]). Thus Lin teaches wherein the internal resistance layer and the resistance change layer comprise a ternary metal oxide.
Han and Lin are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Han to include wherein the internal resistance layer and the resistance change layer comprise a ternary metal oxide, as taught by Lin, because it is simple substitution of one known element for another to obtain predictable results (as resistive memory materials). See also, MPEP § 2143.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Han.
Regarding claim 16, Han discloses the device of claim 1.
Han discloses wherein a thickness of the internal resistance layer (250) is 1 nm to 5 nm (see Han, [0114]).
Han does not explicitly disclose wherein a thickness of the internal resistance layer is less than a thickness of the resistance change layer. Han does not explicitly disclose wherein a thickness of the resistance change layer is greater than 5 nm.
However, it is well known a thickness of the resistance change layer determines set and reset voltages of the memory device. See, for example, Kumar (US 2009/0272962), FIGS. 3A-3B and paragraph [0037]. In other words, the thickness of the resistance change layer is a result effective variable for varying.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to have the claimed range/value through routine experimentation and optimization. Also, applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or otherwise critical. See MPEP § 2144.05
Regarding claim 17, Han teaches the device of claim 16.
Han discloses wherein the thickness of the internal resistance layer is 1 nm to 10 nm (see discussion on claim 16 above).
Allowable Subject Matter
Claims 2, 10, 13-14, 18 and 20 are each objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of records, individually or in combination, do not disclose nor teach “wherein the resistance of the internal resistance layer is 0.35 MΩ to 600 MΩ” in combination with other limitations as recited in claim 2.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the first element comprises any one of hafnium (Hf), aluminum (AI), silicon (Si), niobium (Nb), lanthanum (La), zirconium (Zr), scandium (Sc), tungsten (W), vanadium (V), or molybdenum (Mo).” in combination with other limitations as recited in claim 10.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the second element comprises any one of tantalum (Ta), titanium (Ti), stannum (Sn), chromium (Cr), or manganese (Mn)” in combination with other limitations as recited in claim 13.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the third content of the second element in the internal resistance layer is less than the fourth content of the second element in the resistance change layer” in combination with other limitations as recited in claim 14.
The prior art of records, individually or in combination, do not disclose nor teach “wherein a pitch between the plurality of gate electrodes is 20 nm or less” in combination with other limitations as recited in claim 18.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the pillar comprises a conductive material.” in combination with other limitations as recited in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811