DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Device Embodiment 2, seen in Fig 4 and described in Para 0067-Para 0071 of the Specification, Device Embodiment 2 shows a third height c2 of the third sidewall S2b of the second gate electrode 32b may be greater than a fourth height d2 of the fourth sidewall S3b of the second gate electrode 32b adjacent to the recess region 42. These features are not observed Fig 3 nor in the Specification for Device Embodiment 1. In addition, these species are not obvious variants of each other based on the current record. there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/01/2025.
Applicant’s election without traverse of Device Embodiment 1 in the reply filed on 12/01/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Bhuwalka et al. (US 2020/0066725 A1, hereinafter Bhuwalka ‘725) in view of Ando et al. (US 10,490,559 B1, hereinafter Ando ‘559), in view of the following arguments.
With respect to Claim 1 Bhuwalka ‘725 discloses an integrated circuit semiconductor device (Fig 1-4) comprising:
a first transistor (TP, Fig 1, Para [0018]) on a substrate (101, Fig 2, Para [0023]), the first transistor (TP) includes a first gate electrode (GP, Fig 2, Para [0019]); and
a second transistor (TN, Fig 1, Para [0018]) on the substrate (101) and spaced apart from (disclosed in Fig 1 and Fig 2) the first transistor (TP), the second transistor (TN) includes a second gate electrode (GN, Fig 2, Para [0019]) that is directly connected to (Fig 2 and Para [0022] disclose GP and GN directly connected) the first gate electrode (GP), of the first gate electrode (GP) and the second gate electrode (GN) the first gate electrode (GP) and the second gate electrode (GN),
But Bhuwalka ‘725 fails to explicitly disclose a recess region that is recessed in surfaces of the first gate electrode and the second gate electrode and is arranged between the first gate electrode and the second gate electrode.
Nevertheless, in a similar field of endeavor, (Fig 1-13 of Ando ‘559), Ando ‘559 teaches a gate all around field effect transistor wherein manipulation of the electrode shape and work metal thickness with respect to the channel to control current flow through the devices. Col 1, Lines 23-25 of Ando ‘559. Applying this concept of manipulating electrode shape and thickness one of ordinary skill in the art would be motivated to manipulate the electrode thickness between devices of Bhuwalka ‘725 to be thin in order to provide better current control over the channels and reduce the size of the device. Ando ‘559 teaches the concept of conformally applying the gate metal connection between the two FET devices which results in a thin electrode line (1302, Fig 9 of Ando ‘559, Col 11, Lines 18-19) with a recessed area between the two FET devices (a recessed area between two FETs and over the electrode line 1302 is disclosed in Fig 13). Using the teachings of Ando ‘559, manipulating the amount, or thicknesses, of the gate electrodes between the devices and applying that in a conformal method would be motivating to a person of ordinary skill in the art, therefore, to enable better control current flow and to improve the manufacturing method through a well-known conformal deposition process.
As incorporated into Bhuwalka ‘725, the gate electrode thickness teachings of Ando ‘559 provides a recess region (area between SRAM FET devices and over line 1302 as shown in Fig 13 of Ando ‘559) that is recessed in surfaces of the first gate electrode (GP) and the second gate electrode (GN) and is arranged between (recess arranged between shown in Fig 13 of Ando ‘559) the first gate electrode (GP) and the second gate electrode (GN).
But the current embodiment of Bhuwalka ‘725 as modified by Ando ‘559 is silent on the width of the second and third width less than the first and fourth width, respectively, after the incorporation of the recess area (recess arranged between shown in Fig 13 of Ando ‘559) of Ando ‘559 in the device of Bhuwalka ‘559.
Nevertheless, Bhuwalka ‘725 further teaches (Fig 17 and Para [0063-0065]) a MBC-FET semiconductor device may have an asymmetrical gate (Para [0065] of Bhuwalka ‘725). One of ordinary skill in the art would be motivated to apply this teaching to the device of Bhuwalka ‘725, at least because, as Bhuwalka ‘725 teaches in Para [0063] reducing the length of the gate electrode to the side of the channel causes a higher operating speed in the device. Further, Bhuwalka ‘725 teaches the skewed gate contact (Bhuwalka ‘725 teaches in Para [0065] that the gate edge can skew from -3nm to +3nm) reduces parasitic capacitance. Incorporating the skewed gate structure further taught by Bhuwalka ‘725 into the device of Bhuwalka ‘725 as modified by Ando ‘559, Bhuwalka ‘725 as modified by Ando ‘559 then discloses the first width (D3) of a first sidewall (GP) of the first gate electrode (GP) is less than a second width (width from right side of channels CP to incorporated recess of Ando ‘559)(incorporating teaching of skewed gate structure of Bhuwalka ‘725 as shown above, the second width would be +3nm wider than the first width) of a second sidewall (left side of incorporated recess of Ando ‘559) of the first gate electrode (GP) adjacent to the recess region (recess of Ando ‘559 as incorporated in Bhuwalka ‘725) and opposite the first sidewall (GC3), and wherein a third width (D1, Fig 1, Para [0031]) of a third sidewall (GC1, Fig 2, Para [0031]) of the second gate electrode (GN) is less than a fourth width (width from left side of channels CN to incorporated recess of Ando ‘559)(incorporating teaching of skewed gate structure of Bhuwalka ‘725 as shown above, the fourth width would be +3nm wider than the third width) of a fourth sidewall (right side of incorporated recess of Ando ‘559) of the second gate electrode (GN) adjacent to the recess region (recess of Ando ‘559 as incorporated in Bhuwalka ‘725) and opposite the third sidewall (GC1).
With respect to Claim 2 Bhuwalka ‘725 as modified by Ando ‘559 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Bhuwalka ‘725 further discloses wherein the first transistor (TP) and the second transistor (TN) include multi-bridge channel transistors (Para [0065] discloses device of Bhuwalka ‘725 as an MBC-FET).
With respect to Claim 3 Bhuwalka ‘725 as modified by Ando ‘559 discloses all limitations of the integrated circuit semiconductor device of claim 2, and Bhuwalka ‘725 further discloses wherein:
the first transistor (TP) includes a first nanosheet stacking structure (CP, Fig 2, Para [0026]) including a plurality of first nanosheets (Fig 2 and Para [0026] disclose a plurality of nanosheets CP) spaced apart from each other (disclosed in Fig 2 and Para [0006]) in a direction (Z direction as shown in Fig 2) perpendicular (shown in Fig 2) to an upper surface (top of substrate 101 as shown in Fig 2) of the substrate (101), and a first gate insulating layer (GI on CP, Fig 2, Para [0023]) surrounding (disclosed in Fig 2) the plurality of first nanosheets (CP); and
the second transistor (TN) includes a second nanosheet stacking structure (CN, Fig 2, Para [0023]) including a plurality of second nanosheets (Fig 2 and Para [0026] disclose a plurality of nanosheets CN) spaced apart from each other (disclosed in Fig 2 and Para [0006]) in the direction (Z direction as shown in Fig 2) perpendicular (shown in Fig 2) to the upper surface (top of substrate 101 as shown in Fig 2) of the substrate (101), and a second gate insulating layer (GI on CN, Fig 2, Para [0023]) surrounding (disclosed in Fig 2) the plurality of second nanosheets (CN).
With respect to Claim 4 Bhuwalka ‘725 as modified by Ando ‘559 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Bhuwalka ‘725 further discloses wherein:
the first transistor (TP) is disposed on a first active fin (AP, Fig 2, Para [0019]) extending in a first direction (X direction as shown in Fig 1 and Fig 2) on the substrate (101); and
the second transistor (TN) is disposed on a second active fin (AN, Fig 2, Para [0019]) that is spaced apart (AN spaced apart from AP disclosed in Fig 1 and Fig 2) from the first active fin (AP) in a second direction perpendicular (Y direction as shown in Fig 1 and Fig 2) to the first direction (X direction) on the substrate (101), the second active fin (AN) extending in the first direction (X direction as shown in Fig 1 and Fig 2).
With respect to Claim 5 Bhuwalka ‘725 as modified by Ando ‘559 discloses all limitations of the integrated circuit semiconductor device of claim 4, and Bhuwalka ‘725 further discloses wherein the first width (D3), the second width (D4), the third width (D1), and the fourth width (D2) extend in the second direction (Y direction as shown in Fig 2).
With respect to Claim 6 Bhuwalka ‘725 as modified by Ando ‘559 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Bhuwalka ‘725 further discloses wherein the first gate electrode (GP) and the second gate electrode (GN) have a same body as each other (Fig 2 discloses GP and GN as integral to each other).
With respect to Claim 7 Bhuwalka ‘725 as modified by Ando ‘559 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Bhuwalka ‘725 further discloses wherein the first width (D3) is equal to the third width (D1)(Para [0032] discloses D1 and D3 as equal), and the second width (D4) is equal to the fourth width (D2) (Para [0032] discloses D1 and D3 as equal).
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898