DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "a first direction" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner interprets “a second direction” as “the second direction”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2023/0170349 hereinafter Liu ‘349) in view of Bhuwalka et al. (US 2020/0066725 A1, hereinafter Bhuwalka ‘725) in further view of Xu et al. (US 10,741,401 B1, hereinafter Xu ‘401), in further view of the following arguments.
PNG
media_image1.png
597
758
media_image1.png
Greyscale
PNG
media_image2.png
426
702
media_image2.png
Greyscale
With respect to Claim 1 Liu ‘349 discloses an integrated circuit semiconductor device (100 A, Fig. 1A-1B and Fig 16) comprising:
a first transistor (left transistor of 100A, as shown in annotated Fig 1A of Liu ‘349, Para [0019], hereinafter FT) on a substrate (102, Fig. 1A, Para [0019]), the first transistor (FT) includes a first gate electrode (108 of FT, as shown in annotated Fig 1A of Liu ‘349, Para [0019]); and
a second transistor (right transistor of 100A, as shown in annotated Fig 1A of Liu ‘349, Para [0019], hereinafter ST) on the substrate (102) and spaced apart from (Fig 1A discloses the left transistor of 100A is spaced apart from the right transistor of 100A) the first transistor (FT), the second transistor (ST) includes a second gate electrode (108 of ST, as shown in annotated Fig 1A of Liu ‘349, Para [0019]) that is directly connected to (Fig 1A and Para [0022] disclose gate electrode of the first transistor connected to the gate electrode of the second transistor by connection structure B) the first gate electrode (108 of FT), a recess region (area of 112 is a recess region as shown in annotated Fig 1A of Liu ‘349, hereinafter RR) that is recessed in surfaces (RR in surfaces of first and second gate electrodes disclosed in annotated Fig 1A of Liu ‘349 and Para [0021]) of the first gate electrode (108 of FT) and the second gate electrode (108 of ST) and is arranged between (RR between the first and second gate electrodes disclosed in annotated Fig 1A of Liu ‘349 and Para [0021]) the first gate electrode (108 of FT) and the second gate electrode (108 of ST),
wherein the integrated circuit semiconductor device (100A) further includes a plurality of gate electrodes (100A comprising first gate electrode (108 of FT) and second gate electrode (108 of ST) disclosed in annotated Fig 1A of Liu ‘349 and Para [0022]) including the first gate electrode (108 of FT) and the second gate electrode (108 of ST),
wherein a first width (first width shown in annotated Fig 1A of Liu ‘349) of a first sidewall (first sidewall shown in annotated Fig 1A of Liu ‘349) of the first gate electrode (108 of FT) a second width (second width shown in annotated Fig 1A of Liu ‘349) of a second sidewall (second sidewall shown in annotated Fig 1A of Liu ‘349) of the first gate electrode (108 of FT) adjacent to (disclosed in annotated Fig 1A of Liu ‘349) the recess region (RR) and opposite (shown in annotated Fig 1A of Liu ‘349) the first sidewall (first sidewall shown in annotated Fig 1A of Liu ‘349), and wherein a third width (third width shown in annotated Fig 1A of Liu ‘349) of a third sidewall (third sidewall shown in annotated Fig 1A of Liu ‘349) of the second gate electrode (108 of ST) a fourth width (second width shown in annotated Fig 1A of Liu ‘349) of a fourth sidewall (fourth sidewall shown in annotated Fig 1A of Liu ‘349) of the second gate electrode (108 of ST) adjacent to (disclosed in annotated Fig 1A of Liu ‘349) the recess region (RR) and opposite (shown in annotated Fig 1A of Liu ‘349) the third sidewall (third sidewall shown in annotated Fig 1A of Liu ‘349).
But Liu ‘349 fails to explicitly disclose a first width is less than a second width and a third width is less than a fourth width.
Nevertheless, in a related endeavor (Fig 1-4 and 17 of Bhuwalka ‘725) Bhuwalka ‘725 further teaches a FET semiconductor device may have an asymmetrical gate (Para [0065] of Bhuwalka ‘725). Bhuwalka ‘725 teaches wherein a first width (D3, Fig 2 of Bhuwalka ‘725, Para [0031]) of a first sidewall (GC3, Fig 2 of Bhuwalka ‘725, Para [0031]) of the first gate electrode (GP, Fig 2 of Bhuwalka ‘725, Para [0028]) is less than a second width (D4, Fig 2 of Bhuwalka ‘725, Para [0031]) of a second sidewall (left side of GC2, Fig 2 of Bhuwalka ‘725, Para [0028]) of the first gate electrode (GP) and opposite (disclosed in Fig 2 of Bhuwalka ‘725) the first sidewall (GC3), and wherein a third width (D1, Fig 2 of Bhuwalka ‘725, Para [0031]) of a third sidewall (GC1, Fig 2 of Bhuwalka ‘725, Para [0031]) of the second gate electrode (GN, Fig 2 of Bhuwalka ‘725, Para [0028]) is less than a fourth width (D2, Fig 2 of Bhuwalka ‘725, Para [0031]) of a fourth sidewall (right side of GC2, Fig 2 of Bhuwalka ‘725, Para [0028]) of the second gate electrode (GN) and opposite the third sidewall (GC1)( disclosed in Fig 2 of Bhuwalka ‘725).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Bhuwalka ‘725’s teaching of a first width is less than a second width and a third width is less than a fourth width into Liu ‘349’s device. Liu ‘349 discloses an integrated circuit device comprising a plurality of transistors with a connected first and second gate electrode and Liu ‘349 discloses in the embodiment, (Fig 16, Para [0063] of Liu ‘349) that the distance from channel regions and isolation structures can vary. Bhuwalka ‘725 teaches an integrated semiconductor device with gate electrodes of a first and second transistor connected and also teaches that the channel structures can have different dimensions from the sidewalls. The ordinary artisan would have been motivated to modify Liu ‘349 as modified by Xu ‘401 in the manner set forth above, at least, as Bhuwalka ‘725 teaches in Para [0063] reducing the length of the gate electrode to the side of the channel causes a higher operating speed in the device. Further, Bhuwalka ‘725 teaches the skewed gate contact (Bhuwalka ‘725 teaches in Para [0065] that the gate edge can skew from -3nm to +3nm) reduces parasitic capacitance.
As incorporated the teachings of Bhuwalka ‘725 of a first width (D3) is less than a second width (D4) and a third width (D1) is less than a fourth width (D2) would be used as the first width, second width, third width and fourth width of Liu ‘349.
Liu ‘349 as modified by Bhuwalka ‘725 fails to explicitly disclose and at least one of the plurality of gate electrodes is not connected to another of the plurality of gate electrodes in a second direction.
Nevertheless, in a related endeavor, (Fig 1A of Xu ‘401), Xu ‘401 teaches and at least one (rightmost 330, as shown in annotated Fig 1A of Xu ‘401, Col 7, Lines 6-15) of the plurality of gate electrodes (annotated Fig 1A of Xu ‘401 discloses a plurality of gate electrodes 330) is not connected to another of the plurality of gate electrodes (leftmost 330 as shown in annotated Fig 1A of Xu ‘401)(annotated Fig 1A of Xu ‘401 and Col 7, Lines 29-30 discloses gate cut structure 1402 separates a first and second transistor from a further transistor) in a second direction (y direction (horizontal) as shown in annotated Fig 1A of Xu ‘401).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Xu ‘401’s teaching of and at least one of the plurality of gate electrodes is not connected to another of the plurality of gate electrodes in a second direction into Liu ‘349 as modified by Bhuwalka ‘725’s device. Liu ‘349 as modified by Bhuwalka ‘725 teaches an integrated circuit device comprising a plurality of transistors with a connected first and second gate electrode over each respective transistor. Liu ‘349, in Para [0021] discloses isolation features that separate the gate electrodes of the first and second transistors from an additional device. Xu ‘401 also discloses an integrated circuit device comprising a plurality of transistors with a connected first and second gate electrode over each respective transistor with an isolation feature that separates the gate electrodes of the first and second transistor from an additional third transistor device and the gate electrode of the that transistor. The ordinary artisan would have been motivated to modify Liu ‘349 as modified by Bhuwalka ‘725 in the manner set forth above, at least, because as this dielectric isolation would allow additional transistors to be used for the adjacent device referenced by Liu ‘349 and the dielectric isolation would provide dielectric insulation between gate electrodes.
As incorporated, the teaching of at least one of the plurality of gate electrodes is not connected to another of the plurality of gate electrodes in a second direction of Xu ‘401 would be used so that isolation structure (114) of Liu ‘349 as modified by Bhuwalka ‘725 would separate the first and second electrode from an additional transistor electrode.
With respect to Claim 2 Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Bhuwalka ‘725 further discloses wherein the first transistor (TP, Fig 1 of Bhuwalka ‘725, Para [0018]) and the second transistor (TN, Fig 1 of Bhuwalka ‘725, Para [0018]) include multi-bridge channel transistors (Para [0065] discloses device of Bhuwalka ‘725 as an MBC-FET).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Bhuwalka ‘725’s further teaching of wherein the first transistor and the second transistor include multi-bridge channel transistors into Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401’s device. The ordinary artisan would have been motivated to modify Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 in the manner set forth above, at least, because as Bhuwalka ‘725 teaches in Para [0065] that using the large nanosheet width and asymmetric gate of a MBC-FET, parasitic capacitance can be reduced.
As incorporated, the teaching of Bhuwalka ‘725 of the semiconductor device as a multi-bridge channel transistor would be used as the semiconductor device of Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401.
With respect to Claim 3 Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 discloses all limitations of the integrated circuit semiconductor device of claim 2, and Liu ‘349 further discloses wherein:
the first transistor (FT) includes a first nanosheet stacking structure (106 of FT as shown in annotated Fig 1A of Liu ‘349, Para [0020 and 0015] discloses semiconductor structures 106 as nanosheets) including a plurality of first nanosheets (plurality of 106 of FT as shown in annotated Fig 1A of Liu ‘349) spaced apart from each other (disclosed in Fig 1A) in a direction (Z direction as shown in Fig 1A) perpendicular to an upper surface (upper surface of 102 as shown in annotated Fig 1A of Liu ‘349) of the substrate (102),; and
the second transistor (ST) includes a second nanosheet stacking structure (106 of ST as shown in annotated Fig 1A of Liu ‘349, Para [0020 and 0015] discloses semiconductor structures 106 as nanosheets) including a plurality of second nanosheets (plurality of 106 of ST as shown in annotated Fig 1A of Liu ‘349) spaced apart from each other (disclosed in Fig 1A) in the direction perpendicular (Z direction as shown in Fig 1A) to the upper surface (upper surface of 102 as shown in annotated Fig 1A of Liu ‘349) of the substrate (102),.
And Bhuwalka ‘725 further teaches and a first gate insulating layer (GI on CP, Fig 2 of Bhuwalka ‘725, Para [0023]) surrounding (disclosed in Fig 2 of Bhuwalka ‘725) the plurality of first nanosheets (CP, Fig 2 of Bhuwalka ‘725, Para [0023]) and a second gate insulating layer (GI on CN, Fig 2 of Bhuwalka ‘725, Para [0023]) surrounding (disclosed in Fig 2 of Bhuwalka ‘725) the plurality of second nanosheets (CN, Fig 2 of Bhuwalka ‘725, Para [0023]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Bhuwalka ‘725’s further teaching of a first gate insulating layer surrounding the plurality of first nanosheets and a second gate insulating layer surrounding the plurality of second nanosheets into Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401’s device. The ordinary artisan would have been motivated to further modify Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 in the manner set forth above, at least, because using a gate insulating layer over the nanosheet structures would protect the nanosheets from damage during the etching process to replace the sacrificial layers with the gate electrode material.
As incorporated, the gate insulating layers (GI) of Bhuwalka ‘725 would be used surrounding the plurality of first nanosheets (plurality of 106 of FT) and the plurality of second nanosheets (plurality of 106 of ST) of Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401’s device.
With respect to Claim 4 Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Liu ‘349 further discloses wherein:
the first transistor (FT) is disposed on a first fin (first fin of 102 as shown in annotated Fig 1A of Liu ‘349) extending in a first direction (X direction as shown in Fig 1A) on the substrate (102) and,
the second transistor (ST) is disposed on a second fin (second fin of 102 as shown in annotated Fig 1A of Liu ‘349) that is spaced apart (annotated Fig 1A of Liu ‘349 discloses first fin spaced from second fin) from the active fin (first fin of 102 as shown in annotated Fig 1A of Liu ‘349) in a second direction (Y direction)(Note Examiner’s interpretation of “a second direction” as “the second direction”) perpendicular to the first direction (x direction) on the substrate (102), the second fin (second fin of 102 as shown in annotated Fig 1A of Liu ‘349) extending in (disclosed in Fig 1A) the first direction (x direction).
But Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 fails to disclose the first and second fin as first and second active fins.
Nevertheless, Bhuwalka ‘725 further teaches a first active fin (AP, Fig 2 of Bhuwalka ‘725, Para [0019]) and a second active fin (AN, Fig 2 of Bhuwalka ‘725, Para [0019]) extending in the first direction (X direction as shown in Fig 1 and Fig 2 of Bhuwalka ‘725).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Bhuwalka ‘725’s further teaching of a first active fin and a second active fin extending in the first direction into Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401’s device. The ordinary artisan would have been motivated to modify Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 in the manner set forth above, at least, because as one of ordinary skill in the art would recognize, the active fin is critical to channel operation and current flow to the source and drain.
As incorporated, the first active fin (AP) and second active fin (AN) of Bhuwalka ‘725 would be used as the first fin (first fin of 102 as shown in annotated Fig 1A of Liu ‘349) and second fin (second fin of 102 as shown in annotated Fig 1A of Liu ‘349).
With respect to Claim 5 Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 discloses all limitations of the integrated circuit semiconductor device of claim 4, and Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 further discloses wherein the first width (D3 as incorporated above), the second width (D4 as incorporated above), the third width (D1 as incorporated above), and the fourth width (D2 as incorporated above) extend in the second direction (Y direction as shown in annotated Fig 1A of Liu ‘349).
With respect to Claim 6 Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Liu ‘349 further discloses wherein the first gate electrode (108 of FT) and the second gate electrode (108 of ST) have a same body as each other (Fig 1A and Para [0022] discloses first gate electrode and second gate electrode as integral to each other through connection structure B).
With respect to Claim 7 Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 discloses all limitations of the integrated circuit semiconductor device of claim 1, and Liu ‘349 as modified by Bhuwalka ‘725 and further modified by Xu ‘401 further discloses wherein the first width (D3 as incorporated above) is equal to the third width (D1 as incorporated above)(Para [0032] of Bhuwalka ‘725 discloses D1 and D3 as equal), and the second width (D4 as incorporated above) is equal to the fourth width (D2 as incorporated above) (Para [0032] of Bhuwalka ‘725 discloses D1 and D3 as equal).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights