DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/18/2024, 4/8/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 11 is objected to because of the following informalities:
In claim 11, line 9, the limitation “of the first fin” should be corrected into “or the first fin”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6 and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (2022/0130961).
Regarding claim 6, Wu discloses, in at least figures 2A-5, 7, and related text, an integrated circuit structure, comprising:
a first sub-fin structure (106 in 104 of PFET, [17], figures) beneath a first fin (106 above 106 in 104 of PFET, [17], figures);
a second sub-fin structure (106 in 104 of NFET, [17], figures) beneath a second fin (106 above 106 in 104 of NFET, [17], figures);
a first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures) at an end of the first fin (106 above 106 in 104 of PFET, [17], figures), the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures) having no dent or a shallower dent (142, [34]) therein; and
a second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures) at an end of the second fin (106 above 106 in 104 of NFET, [17], figures), the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures) having a deeper dent (132, [34]) therein.
Regarding claim 8, Wu discloses the integrated circuit structure of claim 6 as described above.
Wu further discloses, in at least figures 2A-5, 7, and related text, the deeper dent (132, [34]) has a saddle shape.
Regarding claim 9, Wu discloses the integrated circuit structure of claim 6 as described above.
Wu further discloses, in at least figures 2A-5, 7, and related text, the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures) is a P-type epitaxial source or drain structure, and the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures) is an N-type epitaxial source or drain structure.
Regarding claim 10, Wu discloses the integrated circuit structure of claim 6 as described above.
Wu further discloses, in at least figures 2A-5, 7, and related text, a first trench contact structure (144, [40]) on the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures); and
a second trench contact structure (134, [40]) on the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures), the second trench contact structure (134, [40]) having a vertical thickness greater than a vertical thickness of the first trench contact structure (144, [40]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (2022/0130961) in view of Trivedi (US 2022/0359697).
Regarding claim 1, Wu discloses, in at least figures 2A-5, 7, and related text, an integrated circuit structure, comprising:
a first sub-fin structure (106 in 104 of PFET, [17], figures);
a second sub-fin structure (106 in 104 of NFET, [17], figures);
a first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures), the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures) having no dent or a shallower dent (142, [34]) therein; and
a second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures), the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures) having a deeper dent (132, [34]) therein.
Wu does not explicitly disclose a first sub-fin structure beneath a first stack of nanowires; a second sub-fin structure beneath a second stack of nanowires; a first epitaxial source or drain structure at an end of the first stack of nanowire; a second epitaxial source or drain structure at an end of the second stack of nanowires.
Trivedi teaches, in at least figure 3I and related text, the device comprising a first sub-fin structure (303, [43]) beneath a first stack of nanowires (308B, [51]); a second sub-fin structure (303, [43]) beneath a second stack of nanowires (306B, [51]); a first epitaxial source or drain structure (346, [51]) at an end of the first stack of nanowire (308B, [51]); a second epitaxial source or drain structure (336, [51]) at an end of the second stack of nanowires (306B, [51]), for the purpose of providing state-of-the-art CMOS nanoribbon transistors utilize silicon (Si) nanoribbons to fabricate both NMOS and PMOS transistors ([25]).
Wu and Trivedi are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of Trivedi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Wu to have the first sub-fin structure beneath a first stack of nanowires; the second sub-fin structure beneath a second stack of nanowires; the first epitaxial source or drain structure at an end of the first stack of nanowire; the second epitaxial source or drain structure at an end of the second stack of nanowires, as taught by Trivedi, for the purpose of providing state-of-the-art CMOS nanoribbon transistors utilize silicon (Si) nanoribbons to fabricate both NMOS and PMOS transistors ([25], Trivedi).
Regarding claim 3, Wu in view of Trivedi discloses the integrated circuit structure of claim 1 as described above.
Wu further discloses, in at least figures 2A-5, 7, and related text, the deeper dent (132, [34]) has a saddle shape.
Regarding claim 4, Wu in view of Trivedi discloses the integrated circuit structure of claim 1 as described above.
Wu further discloses, in at least figures 2A-5, 7, and related text, the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures) is a P-type epitaxial source or drain structure, and the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures) is an N-type epitaxial source or drain structure.
Regarding claim 5, Wu in view of Trivedi discloses the integrated circuit structure of claim 1 as described above.
Wu further discloses, in at least figures 2A-5, 7, and related text, a first trench contact structure (144, [40]) on the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures); and
a second trench contact structure (134, [40]) on the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures), the second trench contact structure (134, [40]) having a vertical thickness greater than a vertical thickness of the first trench contact structure (144, [40]).
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Trivedi (US 2022/0359697) in view of Wu (2022/0130961).
Regarding claim 11, Trivedi discloses, in at least figures 3I, 10, and related text, a computing device, comprising:
a board (1002, [147]); and
a component (1004, [150]) coupled to the board, the component (1004, [150]) including an integrated circuit structure ([150]), comprising:
a first sub-fin structure (303, [43]) beneath a first stack of nanowires (308B, [51]) or a first fin;
a second sub-fin structure (303, [43]) beneath a second stack of nanowires (306B, [51]) or a second fin;
a first epitaxial source or drain structure (346, [51]) at an end of the first stack of nanowire (308B, [51]) of the first fin; and
a second epitaxial source or drain structure (336, [51]) at an end of the second stack of nanowires (306B, [51]) or the second fin.
Trivedi does not explicitly disclose the first epitaxial source or drain structure having no dent or a shallower dent therein; the second epitaxial source or drain structure having a deeper dent therein.
Wu teaches, in at least figures 2A-5, 7, and related text, the device comprising the first epitaxial source or drain structure (120 of PFET (140), [27], [33], figures) having no dent or a shallower dent (142, [34]) therein; the second epitaxial source or drain structure (120 of NFET (130), [27], [33], figures) having a deeper dent (132, [34]) therein, for the purpose of providing epitaxial structures that have optimized shape profiles for resistance and capacitance reduction ([14]).
Trivedi and Wu are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Trivedi with the specified features of Wu because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Trivedi to have the first epitaxial source or drain structure having no dent or a shallower dent therein; the second epitaxial source or drain structure having a deeper dent therein, as taught by Wu, for the purpose of providing epitaxial structures that have optimized shape profiles for resistance and capacitance reduction ([14], Wu).
Regarding claim 12, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, the first (308B, [51]) and second (306B, [51]) stacks of nanowires.
Regarding claim 13, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Wu further teaches, in at least figures 2A-5, 7, and related text, the first (106 above 106 in 104 of PFET, [17], figures) and second (106 above 106 in 104 of NFET, [17], figures) fins.
Regarding claim 14, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, a memory ([148]) coupled to the board (1002, [147]).
Regarding claim 15, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, a communication chip (1006, [151]) coupled to the board (1002, [147]).
Regarding claim 16, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, a battery ([148]) coupled to the board (1002, [147]).
Regarding claim 17, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, a camera ([148]) coupled to the board (1002, [147]).
Regarding claim 18, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, a display ([148]) coupled to the board (1002, [147]).
Regarding claim 19, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, the component (1004, [150]) is a packaged integrated circuit die ([150]).
Regarding claim 20, Trivedi in view of Wu discloses the computing device of claim 11 as described above.
Trivedi further discloses, in at least figures 3I, 10, and related text, the component is selected from the group consisting of a processor (1004, [150]), a communications chip (1006, [151]), and a digital signal processor ([148]).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 2 that recite "the shallower dent is less than 5% of a vertical thickness of the first epitaxial source or drain structure, and wherein the deeper dent is greater than 10% of a vertical thickness of the second epitaxial source or drain structure" in combination with other elements of the base claims 1 and 2.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 6 and 7 that recite "the shallower dent is less than 5% of a vertical thickness of the first epitaxial source or drain structure, and wherein the deeper dent is greater than 10% of a vertical thickness of the second epitaxial source or drain structure" in combination with other elements of the base claims 6 and 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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