DETAILED ACTION
This action is responsive to the amendment received on 03/05/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in REPUBLIC OF KOREA on 06/30/2022.
Terminal Disclaimer
The terminal disclaimer filed on March 5, 2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of any patent granted on Application Number 18215112 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”).
Regarding Claim 1. Chu discloses A display apparatus (#1, Figure 1, display apparatus wherein Figures 2-5 are views of an equivalent circuit of one of the pixels, a top down view of the circuit, a top down view of the semiconductor layer, and a cross-sectional view of the circuit, respectively, according to [0031]-[0035), comprising:
a substrate (#101, Figure 5, substrate) having a display area (#DA, Figure 1, display area) and a non-display area (#PA, Figure 1, peripheral area);
a first transistor (#T3, Figure 5, compensation thin-film transistor) including:
a first semiconductor layer (#A3, Figure 5, compensation semiconductor layer) on the substrate (Figure 5 #A3 is on #101, where “on” does not require direct contact according to [0033] of the instant application), the first semiconductor layer including oxide semiconductor (#1130, Figure 4, [0095], active layer portions of each respective transistor, such as #T3, may include an oxide semiconductor),
at least a part of a first insulating layer (#112, Figure 5, second insulating layer) on the first semiconductor layer (Figure 5, a portion of #112 in the middle portion of the figure is in direct contact with #A3),
a first gate electrode (#G3, Figure 5, compensation gate electrode) on the part of the first insulating layer (Figure 5, #G3 is directly on the part of #112 which is on #A3) and a second insulating layer (#111, Figure 5, first insulating layer) on the first gate electrode (Figure 5, #111 is on #G3 as being part of the same device since “on” does not require direct contact according to [0033] of the instant application and may include intervening elements);
a second transistor (#T4, Figure 5, first initialization thin-film transistor) including
a second semiconductor layer (#A4, Figure 5, first initialization semiconductor layer) on the substrate (Figure 5 #A4 is on #101, where “on” does not require direct contact according to [0033] of the instant application) and
a second gate electrode (#G4, Figure 5, first initialization gate electrode) on the first insulating layer (Figure 5, #G4 is directly on #112); and
a third transistor (#T1, Figure 5, driving thin-film transistor) including:
a third semiconductor layer (#A1, Figure 5, driving semiconductor layer) on the substrate (Figure 5 #A1 is on #101, where “on” does not require direct contact according to [0033] of the instant application), the third semiconductor layer including oxide semiconductor (#1130, Figure 4, [0095], active layer portions of each respective transistor, such as #T1, may include an oxide semiconductor),
at least another part of the first insulating layer on the third semiconductor layer (Figure 5, a portion of #112 in the left portion of the figure is on #A1 where “on” does not require direct contact according to [0033] of the instant application),
at least a part of the second insulating layer on the first insulating layer (Figure 5, at least a portion of #111 is in direct contact with #112), and
a third gate electrode (#G1, Figure 5, driving gate electrode) on the part of the second insulating layer (Figure 5, #G1 is on the entirety of #111, necessarily including the part of #111 that is on #112, as “on” does not require direct contact according to [0033] of the instant application), wherein a top surface of the second insulating layer is disposed below the third gate electrode (Figure 5, a top surface of #111 is disposed below #G1).
Regarding Claim 2. Chu discloses The display apparatus of claim 1, wherein the first insulating layer is disposed on the second semiconductor layer (Figure 5, #112 is directly on #A4), and the second insulating layer is disposed on the second gate electrode (Figure 5, #111 is on #G4, where as being part of the same device since “on” does not require direct contact according to [0033] of the instant application).
Regarding Claim 3. Chu discloses The display apparatus of claim 1, wherein a distance between the first semiconductor layer (#A3) and the first gate electrode (#G3) is a same distance as a distance between the second semiconductor layer (#A4) and the second gate electrode (#G4) (Figure 5, the vertical distance between #A3 and #G3 is the same as the vertical distance between #A4 and #G4, that distance being the thickness t2 of #112).
Regarding Claim 4. Chu discloses The display apparatus of claim 1, wherein a distance between the first semiconductor layer (#A3) and the first gate electrode (#G3) is smaller than a distance between the third semiconductor layer (#A1) and the third gate electrode (#G1) (Figure 5, the vertical distance between #A3 and #G3, thickness t2 of #112, is smaller than the vertical distance between #A1 and #G1, that distance being the thickness t2 of #112 plus the thickness t1 of #111).
Regarding Claim 5. Chu discloses The display apparatus of claim 1, wherein a distance between the second semiconductor layer (#A4) and the second gate electrode (#G4) is smaller than a distance between the third semiconductor layer (#A1) and the third gate electrode (#G1) (Figure 5, the vertical distance between #A4 and #G4, thickness t2 of #112, is smaller than the vertical distance between #A1 and #G1, that distance being the thickness t2 of #112 plus the thickness t1 of #111).
Regarding Claim 6. Chu discloses The display apparatus of claim 1, wherein a capacitance between the third semiconductor layer (#A1) and the third gate electrode (#G1) is smaller than a capacitance between the first semiconductor layer (#A3) and the first gate electrode (#G3), and wherein a capacitance between the third semiconductor layer (#A1) and the third gate electrode (#G1) is smaller than a capacitance between the second semiconductor layer (#A4) and the second gate electrode (#G4) (Figure 5, [0127], the thickness of the insulating layer between #G3/#G4 and #A3/#A4 is made thinner by the removal of #111 such that the capacitance between #G1 and #A1 is smaller than the capacitances between both of #G3/#G4 and #A3/#A4 because the thicker insulation (#111 and #112) between #G1 and #A1 increases the distance between the plates and reduces capacitance).
Regarding Claim 7. Chu discloses The display apparatus of claim 1, wherein the first gate electrode (#G3) is disposed in a different layer from the third gate electrode (#G1) (Figure 5, #G1 is disposed in a different vertical layer which is higher than a vertical layer in which #G3 is disposed wherein #113 may be interpreted as having a plurality of vertical layers in the thickness direction), and
wherein the second gate electrode (#G4) is disposed in a different layer from the third gate electrode (#G1) (Figure 5, #G1 is disposed in a different vertical layer which is higher than a vertical layer in which #G4 is disposed wherein #113 may be interpreted as having a plurality of vertical layers in the thickness direction).
Regarding Claim 10. Chu discloses The display apparatus of claim 1, further comprising (Examiner note: [0096] of Chu states that “Each source region and each drain region may respectively correspond to a source electrode and a drain electrode . . . the terms “source region” and “drain region” are used instead of the “source electrode” or the “drain electrode”, i.e. each drain and source region is interpreted to include a drain and source electrode):
a first source electrode (#S3, Figure 5, compensation source region) and a first drain electrode (#D3, Figure 5, compensation drain region) on the first gate electrode (Figure 5, #S3 and #D3 are on #G3 where “on does not require direct contact according to [0033] of the instant application);
a second source electrode (#S4, Figure 5, initialization source region) and a second drain electrode (#D4, Figure 5, initialization drain region) on the second gate electrode (Figure 5, #S4 and #D4 are on #G4 where “on does not require direct contact according to [0033] of the instant application); and
a third source electrode (#S1, Figure 5, driving source region) and a third drain electrode (#D1, Figure 5, driving drain region) on the third gate electrode (Figure 5, #S1 and #D1 are on #G1 where “on does not require direct contact according to [0033] of the instant application),
wherein the first source electrode (#S1) is connected to a fourth gate electrode (#G2, Figure 3, switching gate electrode which is both indirectly physically and indirectly electrically connected to #S1 through the circuit structure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”) as applied to claim 1 above, and further in view of US 12,484,378 B1; Chang et al.; 11/2025; (“Chang”).
Regarding Claim 8. Chu discloses The display apparatus of claim 1.
Chu does not disclose a fourth gate electrode under the first semiconductor layer;
a fifth gate electrode under the second semiconductor layer; and
a sixth gate electrode under the third semiconductor layer.
However, Chang teaches a driver circuit (Figure 6) with a side view provided in Figure 3 wherein all of the transistors (#T1-#T7) are dual gate transistors with oxide semiconductor active layers and top gate conductors over the active layers and bottom gate conductors under the active layers (column 8, line 66 through column 9, line 27 and Figures 3 and 6).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a fourth, fifth, and sixth gate electrode under the first, second, and third semiconductor layers, respectively, as was done for all transistors in the driving circuit of Chang, in the device of Chu since the inclusion of dual gate transistors including bottom gates provides for enhanced control flexibility (see column 1, lines 43-62 and column 11, lines 1-16 of Chang)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”) as applied to claim 1 above, and further in view of US 2024/0055535 A1; Cheng et al.; 02/2024; (“Cheng”).
Regarding Claim 11. Chu discloses The display apparatus of claim 1.
Chu does not disclose that the non-display area includes a gate driving part, further comprising a fourth transistor in the gate driving part and including a fourth semiconductor layer, wherein the fourth semiconductor layer includes a polycrystalline semiconductor material. However, Chu does teach that the non-display area (peripheral area) may include a driving integrated circuit ([0066]).
Cheng teaches a gate driving circuit (Figure 7, [0024]) which may be part of a gate driving unit (#60, Figure 5) located in the peripheral region (#200b, Figure 5) of a display panel (#200, Figure 5), wherein the gate driving part comprises a plurality of transistors (#NT1-#NT3) which include a semiconductor layer which includes a polycrystalline semiconductor material ([0052], “first thin film transistor NT1 to the thirteenth thin film transistor NT13 all can be the above-mentioned thin film transistors comprising the first channel 1021 and the second channel 1041. . . low-temperature polycrystalline silicon thin film transistor with dual channels is applied to the gate driving circuit”).
Since Chu appears to be silent regarding the details of the gate driving circuitry structure, this would motivate one of ordinary skill to seek out teachings such as Cheng in order to practice the invention of Chu. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider providing the TFT including a polycrystalline silicon active layer in the gate driving circuitry from Cheng since “when the low-temperature polycrystalline silicon thin film transistor with dual channels is applied to the gate driving circuit, the problem that the channel close to the drain of the thin film transistor is subjected to large bias stress is improved, and the stability of the gate driving circuit is improved” as taught by Cheng in [0052].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”) as applied to claim 1 above, and further in view of US 2024/0040882 A1; Zhou, Jing; 02/2024; (“Zhou”).
Regarding Claim 12. Chu discloses The display apparatus of claim 1, further comprising:
an emitting device (#OLED, Figure 5, organic light-emitting diode) in the display area ([0065], “Display elements may be positioned or disposed in the display area DA. In an embodiment, each display element may be an organic light-emitting diode (OLED)”), and an encapsulation part on the emitting element (Figure 5, [0121], “encapsulation layer including a first inorganic layer, a second inorganic layer, and an organic layer therebetween may be positioned or disposed on the common electrode 230”, i.e. the encapsulation layer is on the common electrode of the light emitting element).
Chu does not disclose a touch part on the encapsulation part; and a color filter layer on the touch part or between the touch part and the encapsulation part.
However, Zhou teaches a display panel (Figure 3, [0037]) including a touch part (#30, touch electrode layer) on an encapsulation part (#20 thin film encapsulation layer) that is located on a light emitting device (#1011, light emitting pixel unit), and a color filter layer (#40, color filter layer) on the touch part or between the touch part and the encapsulation layer (3, #40 is located on #30).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the touch part and the color filter layer of Zhou in the display device of Chu in order to “realize a touch function” ([0081] of Zhou), and “prevent light leakage”, “reduce reflectivity” and “improve light output rate of the OLED display panel” ([0003)-[0004] of Zhou).
Allowable Subject Matter
Claim(s) 9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art, either alone or in combination, teaches “a distance between the fourth gate electrode and the first semiconductor layer is smaller than a distance between the fifth gate electrode and the second semiconductor layer, and wherein a distance between the fourth gate electrode and the first semiconductor layer is smaller than a distance between the sixth gate electrode and the third semiconductor layer” as required in claim 9 and in combination with all of the other limitations of the claim and those it depends on.
Regarding Claim 9. Chu in view of Chang discloses The display apparatus of claim 8 (as described above).
Chu in view of Chang do not disclose a distance between the fourth gate electrode and the first semiconductor layer is smaller than a distance between the fifth gate electrode and the second semiconductor layer, and wherein a distance between the fourth gate electrode and the first semiconductor layer is smaller than a distance between the sixth gate electrode and the third semiconductor layer. This is not interpreted by the examiner as an obvious rearrangement of parts (MPEP 2144.04.VI.C) or change in size/proportion (MPEP 2144.04.IV.A) as the relative distances of the respective gate electrodes from their respective active layers will modify device capacitance and operational parameters relative to one another (see [0196]-[0204] of the instant application). Claim 9 is therefore interpreted as containing allowable subject matter.
Response to Arguments/Amendments
Applicant’s amendments to claim 3 and corresponding remarks, see page 11 of the remarks, filed 03/05/2026, with respect to the objection to claim 3 have been fully considered. The objection to claim 3 has been withdrawn.
Applicant’s amendments to claims 1 and 10 and corresponding remarks, see page 11 of the remarks, filed 03/05/2026, with respect to the 35 U.S.C. 112(b) rejections of claims 1-12 have been fully considered. The 35 U.S.C. 112(b) rejections of claims 1-12 have been withdrawn.
Applicant’s amendments to claim 1 and corresponding arguments, see pages 11-12 of the remarks, filed 03/05/2026, with respect to the 35 U.S.C. 102 and 35 U.S.C. 103 rejections of claims 1-12 have been fully considered but are not found persuasive. Applicant argues that Chu (US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”)) does not disclose the amended limitation of “a third gate electrode on the part of the second insulating layer, wherein a top surface of the second insulating layer is disposed below the third gate electrode”. While applicant is correct under the original interpretation where #113 (third insulating layer) was interpreted to read on the second insulating layer, in view of the amendments, a new interpretation of Chu has been made. Chu discloses a first gate electrode (#G3, Figure 5, compensation gate electrode) on the part of the first insulating layer (Figure 5, #G3 is directly on the part of #112 which is on #A3) and a second insulating layer (#111, Figure 5, first insulating layer) on the first gate electrode (Figure 5, #111 is on #G3 as being part of the same device since “on” does not require direct contact according to [0033] of the instant application and may include intervening elements); . . . at least a part of the second insulating layer on the first insulating layer (Figure 5, at least a portion of #111 is in direct contact with #112), and a third gate electrode (#G1, Figure 5, driving gate electrode) on the part of the second insulating layer (Figure 5, #G1 is on the entirety of #111, necessarily including the part of #111 that is on #112, as “on” does not require direct contact according to [0033] of the instant application), wherein a top surface of the second insulating layer is disposed below the third gate electrode (Figure 5, a top surface of #111 is disposed below #G1). Therefore, it is the examiner’s interpretation the Chu does disclose all of the limitations of amended claim 1.
Claim(s) 1-7 and 10 stand(s) rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”).
Claim(s) 8 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”) as applied to claim 1 above, and further in view of US 12,484,378 B1; Chang et al.; 11/2025; (“Chang”).
Claim(s) 11 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”) as applied to claim 1 above, and further in view of US 2024/0055535 A1; Cheng et al.; 02/2024; (“Cheng”).
Claim(s) 12 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0399420 A1; Chu et al.; 12/2022; (“Chu”) as applied to claim 1 above, and further in view of US 2024/0040882 A1; Zhou, Jing; 02/2024; (“Zhou”).
Applicant’s filing of a terminal disclaimer and corresponding remarks, see page 12 of the remarks, filed 03/05/2026, with respect to the double patenting rejection of claims 1-5, 8, and 10-12 have been fully considered. The double patenting rejection of claims 1-5, 8, and 10-12 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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