DETAILED ACTION
This action is responsive to the following communications: the Application filed on June 28, 2023 and the Information Disclosure Statements filed on June 28, 2023; February 15, 2024; November 8, 2024; June 2, 2025 and September 10, 2025.
Claims 1-20 are pending. Claims 1 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDSs) filed on June 28, 2023; February 15, 2024; November 8, 2024; June 2, 2025 and September 10, 2025. These IDSs have been considered.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0023], line 3, “anther processing circuit” should be --another processing circuit--.
In paragraph [0028], line 11, “weighted capacitor array 122” should be --weighted capacitor array 112--.
Appropriate correction is required.
Claim Objections
Claim 4 is objected to because of the following informalities:
In claim 4, line 3, “memory cells in the memory array” should be --memory cells in the first memory array--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-8, 12 and 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 7, the claim recites “a second charge-domain passive summation circuit, arranged to generate a second analog computation result of a second input received by the second processing circuit”. There is insufficient antecedent basis for the limitation “the second processing circuit” in the claim. Neither claim 7 nor claim 1, on which claim 7 depends, previously introduces “a second processing circuit”. Claim 8 is rejected for the same reason because claim 8 depends on and incorporates the indefinite limitation of claim 7.
With respect to claim 12, the claim recites “the plurality of memory cells comprise a plurality of first memory cells arranged to store a plurality of bits of the first target weight”. There is insufficient antecedent basis for the limitation “the plurality of memory cells” in the claim. Neither claim 12 nor claim 1, on which claim 12 depends, previously introduces “a plurality of memory cells”.
With respect to claim 15, the claim recites “wherein the CIM circuit is further involved in calibration of the first external analog buffer and the second external analog buffer”. The phrase “is further involved in calibration” does not define with reasonable clarity the function, operation, or structural relationship required of the CIM circuit. In particular, it is unclear whether the limitation requires the CIM circuit to perform the calibration; control the calibration; measure an error used for calibration; provide signals to a separate calibration circuit; or merely receive signals from external analog buffers that are calibrated by another device. A person of ordinary skill in the art cannot determine the degree or type of participation by the CIM circuit necessary to satisfy the limitation. Therefore, the metes and bounds of claim 15 are unclear. Claims 16-18 are rejected for the same reason because claims 16-18 depend on and incorporate the indefinite limitation of claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
Claims 1-2, 4-14 and 19-20 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by Wang et al. (US 20220334801).
Regarding independent claim 1, Wang et al. disclose a compute-in-memory (CIM) circuit [Fig. 3A: 320] comprising:
a first processing circuit [see Fig. 3A, the analog compute array 320 includes a plurality of CiM arrays 322, 324, 326, 328, 330, 332, para. 41], comprising:
a first data-selection circuit [Fig. 3A: 322, para. 42], comprising:
a first memory array, arranged to store a plurality of candidate weights [see Fig. 3A, the first CiM array 322 includes p banks that comprise memory cells represented as squares. Each of the p banks stores a q-bit weight in memory cells (e.g., each memory cell stores one bit of the q-bit weight), para. 42]; and
a first selection circuit, arranged to select a first target weight from the plurality of candidate weights stored in the first memory array [see Fig. 3A, a C-2C ladder 312 of the first CiM array 322 receives an input signal IAi. One of the p banks is connected to the C-2C ladder 312 to provide a weight to the C-2C ladder 312, para. 42]; and
a first charge-domain passive summation circuit [Fig. 3A: 312], arranged to generate a first analog computation result of a first input received by the first processing circuit [see Fig. 3A, the first CiM array 322 executes an operation based on the weight and the input signal IAi to generate an output signal OA2, para. 42] and the first target weight stored in the first memory array through a first weighted capacitor array integrated with the first memory array [one of the p memory banks is connected to the C-2C ladder 312 to provide a weight to the C-2C ladder 312, para. 42. See Fig. 6, the C-2C ladder 600 is a capacitor network having C and 2C capacitors arranged in binary weighted branches. Each branch represents a different weight bit and the ladder output becomes the product of input activation IA and weight W, para. 51-53. See Fig. 7, the SRAM cells 616 are connected to the C-2C ladder 618 via switching elements and inverters, para. 55].
Regarding claim 2, Wang et al. disclose wherein the plurality of candidate weights are weights of a neural network [the weights are obtained during a neural network training process and preloaded in the network, para. 25].
Regarding claim 4, Wang et al. disclose wherein the first target weight comprises a plurality of bits, and the plurality of bits are stored in a plurality of memory cells in the memory array, respectively [he plurality of memory cells 104 may store weights. The first memory cells 104a may store a first weight (e.g., various memory elements store different bits of the first weight), the second memory cells 104b may store a second weight (e.g., various memory elements store different bits of the second weight) and the N memory cells 104n may store an N weight (e.g., various memory elements store different bits of the N weight), para. 24].
Regarding claim 5, Wang et al. disclose wherein the first weighted capacitor array comprises a plurality of capacitors [see Fig. 6, the C-2C ladder 600 as a series of capacitors C and 2C arranged in branches, para. 51-53]; and the first selection circuit is further arranged to selectively apply the first input to the plurality of capacitors according to the plurality of bits, respectively [see Fig. 7, the analog input IA is applied to the C-2C ladder and transmission gate switches are controlled by corresponding stored weight signals, para. 55].
Regarding claim 6, Wang et al. disclose wherein the first selection circuit is further arranged to control transmission of the first input by referring to the plurality of bits concurrently [see Fig. 7, the analog input IA is applied to the C-2C ladder and transmission gate switches are controlled by corresponding stored weight signals, para. 55].
Regarding claim 7, Wang et al. disclose further comprising:
a second data-selection circuit, comprising:
a second memory array, arranged to store the plurality of candidate weights; and
a second selection circuit, arranged to select a second target weight from the plurality of candidate weights stored in the second memory array; and
a second charge-domain passive summation circuit, arranged to generate a second analog computation result of a second input received by the second processing circuit and the second target weight stored in the second memory array through a second weighted capacitor array integrated with the second memory array [see Fig. 3A: the analog compute array 320 includes a plurality of CiM arrays 322, 324, 326, 328, 330, 332. While the first CiM array 322 is discussed, it will be understood that the other CiM arrays 324, 326, 328, 330, 332 may be similarly formed, para. 41];
wherein the first weighted capacitor array comprises a plurality of first capacitors each having a first plate and a second plate; the second weighted capacitor array comprises a plurality of second capacitors each having a first plate and a second plate; and first plates of the plurality of first capacitors are connected to first plates of the second capacitors [see Fig. 6, the C-2C ladder 600 includes a series of capacitors C segmented into branches. Each branch contains a switch and a capacitor with one unit capacitance C. A serial capacitor, with a capacitance of two unit capacitance 2C, is inserted between each of two branches, para. 52].
Regarding claim 8, Wang et al. disclose wherein the plurality of candidate weights are weights of a neural network [the weights are obtained during a neural network training process and preloaded in the network, para. 25].
Regarding claim 9, Wang et al. disclose wherein the first weighted capacitor array of the first charge-domain passive summation circuit is shared among the plurality of candidate weights stored in the first memory array [Each of the p banks stores a q-bit weight in memory cells (e.g., each memory cell stores one bit of the q-bit weight). A C-2C ladder 312 of the first CiM array 322 receives an input signal IAi. One of the p banks is connected to the C-2C ladder 312 to provide a weight to the C-2C ladder 312, para. 42. Multiple SRAM cells to share the same C-2C ladder which is enlarged, para. 63].
Regarding claim 10, Wang et al. disclose wherein the first memory array comprises a plurality of memory cell lines arranged to store the plurality of candidate weights, respectively [groups of memory cells storing the different bits of a a particular weight, para. 24]; the first selection circuit comprises:
a plurality of global selection switches, corresponding to the plurality of memory cell lines, respectively [the controller 106 controls the switching elements 108 to selectively electrically connect the plurality of memory cells 104 to the MAC 110, para. 27, wherein each of the plurality of global selection switches has one terminal that is arranged to receive the first input [The controller 106 may transmit control signals to the switching elements 108 over a local read word line, para. 27], and one of the plurality of global selection switches that corresponds to a memory cell line in which the first target weight is stored is switched on [only one of the first-N memory cells 104a-104n may be electrically connected to the MAC 110. For example, the controller 106 may control the switching elements 108 to selectively connect the plurality of memory cells 104 to the MAC 110, para. 28].
Regarding claim 11, Wang et al. disclose wherein the rest of the plurality of global selection switches are switched off [while the first weight group is connected, the second through N groups are simultaneously disconnected, para. 28-30].
Regarding claim 12, Wang et al. disclose wherein the plurality of memory cells comprise a plurality of first memory cells arranged to store a plurality of bits of the first target weight [groups of memory cells storing the different bits of a a particular weight, para. 24]; and for each of the plurality of bits of the first target weight, the first selection circuit comprises:
a first switch, controlled by the bit, wherein the first switch determines whether the first input is passed to the first charge-domain passive summation circuit [transmission gate formed switches on the C-2C ladder selectively couple the analog input IA to the capacitors of the C-2C ladder according to the stored weight signals, para. 55-56]; and
a second switch, controlled by an inverse of the bit, wherein the second switch determines whether a reference voltage is passed to the first charge-domain passive summation circuit [see Fig. 6, each branch of the C-2C ladder 600 contains a switch. The switches are controlled by digital bits B0-B3 (e.g., bits of a weight which are stored in different memory cells of a same memory bank as described above) and connected to either a fixed reference voltage VREF or ground node (GND). For example, if a stored bit (i.e., one of digital bits B0-B3) is a ‘1’ the corresponding switch is connected to Vref. If the stored bit is a ‘0,’ the corresponding switch is connected to ground, para. 52].
Regarding claim 13, Wang et al. disclose wherein the first memory array comprises a plurality of memory cell lines arranged to store the plurality of candidate weights, respectively; the first selection circuit comprises:
a plurality of cell selection switch groups, corresponding to the plurality of memory cell lines, respectively [the controller 106 controls the switching elements 108 to selectively electrically connect the plurality of memory cells 104 to the MAC 110, para. 28], wherein each of the plurality of cell selection switch groups comprises cell selection switches, each having one terminal that is coupled to the first charge-domain passive summation circuit; and cell selection switches of one of the plurality of cell selection switch groups that corresponds to a memory cell line in which the first target weight is stored are switched on [the controller may generate the connection signal and transmit the connection signal over RWL0 to execute NN operations. Bank 0 will then receive the connection signal over RWL0 and internal transistors (or switches) may connect the memory cells of bank 0 to the C-2C ladder 310. The internal transistors may correspond to the switching elements 108 (FIG. 1), para. 38].
Regarding claim 14, Wang et al. wherein cell selection switches of the rest of the plurality of cell selection switch groups are switched off [while the first weight group is connected, the second through N groups are simultaneously disconnected, para. 28-30].
Regarding independent claim 19, Wang et al. disclose a compute-in-memory (CIM) [Fig. 3A: 320] method comprising:
storing a plurality of candidate weights in a memory array [see Fig. 3A, the first CiM array 322 includes p banks that comprise memory cells represented as squares. Each of the p banks stores a q-bit weight in memory cells (e.g., each memory cell stores one bit of the q-bit weight), para. 42];
selecting a target weight from the plurality of candidate weights [see Fig. 4: step 452-454, identify stored data for a MAC operation and connect the selected memory cell while disconnecting another, para. 48-49];
and performing, by a weighted capacitor array integrated with the memory array, charge-domain passive summation to generate an analog computation result of an input and the target weight [one of the p memory banks is connected to the C-2C ladder 312 to provide a weight to the C-2C ladder 312, para. 42. See Fig. 6, the C-2C ladder 600 is a capacitor network having C and 2C capacitors arranged in binary weighted branches. Each branch represents a different weight bit and the ladder output becomes the product of input activation IA and weight W, para. 51-53. See Fig. 7, the SRAM cells 616 are connected to the C-2C ladder 618 via switching elements and inverters, para. 55].
Regarding claim 20, Wang et al. disclose wherein the plurality of candidate weights are weights of a neural network [the weights are obtained during a neural network training process and preloaded in the network, para. 25].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Wang et al. (US 20220334801) as applied to claim 1 above, and further in view of Chen et al. (US 20220230064].
Regarding claim 3, Wang et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose wherein the first input of the first processing circuit is a single analog signal [para. 30 as well as para. 56].
However, Wang et al. are silent with respect to the first input of the first processing circuit is generated from an external analog buffer.
Chen et al. teach an analog circuit 120 is an analog compute-in-memory (ACIM) device that includes a cell array for data storage and in-memory computations. The analog circuit 120 is coupled to an input circuit 350 and an output circuit 360, which buffer input data and output data of convolution operations, respectively [see Fig. 3, para. 29].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chen et al. to the teaching of Wang et al. such that applying input circuit of Chen et al. to CIM array of Wang et al. so that input circuit of Chen et al. buffers and converts input data to generate the analog input signal supplied to Wang et al.’s C-2C ladder. The motivation would have been to provide the input buffering and data format conversion needed to interface neural network input data with Wang et al.’s CIM circuit, with a reasonable expectation of success because Chen et al. uses that arrangement with an ACIM cell array.
Allowable Subject Matter
Claims 15-18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
Prosecution Insights