DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 12/17/2025 in response to the Office Action mailed on 10/20/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into
fully consideration all the amendments.
Response to Arguments
Applicant’s arguments, see page 9 of the remarks, filed on 12/17/2025, with respect to the 112(b) rejection of Claim 15 have been fully considered and are persuasive. The rejection of Claim 15 has been withdrawn.
Applicant’s arguments, see page 10 of the remarks, filed on 12/17/2025, with respect to the rejections of claims 1, 12 and 17 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of previously applied prior art reference of Gu et al. in combination with newly found prior art reference of Lu et al. Lu et al. teaches the newly added limitations of claims 1, 12 and 17 as outlined in the rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary reference(s).
Claims 1-4, 7-15, 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 20150221714 A1), in view of Lu et al. (US 20210320059 A1).
Regarding Claim 1, Gu et al. teaches an integrated circuit (IC) package 900, comprising:
a substrate 1201 (see annotated Fig. 12: 1201, paragraph 0136);
a bare die 1202 mounted on the substrate 1201 (see annotated Fig. 12: 1202, 1201, paragraph 0136),
the bare die 1202 including IC circuitry 1001, a dielectric region 1002, 1020 at least partially encapsulating the IC circuitry 1001, and an IC contact 1016, 1018 exposed through the dielectric region 1002, 1020 (Fig. 10: 1001, 1002, 1020, 1016, 1018, annotated Fig. 12: 1202, paragraph 0129, 0204);
Note that Fig. 10 of Gu et al. shows an example of the die 1202 of Fig. 12. According to paragraph 0204, the substrate 1001 of the die comprises circuit elements and hence is interpreted as the IC circuitry.
a conductive routing region including multiple conductive routing layers a, b, c, d, e, f, including at least a first conductive routing laver d and a second conductive routing layer e, formed over the bare die 1202 (see annotated Fig. 12, a, b, c, d, e, f, paragraph 0136);
a conductive routing structure 1208, 1212, 1210 formed in the multiple conductive routing layers a, b, c, d, e, f, wherein the conductive routing structure 1208, 1212, 1210 is conductively connected to the IC contact of the bare die 1202 (see annotated Fig. 12: 1208, 1212, 1210, 1202, paragraph 0136);
and a capacitor 1216 formed in the conductive routing region (see annotated Fig. 12: 1214, paragraph 0136), the capacitor 1216 including:
a first capacitor electrode 1104 (see annotated Fig. 12, Fig. 11: 1104, 1108, paragraph 0120, 0131, 0134) including a first electrode first comb-shaped structure formed in the first conductive routing layer, a first electrode second comb-shaped structure formed in the second conductive routing layer, and at least one first electrode connecting element conductively connecting the first electrode first comb-shaped structure with the first electrode second comb-shaped structure;
a second capacitor electrode 1108 (see annotated Fig. 12, Fig. 11: 1104, 1108, paragraph 0120, 0131, 0134) including a second electrode first comb-shaped structure formed in the first conductive routing layer, a second electrode second comb-shaped structure formed in the second conductive routing layer, and at least one second electrode connecting element conductively connecting the second electrode first comb- shaped structure with the second electrode second comb-shaped structure;
and a capacitor dielectric element 1106 formed between the first capacitor electrode 1104 and the second capacitor electrode 1108 (see annotated Fig. 12, Fig. 11: 1104, 1108, paragraph 0120, 0131, 0134).
Note that Fig. 11 of Gu et al. shows a close up of the capacitor 1216 of Fig. 12.
Lu et al. teaches an integrated circuit (IC) package comprising the following limitations not disclosed in Gu et al. :
a first capacitor electrode 12 including a first electrode first comb-shaped structure 12C formed in the first conductive routing layer M1, a first electrode second comb-shaped structure 12B formed in the second conductive routing layer M2, and at least one first electrode connecting element 16 conductively connecting the first electrode first comb-shaped 12C structure with the first electrode second comb-shaped structure 12B (Fig. 1: M1, M2, M3, Fig.2: 12, 12A, 12B, 12C, 14, 14A, 14B, 14C, 16, 18, paragraphs 0021, 0023,-0025).
a second capacitor electrode 14 including a second electrode first comb-shaped structure 14C formed in the first conductive routing layer M1, a second electrode second comb-shaped structure 14B formed in the second conductive routing layer M2, and at least one second electrode connecting element 18 conductively connecting the second electrode first comb-shaped structure.
14C with the second electrode second comb-shaped structure 14B (Fig. 1: M1, M2, M3, Fig.2: 12, 12A, 12B, 12C, 14, 14A, 14B, 14C, 16, 18, paragraphs 0021, 0023,-0025).
Note that paragraph 0021 suggests that the conductive routing layers M1, M2, M3 of Fig. 1 implement fingers 12, 14, 16, 18 of the capacitor 10 shown in Fig. 2.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gu et al. and Lu et al. in order to come up with the claimed invention as recited in Claim 1. Doing so would enable the fabrication of an interdigitated capacitor with high-capacitance density, as recognized by Lu et al. (paragraph 0001).
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Annotated Fig. 12 of Gu et al. (US 20150221714 A1).
Regarding Claim 2, Gu et al. teaches the IC package of Claim 1, wherein the IC package 1200 comprises a chip-first package (See Fig. 20A, paragraph 0209, 0210).
Note that in Fig. 20A, the die is placed first on the substrate during step 1 before the routing layers are fabricated around the die in steps 2 and 3.
Regarding Claim 3, Gu et al. teaches the IC package of Claim 1, wherein the conductive routing region comprises a redistribution layer (RDL) region, wherein respective conductive routing layers of the multiple conductive routing layers comprise respective RDL layers (see annotated Fig. 12, paragraph 0136).
Regarding Claim 4, Gu et al. teaches the IC package of Claim 1, wherein the conductive routing structure includes at least one conductive element 1208, 1210 separate from the capacitor 1216 and formed in at least one of the first conductive routing layer d or the second conducting routing layer e (see annotated Fig. 12: d, e, 1208, 1210, 1216).
Regarding Claim 7, Gu et al . teaches the IC package of Claim 1, the IC package of Claim 1, wherein the capacitor dielectric element 1106 is formed in a via layer e between the first conductive routing layer d and the second conducting routing layer e (see annotated Fig. 12: e, Fig 11: 1106, d, e, paragraph 0135).
Regarding Claim 8, Lu et al. teaches the IC package of Claim 1, wherein: the first electrode first comb-shaped structure 12C includes multiple elongated fingers 20A; and the second electrode second comb-shaped structure 14C includes multiple elongated fingers 20B interdigitated with the multiple elongated fingers 20A of the first electrode first comb-shaped structure 12C (Fig. 2: 12C, 14C, 20A, 20B, paragraph 0023).
Regarding Claim 9, Gu et al. teaches the IC package of Claim 1, wherein:
the multiple conductive routing layers a, b, c, d, e include multiple metal layers b, d alternating with multiple via layers a, c, e (as taught by Gu et al., see annotated Fig. 12: a, b, c, d, e);
the first conductive routing layer d comprises a first respective metal layer (metal layer corresponding to the first electrode in annotated Fig 12) of the multiple metal layers b, d;
the second conductive routing layer e comprises a second respective metal layer (metal layer corresponding to the second electrode in annotated Fig. 12) of the multiple metal layers b, d.
and the capacitor dielectric element is formed in a respective via layer e of the multiple via layers a, c, e arranged between the first respective metal layer (metal layer corresponding to the first electrode in annotated Fig. 12) and the second respective metal layer (metal layer corresponding to the second electrode in annotated Fig. 12) (see annotated Fig. 12: a, b, c, d, e),
Regarding Claim 10, Gu et al . teaches the IC package of Claim 1, wherein: the IC package 1200 includes a further bare die 1204 mounted to the substrate 1201; and the capacitor 1216 is electrically coupled between the bare die 1202 and further bare die 1204 (See annotated fig. 12: 1204, 1202, 1201, 1216, paragraph 0138).
Regarding Claim 11, Gu et al. teaches the IC package of Claim 1, wherein: the conductive routing structure includes an external contact element 1218 contactable by an external device, but fails to teach the capacitor 1216 is electrically coupled between the bare die 1202 and the external contact element 1218 (see annotated Fig. 12: 1218, 1216, 1202, paragraph 0136, 0140).
However, in a different embodiment, Gu et al. teaches the capacitor 914 is electrically coupled between the bare die 902 and the external contact element 918 (see Fig. 9: 918, 916, 902, paragraph 0117, 0122).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the different embodiments of Gu et al. in order to have the capacitor electrically coupled between the bare die and the external contact element. Doing so would enable the bare die to interface with external circuits.
Regarding Claim 12, Gu et al. teaches a method of forming an integrated circuit (IC) package, comprising:
mounting a bare die 2006 on a substrate 2001 (Fig. 20A: 2006, 2001, paragraph 0210),
the bare die 2006 including IC circuitry 1001, a dielectric region 1002, 1020 at least partially encapsulating the IC circuitry 1001, and an IC contact 1016, 1018 exposed through the dielectric region 1002, 1020 (Fig. 10: 1001, 1002, 1020, 1016, 1018, annotated Fig. 20A: 2006, paragraph 0129, 0204);
Note that Fig. 10 of Gu et al. shows an example of the die 2006 of Fig. 20A. According to paragraph 0204, the substrate 1001 of the die comprises circuit elements and hence is interpreted as the IC circuitry.
and after mounting the bare die 2006 on the substrate 2001, forming a conductive routing region including multiple conductive routing layers over the bare die 2006, including at least a first conductive routing laver d and a second conductive routing layer e (see Fig 20A: steps 2-3, Fig. 20B: step 4, annotated Fig. 9, paragraphs 0211-0213);
wherein forming the conductive routing region includes: forming a conductive routing structure including conductive elements 2012, 2014, 2016, 2022, 2026, 2032, 2036 formed in respective conductive routing layers of the multiple conductive routing layers, wherein the conductive routing structure is conductively connected to the IC contact of the bare die 2006 (Fig. 20A-20B: 2012, 2014, 2016, 2022, 2026, 2032, 2036, Fig. 9, paragraphs 0211-0213);
and forming a capacitor 2024 including:
forming a first capacitor electrode 1702 (Fig. 20A: step 3, 2024, Fig. 17A: 1702, 1704, 1706, paragraphs 0173-0176) including a first electrode first comb-shaped structure formed in the first conductive routing layer, a first electrode second comb-shaped structure formed in the second conductive routing layer, and at least one first electrode connecting element conductively connecting the first electrode first comb-shaped structure with the first electrode second comb-shaped structure;
forming a second capacitor electrode 1706 (Fig. 20A: step 3, 2024, Fig. 17A: 1702, 1704, 1706, paragraphs 0173-0176) including a second electrode first comb-shaped structure formed in the first conductive routing layer, a second electrode second comb-shaped structure formed in the second conductive routing layer, and at least one second electrode connecting element conductively connecting the second electrode first comb- shaped structure with the second electrode second comb-shaped structure;
and forming a capacitor dielectric element 1704 between the first capacitor electrode 1702 and the second capacitor electrode 1706 (Fig. 20A: step 3, 2024, Fig. 17A: 1702, 1704, 1706, paragraphs 0173-0176).
Note that Fig. 17A of Gu et al. shows the manufacturing steps of the capacitor 2024 of Fig. 20A.
Lu et al. teaches a method of forming an integrated circuit (IC) package comprising the following limitations not disclosed in Gu et al. :
forming a first capacitor electrode 12 including a first electrode first comb-shaped structure 12C formed in the first conductive routing layer M1, a first electrode second comb-shaped structure 12B formed in the second conductive routing layer M2, and at least one first electrode connecting element 16 conductively connecting the first electrode first comb-shaped 12C structure with the first electrode second comb-shaped structure 12B (Fig. 1: M1, M2, M3, Fig.2: 12, 12A, 12B, 12C, 14, 14A, 14B, 14C, 16, 18, paragraphs 0021, 0023,-0025).
forming a second capacitor electrode 14 including a second electrode first comb-shaped structure 14C formed in the first conductive routing layer M1, a second electrode second comb-shaped structure 14B formed in the second conductive routing layer M2, and at least one second electrode connecting element 18 conductively connecting the second electrode first comb-shaped structure 14C with the second electrode second comb-shaped structure 14B (Fig. 1: M1, M2, M3, Fig.2: 12, 12A, 12B, 12C, 14, 14A, 14B, 14C, 16, 18, paragraphs 0021, 0023,-0025).
Note that paragraph 0021 suggests that the conductive routing layers M1, M2, M3 of Fig. 1 implement fingers 12, 14, 16, 18 of the capacitor 10 shown in Fig. 2.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gu et al. and Lu et al. in order to come up with the claimed invention as recited in Claim 1. Doing so would enable the fabrication of an interdigitated capacitor with high-capacitance density, as recognized by Lu et al. (paragraph 0001).
Regarding Claim 13, Gu et al. teaches the method of Claim 12, wherein forming the conductive routing region including multiple conductive routing layers comprises forming a redistribution layer (RDL) region including multiple RDL layers (Fig. 20A-20B: steps 2-4, paragraphs 0210-0213).
Regarding Claim 14, Gu et al. teaches the method of Claim 12, comprising forming at least one conductive element 2026 of the conductive routing structure, separate from the capacitor 2024, in at least one of the first conductive routing layer d or the second conducting routing layer e (see rejection of Claim 4 above, Fig. 20A-20B: 2026, 2024, steps 2-4, annotated Fig. 12: d, e).
Regarding Claim 15, Gu et al. teaches the method of Claim 12, wherein:
the multiple conductive routing layers a, b, c, d, e include multiple metal layers b, d alternating with multiple via layers a, c, e (see annotated Fig. 12: a, b, c, d, e);
the first conductive routing layer d comprises a first respective metal layer (metal layer corresponding to the first electrode in annotated Fig 12) of the multiple metal layers b, d;
the second conductive routing layer e comprises a second respective metal layer (metal layer corresponding to the second electrode in annotated Fig. 12) of the multiple metal layers b, d.
and the capacitor dielectric element is formed in a respective via layer e of the multiple via layers a, c, e arranged between the first respective metal layer (metal layer corresponding to the first electrode in annotated Fig. 12) and the second respective metal layer (metal layer corresponding to the second electrode in annotated Fig. 12) of the multiple metal layers b, d (see annotated Fig. 12: a, b, c, d, e).
Regarding Claim 17, Gu et al. teaches an integrated circuit (IC) package 1200, comprising:
a substrate 1201 (see Fig. 12: 1201, paragraph 0136);
a first bare die 1202 and a second bare 1204 die mounted on the substrate 1201 (see Fig. 12: 1202, 1204, 1201, paragraph 0136);
and a conductive routing layer stack a, b, c, d, e formed over the first bare die 1202 and second bare die 1204, the conductive routing layer stack a, b, c, d, e including: a first conductive routing layer d and a second conducting routing layer e (see Fig. 12: 1208, 1210, a, b, c, d, e, paragraph 0136);
at least one conductive routing structure 1208, 1210 including respective elements formed in the first conductive routing layer d and second conducting routing layer e and conductively connected to at least one of the first bare die 1202 and the second bare die 1204 (see Fig. 12: 1208, 1210, a, b, c, d, e, paragraph 0136);
and a capacitor 1216 including:
a first capacitor electrode (bottom plate of capacitor 1216) conductively connected to the first bare die 1202 (see Fig. 12: 1202, 1204, 1216, paragraph 0138);
the first capacitor electrode 1104 including a first electrode first comb-shaped structure formed in the first conductive routing layer, a first electrode second comb-shaped structure formed in the second conductive routing layer, and at least one first electrode connecting element conductively connecting the first electrode first comb-shaped structure with the first electrode second comb-shaped structure;
a second capacitor electrode (top plate of capacitor 1216) conductively connected to the second bare die 1204 (see Fig. 12: 1202, 1204, 1216, paragraph 0138);
the second capacitor electrode 1108 including a second electrode first comb-shaped structure formed in the first conductive routing layer, a second electrode second comb-shaped structure formed in the second conductive routing layer, and at least one second electrode connecting element conductively connecting the second electrode first comb- shaped structure with the second electrode second comb-shaped structure;
and a capacitor dielectric element formed between the first capacitor electrode and the second capacitor electrode (see Fig. 12: 1202, 1204, 1216, paragraph 0138).
Lu et al. teaches an integrated circuit (IC) package comprising the following limitations not disclosed in Gu et al. :
the first capacitor electrode 12 including a first electrode first comb-shaped structure 12C formed in the first conductive routing layer M1, a first electrode second comb-shaped structure 12B formed in the second conductive routing layer M2, and at least one first electrode connecting element 16 conductively connecting the first electrode first comb-shaped 12C structure with the first electrode second comb-shaped structure 12B (Fig. 1: M1, M2, M3, Fig.2: 12, 12A, 12B, 12C, 14, 14A, 14B, 14C, 16, 18, paragraphs 0021, 0023,-0025).
the second capacitor electrode 14 including a second electrode first comb-shaped structure 14C formed in the first conductive routing layer M1, a second electrode second comb-shaped structure 14B formed in the second conductive routing layer M2, and at least one second electrode connecting element 18 conductively connecting the second electrode first comb-shaped structure.
14C with the second electrode second comb-shaped structure 14B (Fig. 1: M1, M2, M3, Fig.2: 12, 12A, 12B, 12C, 14, 14A, 14B, 14C, 16, 18, paragraphs 0021, 0023,-0025).
Note that paragraph 0021 suggests that the conductive routing layers M1, M2, M3 of Fig. 1 implement fingers 12, 14, 16, 18 of the capacitor 10 shown in Fig. 2.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gu et al. and Lu et al. in order to come up with the claimed invention as recited in Claim 1. Doing so would enable the fabrication of an interdigitated capacitor with high-capacitance density, as recognized by Lu et al. (paragraph 0001).
Regarding Claim 18, Gu et al. teaches the IC package of Claim 17, wherein the IC package 1200 comprises a chip-first package (See Fig. 20A, paragraph 0209, 0210).
Note that in Fig. 20A, the die is placed first on the substrate during step 1 before the routing layers are fabricated around the die in steps 2 and 3.
Regarding Claim 19, Gu et al. teaches the IC package of Claim 17, wherein the conductive routing layer stack a, b, c, d, e comprises multiple redistribution layer (RDL) layers (see Fig 12: a, b, c, d, e, paragraph 0136).
Regarding Claim 20, Gu et al. teaches the IC package of Claim 17, wherein the capacitor 1216 comprises a Metal-Insulator- Metal (MIM) capacitor (Fig. 12: 1216, paragraph 0144).
Regarding Claim 21, Gu et al. fails to explicitly teach the IC package of Claim 17, wherein the capacitor comprises a Metal-Oxide-Metal (MOM) capacitor.
However, Lu et al. teaches, wherein the capacitor 10 comprises a Metal-Oxide-Metal (MOM) capacitor (Fig. 2: 10, paragraph 0024).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gu et al. and Lu et al. in order to have the capacitor comprise a Metal-Oxide-Metal (MOM) capacitor. Doing so would improve the reliability and stability of the capacitor rendered by the oxide dielectric layer.
Regarding Claim 22, Lu et al. teaches the IC package of Claim 1, wherein: the at least one first electrode connecting element 16 comprise at least one vertically-extending first via V1 connecting the first electrode first comb-shaped structure 12C with the first electrode second comb-shaped structure 12B; and the at least one second electrode connecting element 18 comprise at least one vertically- extending second via V1 connecting the second electrode first comb-shaped structure 14C with the second electrode second comb-shaped structure 14B (Fig.1: V1, Fig.2: 12B, 12C, 14B, 14C, 16, 18, paragraphs 0019, 0021, 0023,-0025).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 20150221714 A1), in view of Lu et al. (US 20210320059 A1), as applied to Claim 12 above, in view of Chen et al. (US 20230230849 A1).
Regarding Claim 16, the combination of Gu et al. and Lu et al. teaches the method of Claim 12, wherein forming the capacitor dielectric element 1704 comprising: using a removal process to form at least one opening 1703 extending vertically through the first conductive routing layer and the second conductive routing layer; and filling the at least one opening with a dielectric material 1704 (as taught by Lu et al., see Fig. 17a: steps 1-5, 1702, 1703, 1704, paragraphs 0173-0176), except that the removal process is a laser-based process.
However, et al. teach However, teaches a method of forming an However, Cheng et al. teaches a method of forming an IC package comprising using a laser-based removal process to form at least one opening OP1-OPm adjacent to the electrode PAD1 - PADm (Fig. 16A: PAD1-PADm, Fig. 16B: OP1-OPm, paragraph 0049).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Gu et al. and Chen et al. in order to for the method of Gu et al. to comprise a laser-based drilling process. Doing so would improve the precision of the removal process as laser-based drilling is well known for its localized removal of micrometer-scale target regions without affecting surrounding regions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817
06/06/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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