DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on September
11, 2024.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 18, the REMARKS states “the P area 22 extends only partially underneath the alleged corresponding first insulating layer (region 24)”. It appears the limitation “completely underneath the first insulating layer” requires the first doped well to be entirely underneath the first insulating layer without extending beyond the first insulating layer. However, it is not clear how such a reading is supported by the first doped well 320 and the first insulating layer 240 shown in Fig. 3 of the Drawings. In fact, it appears the first doped well 320 extends beyond the first insulating layer 240 toward the varying lateral doping zone 310 and the high voltage electrically conductive structure 210. Further, it is noted that Claim 4 already recites “directly underneath the high voltage electrically conductive structure”. It is not clear how the first doped well is completely underneath the first insulating layer when it is already required to be directly underneath the high voltage electrically conductive structure. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 10-11, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0058506 A1 to Nakamura (“Nakamura”) in view of U.S. Patent Application Publication No. 2014/0273516 A1 to Xia et al. (“Xia”).
As to claim 1, although Nakamura discloses a high voltage semiconductor device, comprising: a semiconductor substrate (14); a high voltage electrically conductive structure (5A) disposed on the semiconductor substrate (14); a first step topography at an edge of the high voltage electrically conductive structure (5A); a varying lateral doping zone (22b) disposed within the semiconductor substrate (14); and a layer (20), wherein the layer (20) conforms to the first step topography and extends over the varying lateral doping zone (22b) (See Fig. 91, ¶ 0001, ¶ 0101, ¶ 0120, ¶ 0124, ¶ 0125, ¶ 0127, ¶ 0128, ¶ 0166, ¶ 0188, ¶ 0190, ¶ 0308, ¶ 0309, ¶ 0318, ¶ 0319, ¶ 0322) (Notes: “high voltage” is a relative term such that the limitation is met by applying a relatively high bias to the semiconductor device. Further, the “varying lateral doping zone” varies by the dimension), Nakamura does not further disclose wherein the layer is a layer stack comprising: an electrically insulating buffer layer; a SiC layer over the electrically insulating buffer layer; and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer. However, Xia does disclose a layer stack (406, 402, 404) comprising: an electrically insulating buffer layer (406); a SiC layer (402) over the electrically insulating buffer layer (406); and a silicon nitride layer (404) over the SiC layer (402) or a nitrided surface region of the SiC layer (402) (See Fig. 1, Fig. 4, ¶ 0003, ¶ 0006, ¶ 0026, ¶ 0029, ¶ 0040, ¶ 0042, ¶ 0043, ¶ 0051, ¶ 0052). In view of the teaching of Xia, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Nakamura to have wherein the layer is a layer stack comprising: an electrically insulating buffer layer; a SiC layer over the electrically insulating buffer layer; and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer because Nakamura already teaches the layer is conformally deposited on the high voltage electrically conductive structure (See Fig. 91), Xia then further teaches the layer stack comprising different dielectric layers at the interface introduces an abrupt step for the breakdown voltage via variation of the band gap and misalignment of band diagrams, resulting in improved breakdown strength (See ¶ 0029, ¶ 0040, ¶ 0042, ¶ 0043, ¶ 0051, ¶ 0052). As to claim 2, Nakamura in view of Xia discloses further comprising a first insulating layer (24) disposed on the semiconductor substrate (14) underneath the high voltage electrically conductive structure (5A), wherein the layer stack (20/406, 402, 404) extends along an outer edge of the first insulating layer (24) (See Nakamura Fig. 91, ¶ 0125). As to claim 3, Nakamura in view of Xia further discloses wherein the first insulating layer (24) protrudes out from the high voltage electrically conductive structure (5A) and forms a second step topography at an edge of the first insulating layer (24), and wherein the layer stack (20/406, 402, 404) conforms to the second step topography (See Nakamura Fig. 91). As to claim 4, Nakamura in view of Xia discloses further comprising a first doped well (10, 22) within the semiconductor substrate (14) laterally adjoining the varying lateral doping zone (22b) and directly underneath the high voltage electrically conductive structure (5A) and the first insulating layer (24), wherein the varying lateral doping zone (22b) is more weakly doped (P-) than the first doped well (10, 22) (See Nakamura Fig. 91). As to claim 5, Nakamura in view of Xia discloses further comprising: a peripheral conductive structure (5Z) arranged at an outer edge of the semiconductor substrate (14); and a third step topography at an edge of the peripheral conductive structure (5Z) that faces the high voltage electrically conductive structure (5A), wherein the layer stack (20/406, 402, 404) conforms to the third step topography (See Nakamura Fig. 91, ¶ 0127). As to claim 6, Nakamura in view of Xia discloses further comprising a second insulating layer (24 right) disposed on the semiconductor substrate (14) underneath the peripheral conductive structure (5Z), wherein the layer stack (20/406, 402, 404) extends along an outer edge of the second insulating layer (24 right) (See Nakamura Fig. 91). As to claim 7, Nakamura in view of Xia further discloses wherein the second insulating layer (24 right) protrudes out from the peripheral conductive structure (5Z) and forms a fourth step topography at an edge of the second insulating layer (24 right), and wherein the layer stack (20/406, 402, 404) conforms to the fourth step topography (See Nakamura Fig. 91). As to claim 10, Nakamura in view of Xia further discloses wherein the electrically insulating buffer layer (406) is an oxide layer (406) (See Xia ¶ 0052). As to claim 11, Nakamura further discloses wherein the high voltage electrically conductive structure (5A) comprises aluminum or copper (See Fig. 91, ¶ 0166). As to claim 14, Nakamura in view of Xia further discloses wherein the SiC layer (402) is electrically floating (See Xia Fig. 4) (Notes: the SiC layer is sandwiched by the SiO and SiN layers such that it is electrically floating). As to claim 15, Nakamura further discloses wherein the high voltage electrically conductive structure (5A) is configured to operate at a voltage equal to or greater than 0.6 kV (See ¶ 0101, ¶ 0322). Further, the claim limitation “is configured to operate at a voltage equal to or greater than 0.6 kV” specifies an intended use or field of use, and is met by the prior art since it has been held that in device claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ 2d 1647 (Bd. Pat. App. & Inter. 1987). As to claim 16, Nakamura further discloses wherein the high voltage semiconductor device is one of an IGBT, FET, diode, thyristor, GTO, JFET, MOSFET, BJT, and HEMT (See Fig. 91, ¶ 0322).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0058506 A1 to Nakamura (“Nakamura”) and U.S. Patent Application Publication No. 2014/0273516 A1 to Xia et al. (“Xia”) as applied to claim 1 above, and further in view of EP 1 233 449 A2 to Maex et al. (“Maex”). The teachings of Nakamura and Xia have been discussed above. As to claim 8, although Xia discloses the SiC layer (402) (See ¶ 0052), Nakamura and Xia do not further disclose wherein the SiC layer is an a-SiC:H layer.
However, Maex does disclose wherein the SiC layer is an a-SiC:H layer (See ¶ 0080). In view of the teaching of Maex, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings Nakamura and Xia to have wherein the SiC layer is an a-SiC:H layer because the SiC layer as a barrier layer is understood to include an a-SiC:H layer along with other variations (See ¶ 0080).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0058506 A1 to Nakamura (“Nakamura”) and U.S. Patent Application Publication No. 2014/0273516 A1 to Xia et al. (“Xia”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2019/0305140 A1 to Morimoto (“Morimoto”). The teachings of Nakamura and Xia have been discussed above. As to claim 12, although Nakamura in view of Xia discloses further comprising: a passivation layer (21) over the silicon nitride layer (404) or over the nitrided surface region of the SiC layer (See Nakamura Fig. 91, ¶ 0128 and Xia Fig. 4, ¶ 0052), Nakamura and Xia do not further disclose wherein the passivation layer is an imide layer. However, Morimoto does disclose wherein the passivation layer (15) is an imide layer (15) (See Fig. 5, ¶ 0031). In view of the teaching of Morimoto, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Nakamura to have wherein the passivation layer is an imide layer because the moisture blocking performance can be improved (See ¶ 0031).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0058506 A1 to Nakamura (“Nakamura”) and U.S. Patent Application Publication No. 2014/0273516 A1 to Xia et al. (“Xia”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2006/0022343 A1 to Lin et al. (“Lin”). The teachings of Nakamura and Xia have been discussed above. As to claim 13, although Nakamura discloses wherein: the first step topography comprises a horizontal base and a vertical sidewall; and the vertical sidewall has a height (See Fig. 91), Nakamura and Xia do not further disclose wherein the height is equal to or greater than 0.5 μm or 1 μm or 2 μm or 3 μm or 5 μm or 7 μm or 10 μm. However, Lin does disclose wherein the height is equal to or greater than 0.5 μm or 1 μm or 2 μm or 3 μm or 5 μm or 7 μm or 10 μm (See Fig. 5, ¶ 0027, ¶ 0033). In view of the teaching of Lin, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Nakamura to have wherein the height is equal to or greater than 0.5 μm or 1 μm or 2 μm or 3 μm or 5 μm or 7 μm or 10 μm because the height is one parameter that determines the overall dimension of the device and the associated conductivity, where having a certain height controls the device dimension and operating condition (See Nakamura and Lin ¶ 0033).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0058506 A1 to Nakamura (“Nakamura”) and U.S. Patent Application Publication No. 2014/0273516 A1 to Xia et al. (“Xia”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2014/0131654 A1 to Tu et al. (“Tu”). The teachings of Nakamura and Xia have been discussed above. As to claim 17, although Nakamura in view of Xia discloses wherein the SiC layer (402) has a thickness (See Xia Fig. 4) Nakamura and Xia do not further disclose wherein the thickness is between 50 nm and 1 μm. However, Tu does disclose a conformally formed SiC layer (425, 430) has a thickness of 50 nm (See Fig. 4, ¶ 0034, ¶ 0035). In view of the teachings of Nakamura, Xia, and Tu, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the thickness is between 50 nm and 1 μm because the thickness is relatively chosen in the layer stack and determined in view of the requirements and/or constraints of passivation, barrier, adhesion, breakdown behavior, and reliability (See Nakamura, Xia, and Tu). Further, the applicant also has not established the critical nature of the “the thickness between 50 nm and 1 μm”. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to adjust the thickness of the SiC layer. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0058506 A1 to Nakamura (“Nakamura”) and U.S. Patent Application Publication No. 2014/0273516 A1 to Xia et al. (“Xia”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2010/0078756 A1 to Schmidt (“Schmidt”). The teachings of Nakamura and Xia have been discussed above. As to claim 19, although Nakamura discloses a dopant concentration of the varying lateral doping zone (22b) (See Fig. 91), Nakamura and Xia do not further disclose wherein the dopant concentration of the varying lateral doping zone decrease in a lateral direction towards an outer edge of the semiconductor substrate. However, Schmidt does disclose wherein the dopant concentration of the varying lateral doping zone (12) decrease in a lateral direction towards an outer edge of the semiconductor substrate (2) (See Fig. 1, ¶ 0020). In view of the teaching Schmidt, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Nakamura to have wherein the dopant concentration of the varying lateral doping zone decrease in a lateral direction towards an outer edge of the semiconductor substrate because the electric field strength is reduced in the edge region, where a moderate field distribution is obtained and a premature break-through of the device under blocking load is avoided (See ¶ 0020).
Response to Arguments
Applicant's arguments filed on September 11, 2024 have been fully considered but they are not persuasive. Applicants argue “there is no corresponding ‘low k film’ in the Nakamura reference that the person of ordinary skill would recognize as being susceptible to the same issues as described in Xia…to address an issue that does not necessarily exist in the Nakamura reference.” This is not found persuasive because Xia explicitly teaches the barrier layer also prevents moisture from penetrating to the underlying ILD and diffusion of the conductive material in [0042]. [0053] further discloses the barrier film stack demonstrates significant improvement in leakage current over ILD with a single barrier. It is also known that moisture or ammonia in the air deteriorates the interlayer dielectric layer (See [0022] of Shim (US 2007/0093048 A1) such that the layer stack of Xia prevents such diffusion. Since the layer 20 of Nakamura is over the interlayer insulating film 24, the electrode 5A/5Z, and the N-drift layer 14, it would have been obvious to form the layer stack to prevent moisture/ammonia diffusion and improve the breakdown strength.
Applicants further argue “the barrier layer disclosed by Xia is a two-layer structure.” This is not found persuasive because Xia teaches the barrier film stack 400 may be used to replace the barrier layer 121. Even if layer 406 corresponds to the interlayer dielectric 102, Xia clearly teaches two or more dielectric materials and the arrangement of SiO/SiC/SiN in [0051] and [0052] at least suggests the layer stack of three different dielectric materials/layers having different bandgaps.
Applicants further argue “the peripheral conductive structure reaches the outer edge of the semiconductor substrate…the electrode 5Z is spaced apart from the edge of the substate 14. It is therefore not arranged at an outer edge of the semiconductor substrate.” This is not found persuasive because the limitation “an outer edge of the semiconductor substrate” does not specify the exact position of the “edge”. The limitation is reasonably interpreted as an outer exposed surface of the semiconductor substrate where 26 of the semiconductor substrate is in direct contact with the electrode 5Z. Since the peripheral conductive structure 5Z is in contact with and therefore arranged at an upper exposed surface/edge of the semiconductor substrate, the limitation is met by Nakamura.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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