DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of group 1 in the reply filed on 8/13/26 is acknowledged.
The restriction requirement made 7/30/26 is withdrawn in response to the applicant’s amendment filed 8/13/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-12, and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Wang et al. US 2021/0202465 A1 (“Wang”).
As to claim 1, Wang discloses an integrated circuit structure, comprising:
a plurality of first cells, each first cell having a corresponding height along a first direction that is within 1 nanometer (nm) of a first height, wherein each first cell has corresponding two or more transistor devices (Figure 1A and 1D or Paragraph 33 – e.g., cells 120 of a particular height Dl, with transistors, e.g., 132 and 134); and
a plurality of second cells, each second cell having a corresponding height along the first direction that is within 1 nm of a second height, the second height at least 3 nm smaller than the first height, wherein each second cell has corresponding two or more transistor devices (Figure 1A or 15 or Paragraph 27 or 52 – e.g., cells 122 of another height Ds, with a Dl/Ds ratio greater than 1.5);
wherein the first direction is parallel to a length of a gate structure of a first cell or a second cell (Figure 1A);
wherein the plurality of first cells are arranged in one or more first rows and the plurality of second cells are arranged in one or more second rows such that the one or more first rows each has the first height and the one or more second rows each has the second height (Figure 15 or Paragraph 52 – e.g., cells of different sizes stitched together); and
wherein the corresponding two or more transistor devices of at least one first cell includes a first transistor device having a first semiconductor body with a first width along the first direction and the corresponding two or more transistor devices of at least one second cell includes a second transistor device having a semiconductor body with a second width along the first direction that is shorter than the first width by at least 5 nm (Figure 1A or Paragraph 28 – e.g., W1 and W2).
As to claim 2, Wang discloses the structure of claim 1, Wang further discloses wherein the first semiconductor body comprises one or more first semiconductor nanoribbons and the second semiconductor body comprises one or more second semiconductor nanoribbons (Figure 1C – e.g., elements 130).
As to claim 3, Wang discloses the structure of claim 1, Wang further discloses a gate cut extending lengthwise along a second direction different from the first direction and along a boundary between adjacent rows of first cells and/or second cells (Figure 15 – e.g., necessary in separate gates 120 and 122).
As to claim 4, Wang discloses the structure of claim 1, Wang further discloses wherein a third transistor device of the two or more transistor devices of the at least one first cell has a third semiconductor body with the second width ().
As to claim 5, Wang discloses the structure of claim 1, Wang further discloses wherein each of the two or more transistor devices of the at least one first cell has a corresponding semiconductor body with substantially the same first width, and each of the two or more transistor devices of the at least one second cell has a corresponding semiconductor body with substantially the same second width (Figure 5 or Paragraph 42 – e.g., a taller cell with transistors of a same width as shorter cell transistors).
Claims 9-12, 14, 15, 17, and 18 recite elements similar to claims 1-5, and are rejected for the same reasons.
As to claim 16, Wang discloses the structure of claim 15, Wang further discloses wherein the first direction is orthogonal to the second direction (Figure 15 – e.g., the spacing between separate gates 120 and 122 is orthogonal to the first direction).
As to claim 19, Wang discloses the structure of claim 15, Wang further discloses a plurality of third cells, each third cell having substantially the same first height along the first direction, wherein each third cell has corresponding two or more transistor devices, wherein the plurality of third cells are arranged in one or more third rows, and wherein at least one of the two or more transistor devices of at least one third cell has a corresponding semiconductor body with substantially the same first width and at least one of the two or more transistor devices of the at least one third cell has a corresponding semiconductor body with substantially the same second width (Figures 9-10 – e.g., multiple rows of both larger and smaller cell heights).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
As to claim 8, Wang discloses the structure of claim 1, Wang further discloses a printed circuit board comprising the integrated circuit structure of claim 1 (obvious in a layered circuit design, e.g., Paragraphs 1, 15, or 18).
Claim 20 recites elements similar to claim 8, and is rejected for the same reasons.
Allowable Subject Matter
Claims 6, 7, and 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest an integrated circuit structure or system having the combination of steps/elements of the claims including, among other elements, layer relationship details of the claims, in combination with the other structural elements of the clams.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/Primary Examiner, Art Unit 2851
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