DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 2/26/2026, has been entered. The Applicant has amended claims 1-4, 6-7, and 20. Claims 1-20 are pending in the application.
Applicant’s amendments to the title and claims 2-4 and 6-7 have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 12/2/2025.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2023-0001322, filed on 01/04/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6, and 8-20are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2012/0276696 A1) in view of Ino (US 2021/0296326 A1).
Regarding claim 1, Yang teaches a vertical NAND flash memory device (NAND flash memory device having a vertical structure, Figs. 1 and 2, [0026]), comprising:
a plurality of cell arrays (plurality of memory cell strings 11, Figs. 1-2, [0034]),
wherein each cell array (memory cell string 11, Figs. 1-2) of the plurality of cell arrays (plurality of memory cell strings 11, Figs. 1-2) comprises:
a channel layer (channel region 130, Fig. 3 (zoomed portion A of Fig. 2), [0055]);
a charge trap layer (comprising charge storage layer 144 and nanocrystals (see [0049]), Fig. 3, [0058]: “The charge storage layer 144 may be a charge trapping layer …“) provided on the channel layer (channel region 130, Figs. 1-2), the charge trap layer (comprising charge storage layer 144 and nanocrystals, Fig. 3) comprising:
a matrix (charge storage layer 144, Fig. 3) comprising a dielectric (charge storage layer 144, Fig. 3, [0058]: “… silicon oxide (SiO2), …, hafnium oxide (HfO2), zirconium oxide (ZrO2) …”); and
a charge trap material ([0049]: “… the charge storage layer may include quantum dots or nanocrystals.”, which will be referred as charge trap material hereafter, as Yang does not specifically name this material) in the matrix (matrix) and
a plurality of gate electrodes (gate electrodes 152, 153, …, Figs. 2-3, [0046]) provided on the charge trap layer (charge storage layer 144, Figs. 2-3).
Yang, however, does not teach that
the charge trap material comprises anti-ferroelectric nanocrystals.
Ino, on the other hand, teaches a semiconductor memory device (three-dimensional NAND flash memory, Fig. 1, [0003]) with a memory cell (charge trap memory cell 100, Fig. 1, [0020]) wherein the charge trapping layer (charge storage layer 14, Figs. 1-2, [0028]: “The charge storage layer 14 has a function of trapping and storing a charge”) comprises
anti-ferroelectric nanocrystals (hafnium oxide crystal 14a, Fig. 2, [0065]: “The charge storage layer 14 contains antiferroelectric hafnium oxide crystals 14a”; and [0036]: “A thickness of the charge storage layer 14 is, for example, 2 nm or more and 10 nm or less.”; therefore hafnium oxide crystal is nanometer sized crystal).
Ino further discloses that the charge storage layer with antiferroelectric hafnium oxide crystals in the charge storage layer improves the charge storage density of the charge storage layer ([0058]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the charge tap layer in the vertical NAND flash memory device of Yang with the charge trap layer taught by Ino, such that the charge trap layer comprises a matrix (Ino: comprising second crystal 14b ([0039]: “The second crystal 14b is, for example, hafnium oxide of a space group P2.sub.1c (space group number 14). The hafnium oxide of the space group P2.sub.1c (space group number 14) is a paraelectric substance.”, Fig. 2) and amorphous region 14c ([0037]: comprises hafnium, oxide, and nitrogen (see claims 1 and 4 of Ino), Fig. 2)), and a charge trap material (comprising antiferroelectric nanocrystals), which would provide the benefit of improving the charge storing density of the charge trap layer.
Regarding claim 2, while Yang in view of Ino teaches the vertical NAND flash memory device of claim 1,
Yang does not teach that the charge trap material further comprises a flurite-based material, a perovskite-based material, or a wurtzite-based material.
Ino, on the other hand, teaches that the charge trap material (hafnium oxide crystal 14a, Fig. 2, [0065]) further comprises a fluorite-based material ([0065]: “hafnium oxide"), a perovskite-based material, or a wurtzite-based material.
Ino further discloses that using antiferroelectric hafnium oxide in the charge storage layer improves the charge storage density of the charge storage layer ([0058]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the charge trap material in the vertical NAND flash memory device of Yang from a fluorite-based material, as disclosed by Ino, to improve charge trapping density of the charge trap layer.
Regarding claim 3, Yang in view of Ino teaches the vertical NAND flash memory device of claim 2, wherein
the combination of Yang and Ino further teaches that the fluorite-based material comprises HfO2 (Ino, [0065]) or ZrO2.
Regarding claim 6, Yang in view of Ino teaches the vertical NAND flash memory device of claim 3, wherein
The combination of Yang and Ino teaches that the fluorite- based material comprises an anti-ferroelectric material (hafnium oxide crystal 14a, Fig. 2, [0038]) having a tetragonal system structure ([0038]: “The first crystal 14a is hafnium oxide of the space group … P42/nmc (space group number 137)”; space group P42/nmc (space group number 137) has a tetragonal system structure) or a ferroelectric material having an orthorhombic system structure.
Regarding claim 8, claim 8 does not require further examination because the charge trap material of the vertical NAND flash memory device of claim 2 does not comprise a perovskite-based material according to claim 2 rejection above.
Regarding claim 9, claim 9 does not require further examination because the charge trap material of the vertical NAND flash memory device of claim 2 does not comprise a perovskite-based material according to claim 2 and claim 8 rejections above.
Regarding claim 10, claim 10 does not require further examination because the charge trap material of the vertical NAND flash memory device of claim 2 does not comprise a wurtzite-based material according to claim 2 rejection above.
Regarding claim 11, claim 11 does not require further examination because the charge trap material of the vertical NAND flash memory device of claim 2 does not comprise a wurtzite-based material according to claim 2 and claim 10 rejections above.
Regarding claim 12, Yang in view of Ino teaches the vertical NAND flash memory device of claim 1, wherein
the combination Yang and Ino further teaches that the matrix (second crystal 14b and amorphous region 14c, Fig. 2, see claim 1 rejection above) further comprises a paraelectric material ([0039]: “The second crystal 14b is, for example, hafnium oxide of a space group P2.sub.1c (space group number 14). The hafnium oxide of the space group P2.sub.1c (space group number 14) is a paraelectric substance.”).
Regarding claim 13, Yang in view of Ino teaches the vertical NAND flash memory device of claim 1, wherein
Yang further discloses a substrate (substrate 100, Fig. 2, [0034])
wherein each cell array (memory cell string 11, Figs. 1-2, [0034]) of the plurality of cell arrays (plurality of memory cell strings 11, Figs. 1-2) is arranged perpendicularly to the substrate (substrate 100, Fig. 2: cell arrays are perpendicular to the substrate).
Regarding claim 14, Yang in view of Ino teaches the vertical NAND flash memory device of claim 13, wherein
Yang further teaches that a channel hole (region filled with buried insulating layer 175, Figs. 2 and 4N, [0039]) extending in a direction perpendicular (Figs. 2 and 4N) to the substrate (substrate 100, Figs. 2 and 4N, [0034]) is inward (Figs. 2 and 4N) relative to the channel layer (channel region 130, Figs 2 and 4N, [0055]).
Regarding claim 15, Yang in view of Ino teaches the vertical NAND flash memory device of claim 14, wherein
Yang further teaches that the channel hole (region filled with buried insulating layer 175, Figs. 2 and 4N, [0039]) is filled with a filling insulating layer (buried insulating layer 175, Figs. 2 and 4N).
Regarding claim 16, Yang in view of Ino teaches the vertical NAND flash memory device of claim 15, wherein
Yang further teaches that the channel layer (channel region 130, Figs. 2-3, [0055]) and the charge trap layer (comprising charge storage layer 144 and nanocrystals (see [0049]), Figs. 2-3) have a cylindrical shape (see Fig. 2) surrounding the channel hole (region filled with buried insulating layer 175, Figs. 2).
Regarding claim 17, Yang in view of Ino teaches the vertical NAND flash memory device of claim 16, wherein
Yang further teaches that the vertical NAND flash memory device further comprises a tunneling barrier layer (tunneling insulating layer 142, Fig. 3, [0056]) provided between the channel layer (channel region 130, Fig. 3) and the charge trap layer (comprising charge storage layer 144 and nanocrystals (see [0049]), Fig. 3).
Regarding claim 18, Yang in view of Ini teaches the vertical NAND flash memory device of claim 16, wherein
Yang further teaches that the plurality of gate electrodes (gate electrodes 152, 153, …, Figs. 2-3, [0046]) are spaced apart from each other (see Fig. 2) in the direction perpendicular to the substrate (substrate 100, Fig. 2, [0034]), and
wherein each gate electrode (each of gate electrodes 152, 153, …, Fig. 2) of the plurality of gate electrodes (gate electrodes 152, 153, …, Fig. 2) surrounds (see Fig. 2) the charge trap layer (comprising charge storage layer 144 and nanocrystals, Fig. 2).
Regarding claim 19, Yang in view of Ino teaches the vertical NAND flash memory device of claim 18, wherein
Yang further teaches that the vertical NAND flash memory device further comprises a blocking insulating layer (blocking insulating layer 146, Fig. 3, [0056]) provided between the charge trap layer (comprising charge storage layer 144 and nanocrystals (see [0049]), Fig. 3) and the plurality of gate electrodes (gate electrodes 152, 153, …, Fig. 3).
Regarding claim 20, Yang teaches an electronic device (non-volatile memory device 700, Fig. 7, [0108]), comprising
a vertical NAND flash memory device (NAND cell array 750, Fig. 7, [0108]) comprising a plurality of cell arrays (plurality of memory cell strings 11, Figs. 1-2, [0034]), wherein each cell array (memory cell string 11, Figs. 1-2) of the plurality of cell arrays (plurality of memory cell strings 11, Figs. 1-2) comprises:
a channel layer (channel region 130, Fig. 3 (zoomed portion A of Fig. 2), [0055]);
a charge trap layer (comprising charge storage layer 144 and nanocrystals (see [0049]), Fig. 3, [0058]: “The charge storage layer 144 may be a charge trapping layer …“) provided on the channel layer (channel region 130, Figs. 2-3), the charge trap layer (comprising charge storage layer 144 and nanocrystals, Fig. 3) comprising:
a matrix (charge storage layer 144, Fig. 3); and
a charge trap material ([0049]: “… the charge storage layer may include quantum dots or nanocrystals.”) in the matrix and comprising nanocrystals ([0049]: “nanocrystals”);
and
a plurality of gate electrodes (gate electrodes 152, 153, …, Figs. 2-3, [0046]) provided on the charge trap layer (charge storage layer 144, Figs. 2-3).
Yang, however, does not teach that
the matrix comprises a paraelectric material; and
the charge trap layer comprises anti-ferroelectric nanocrystals.
Ino, on the other hand, teaches a semiconductor memory device (three-dimensional NAND flash memory, Fig. 1, [0003]) with a memory cell (charge trap memory cell 100, Fig. 1, [0020]) wherein the charge trapping layer (charge storage layer 14, Figs. 1-2, [0028]: “The charge storage layer 14 has a function of trapping and storing a charge”) comprises
the matrix (comprising second crystal 14b ([0039]: “The second crystal 14b is, for example, hafnium oxide of a space group P2.sub.1c (space group number 14). The hafnium oxide of the space group P2.sub.1c (space group number 14) is a paraelectric substance.”, Fig. 2) and amorphous region 14c ([0037]: comprises hafnium, oxide, and nitrogen (see claims 1 and 4 of Ino), Fig. 2)) comprises a paraelectric material (second crystal 14b, Fig. 2); and
the charge trap layer (charge storage layer 14, Figs. 1-2, [0028]) comprises anti-ferroelectric nanocrystals (hafnium oxide crystal 14a, Fig. 2, [0065]: “The charge storage layer 14 contains antiferroelectric hafnium oxide crystals 14a”; and [0036]: “A thickness of the charge storage layer 14 is, for example, 2 nm or more and 10 nm or less.”; therefore hafnium oxide crystal 14c is nanometer sized crystal).
Ino further discloses that the charge storage layer with antiferroelectric hafnium oxide crystals in the charge storage layer improves the charge storage density of the charge storage layer ([0058]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the charge tap layer in the vertical NAND flash memory device of Yang with the charge trap layer taught by Ino, such that the charge trap layer comprises a matrix and a charge trap material as disclosed by Ino, which would provide the benefit of improving the charge storing density of the charge trap layer.
Thus, the combination of Yang and Ino also meets the limitations that
the matrix comprises a paraelectric material; and
the charge trap layer comprises anti-ferroelectric nanocrystals.
Claims 4-5 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2012/0276696 A1) in view of Ino (US 2021/0296326 A1) as applied to claims 1-3, 6, and 8-20 above, and further in view of Park (Park et al. (2015), Ferroelectricity and Antiferroelectricity of Doped Thin HfO2-Based Films. Adv. Mater., 27: 1811-1831. https://doi.org/10.1002/adma.201404531).
Regarding claim 4, while Yang in view Ino teaches the vertical NAND flash memory device of claim 3,
Yang and Ino are silent on the fluorite-based material further comprising a dopant.
Park, on the other hand, teaches that doping hafnium oxide with silicon stabilizes the t-phase (space group P42/nmc (space group number 137), page4, section 2.1)) (page 8, section 3.1) and induces antiferroelectric state at the doping level of 5-8% (page 8, section 3.1).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include Si dopants in the fluorite-based material of nanocrystals in the vertical NAND flash memory device of Yang in view of Ino, as disclosed by Park, to stabilize the antiferroelectric phase of nanocrystals.
Thus, the combination of Yang, Ino, and Park meets the limitation that
the flurite-based material further comprises a dopant.
Regarding claim 5, Yang in views of Ino and Park teaches the vertical NAND flash memory device of claim 4, wherein
the combination of Yang, Ino, and Park (see claim 4 rejection above) further teaches the dopant comprises at least one of Al, Ga, Co, Ni, Mg, In, La, Y, Nd, Sm, Er, Sr, Ba, Gd, Ge, N, and Si (Si, see claim 4 rejection above).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2012/0276696 A1) in view of Ino (US 2021/0296326 A1) as applied to claims 1-3, 6, and 8-20 above, and further in view of Yoo (US 2019/0244973 A1).
Regarding claim 7, while Yang in view of Ino teaches the vertical NAND flash memory device of claim 6
Yang and Lin are silent on that the flurite-based material comprises nanocrystals having a grain size of about 1 nm to about 7 nm.
Yoo, on the other hand teaches ferroelectric nano-sized hafnium dioxide crystal grains ([0105]; analogous to the fluorite-based material nanocrystals) in a ferroelectric hafnium dioxide layer (ferroelectric layer 325, Fig. 18, [0105]; analogous to the charge trap layer), wherein the flurite-based material (ferroelectric layer 325, Fig. 18) comprises nanocrystals (nano-sized hafnium dioxide crystal grains, [0105]) having a grain size of about 1 nm to about 7 nm ([0107]: smaller than 8nm).
Therefore, the range of grain size provided by the prior art overlaps with the range of grain size provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of grain sizes can be optimized by routine experimentation to achieve desired charge trapping and electrical characteristics of the device while keeping enough size for proper ferroelectricity (see MPEP 2144.05(II)). Furthermore, it is common to have the nanocrystal in a charge trap layer to have a size range similar to the provided range, as also evidenced by Choi (US 2009/0096014 A1, 1-15 nm. [0041]), Huo (US 2008/0246078 A1, about 5 nm, [0087]) and Ino (US 2011/0241101 A1, 0.9-2.8 nm [0043]). Therefore, the range of values provided does not hold an inventive subject matter.
Response to Arguments
It has been acknowledged that the applicant amended claims 1-4, 6-7, and 20 per response dated on 2/26/2026.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amended independent claims 1 and 20, now limiting the charge trap material to be an anti-ferroelectric material, overcame the rejections based on Yang (US 2012/0276696 A1) in view of Lin (US 2018/0233573 A1) for claim 1 and Yang for claim 20.
However, amended claims 1 and 20 are now rejected under new grounds based on Yang combined with a new prior-art, Ino (US 2021/0296326 A1), in the current office action. Rejections are also made claims 1-3 and 6-20 based on this new prior-art or its combination with the prior-art from the non-final office action.
Claims 4-5 are also rejected under new grounds based on Yang and Ino combined with another new prior-art, Park (Park et al. (2015), Ferroelectricity and Antiferroelectricity of Doped Thin HfO2-Based Films. Adv. Mater., 27: 1811-1831. https://doi.org/10.1002/adma.201404531), in the current office action.
For the purpose of compact prosecution, the Examiner notes that including further structural and material limitations may overcome the current rejections.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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