INTEGRATED CIRCUIT LOW CAPACITANCE ELECTROSTATIC DISCHARGE DIODES

Application No. 18/215,675

• Filed: Jun 28, 2023
• Examiner: DEGRASSE, IAN ISAAC
• Art Unit: 2818
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: Advanced Micro Devices Inc.
• OA Round: 2 (Final)

Office Action

DETAILED ACTION

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

Claims 1-4, 6, and 8-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0358570 A1 to Kaschani et al. (hereinafter “Kaschani” – previously cited reference).

Regarding claim 1, Kaschani discloses an apparatus for protection of integrated circuit inputs and outputs from electrostatic discharge (ESD), comprising:
an integrated circuit (IC) substrate (plurality of ESD cells 200 provided on p-type substrate 105 for I/O circuitry of IC device 400; Figs. 1, 2A and 3-4; paragraphs [0020], [0025], [0036]);
a P-well in the IC substrate (p-well 135a in substrate 105 of npn guard wall pocket 130 of one ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well in the IC substrate (n-well 135a in substrate 105 of pnp guard wall pocket 130 of another ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well ring around the P-well and in the IC substrate (n-well ring 140a in substrate 105 and around p-well 135a of npn guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
a P-well ring around the N-well and in the IC substrate (p-well ring 140a in substrate 105 and around n-well 135a of pnp guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
at least two fingers of an N-diode comprising N+ implants in the P-well (n+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two P+ guard rings comprising P+ implants in the P-well, wherein each P+ guard ring surrounds an associated finger of the N-diode (p+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130 and around n+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two fingers of a P-diode comprising P+ implants in the N-well (p+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]); and
at least two N+ guard rings comprising N+ implants in the N-well, wherein each N+ guard ring surrounds an associated finger of the P-diode (n+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130 and around p+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]).

Regarding claim 2, Kaschani discloses the apparatus according to claim 1, wherein the IC substrate is a P-substrate (p+ substrate 105; Figs. 1 and 3).

Regarding claim 3, Kaschani discloses the apparatus according to claim 1, wherein further comprising shallow trench isolation (STI) between the P+ and N+ implants (isolation regions formed between n+ and p+ regions within p-well 135a of npn guard wall pocket 130 and n-well 135a of pnp guard wall pocket 130; Fig. 3).

Regarding claim 4, Kaschani discloses the apparatus according to claim 1, wherein each of the P+ guard rings are adapted for coupling to an IC ground pad (p+ implants capable of being connected to system ground terminal; Fig. 3; paragraph [0038]).

Regarding claim 6, Kaschani discloses the apparatus according to claim 4, wherein each of the N+ guard rings are adapted for coupling to an IC power pad (n+ implants capable of being connected to power supply terminal; Fig. 3; paragraph [0038]).

Regarding claim 8, Kaschani discloses the apparatus according to claim 1, wherein the N+ implants in the P-well are adapted for coupling to an IC signal pad (n+ implants capable of being connected to signal terminal; Fig. 3; paragraph [0038]).

Regarding claim 9, Kaschani discloses the apparatus according to claim 8, wherein the P+ implants in the P-well are adapted for coupling to the IC signal pad (p+ implants capable of being connected to signal terminal; Fig. 3; paragraph [0038]).

Regarding claim 10, Kaschani discloses the apparatus according to claim 9, wherein the IC signal pad is an input signal pad (signal terminal may be I/O terminal; Fig. 3; paragraph [0038]).

Regarding claim 11, Kaschani discloses the apparatus according to claim 9, wherein the IC signal pad is an output signal pad (signal terminal may be I/O terminal; Fig. 3; paragraph [0038]).

Regarding claim 12, Kaschani discloses the apparatus according to claim 9, wherein the IC signal pad is an input/output signal pad (signal terminal may be I/O terminal; Fig. 3; paragraph [0038]).

Regarding claim 13, Kaschani discloses an integrated circuit (IC) having electrostatic discharge (ESD) protection for signal inputs and signal outputs of the IC, the IC comprising:
an integrated circuit (IC) substrate having electronic circuits with signal inputs and outputs; and
at least one ESD protection circuit for each signal input and each signal output of the electronic circuits (plurality of ESD cells 200 provided on p-type substrate 105 for I/O circuitry of IC device 400; Figs. 1, 2A and 3-4; paragraphs [0020], [0025], [0036]);
wherein each one of the at least one ESD protection circuits comprises: a P-well in the IC substrate (p-well 135a in substrate 105 of npn guard wall pocket 130 of one ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well in the IC substrate (n-well 135a in substrate 105 of pnp guard wall pocket 130 of another ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well ring around the P-well and in the IC substrate (n-well ring 140a in substrate 105 and around p-well 135a of npn guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
a P-well ring around the N-well and in the IC substrate (p-well ring 140a in substrate 105 and around n-well 135a of pnp guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
at least two fingers of an N-diode comprising N+ implants in the P-well (n+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two P+ guard rings comprising P+ implants in the P-well, wherein each P+ guard ring surrounds an associated finger of the N-diode (p+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130 and around n+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two fingers of a P-diode comprising P+ implants in the N-well (p+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]); and
at least two N+ guard rings comprising N+ implants in the N-well, wherein each N+ guard ring surrounds an associated finger of the P-diode (n+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130 and around p+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]).

Regarding claim 14, Kaschani discloses the IC according to claim 13, wherein each of the P+ guard rings is coupled to an IC ground bus (p+ implants of pn diode D3 155 coupled to VSS1 ground; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).

Regarding claim 15, Kaschani discloses the IC according to claim 13, wherein each of the N+ guard rings is coupled to an IC power bus (n+ implants of pn diode D3 155 coupled to power supply VDD1/VDD2; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).

Regarding claim 16, Kaschani discloses the IC according to claim 13, wherein the N+ implants of the at least two fingers of the N-diode and the P+ implants of the at least two fingers of the P-diode are coupled to an IC signal circuit (p+ and n+ implants of pn diode D3 155 coupled to I/O terminal and functional circuitry 424; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).

Regarding claim 17, Kaschani discloses a method for forming an electrostatic discharge (ESD) protection structure for signal inputs and signal outputs of an integrated circuit (IC) (plurality of ESD cells 200 provided on p-type substrate 105 for I/O circuitry of IC device 400; Figs. 1, 2A and 3-4; paragraphs [0020], [0025], [0036]), comprising:
forming a P-well in an IC substrate (p-well 135a in substrate 105 of npn guard wall pocket 130 of one ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
forming an N-well in the IC substrate (n-well 135a in substrate 105 of pnp guard wall pocket 130 of another ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
forming the P-well with an N-well ring in the IC substrate (n-well ring 140a in substrate 105 and around p-well 135a of npn guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
forming the N-well with a P-well ring in the IC substrate (p-well ring 140a in substrate 105 and around n-well 135a of pnp guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
forming at least two fingers of an N-diode comprising N+ implants in the P-well (n+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
surrounding each of the at least two fingers with an associated P+ guard ring comprising P+ implants in the P-well (p+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130 and around n+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
forming at least two fingers of a P-diode comprising P+ implants in the N-well (p+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]); and
surrounding each of the at least two fingers of the P-diode with an associated N+ guard ring comprising N+ implants in the N-well (n+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130 and around p+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]).

Regarding claim 18, Kaschani discloses the method according to claim 17, further comprising coupling a ground bus of the IC to each of the P+ guard rings (p+ implants of pn diode D3 155 coupled to VSS1 ground; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).

Regarding claim 19, Kaschani discloses the method according to claim 17, further comprising coupling a power bus of the IC to each of the N+ guard rings (n+ implants of pn diode D3 155 coupled to power supply VDD1/VDD2; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).

Regarding claim 20, Kaschani discloses the method according to claim 17, further comprising coupling a signal circuit of the IC to the N+ implants of the at least two fingers of the N-diode and the P+ implants of the at least two fingers of the P-diode (p+ and n+ implants of pn diode D3 155 coupled to I/O terminal and functional circuitry 424; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).

Response to Arguments
Applicant’s arguments filed March 16, 2026 have been fully considered. Applicant submitted substantive amendments to claims 1, 4, 6, 13-15 and 17-19 and corresponding arguments. Examiner agrees that the 35 USC 112(b) rejection has been overcome by these amendments. However, Applicant’s remarks regarding the independent claims are merely conclusory and do not discuss any of the substance of Examiner’s current 35 USC 102 rejection of the independent claims using Kaschani. Specifically, Applicant’s arguments consist of the following: “Referring to FIG. 3 of the asserted reference Kaschani, Kaschani does not disclose the structure of a P-diode in an N-well comprising two fingers with a separate guard ring surrounding the finger and separate guard ring surrounding the finger. Likewise, the structure of an N-diode in a P-well comprising two fingers with a separate guard ring surrounding the finger and a separate guard ring surrounding the finger. Kaschani further fails to disclose an N-well ring surrounding the P-well of the two of fingers of the N-diode, and a P-well ring surrounding the N-well of the two of fingers of the P-diode. Thus, Kaschani fails to teach or suggest all the elements of independent Claim 1.” Each of these statements is conclusory and provide no additional context. Examiner would happily engage in a substantive dialogue about the merits of the present rejection, but Applicant has not provided substance to argue against. Therefore, Examiner refers Applicant back to the claim analysis provided above with regard to claims 1, 13 and 17. Further, Examiner encourages Applicant to request an interview with Examiner if Applicant still believes the current rejection of claims 1, 13 and 17 is erroneous in any way.

Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action (the minor differences that resulted in different identification using the same reference as the previous office action). Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is [phone]. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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/IAN DEGRASSE/Examiner, Art Unit 2818

/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818

Prosecution Timeline

• Jun 28, 2023: Application Filed
• Dec 18, 2025: Non-Final Rejection mailed — §102
• Mar 16, 2026: Response Filed
• Jun 03, 2026: Final Rejection mailed — §102 (current)