DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 24, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 8-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0358570 A1 to Kaschani et al. (hereinafter “Kaschani” – previously cited reference) in further view of US 2006/0267132 A1 to Lee (hereinafter “Lee” – newly cited reference).
Regarding claim 1, Kaschani discloses an apparatus for protection of integrated circuit inputs and outputs from electrostatic discharge (ESD), comprising:
an integrated circuit (IC) substrate (plurality of ESD cells 200 provided on p-type substrate 105 for I/O circuitry of IC device 400; Figs. 1, 2A and 3-4; paragraphs [0020], [0025], [0036]);
a P-well in the IC substrate (p-well 135a in substrate 105 of npn guard wall pocket 130 of one ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well in the IC substrate (n-well 135a in substrate 105 of pnp guard wall pocket 130 of another ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well ring around the P-well and in the IC substrate (n-well ring 140a in substrate 105 and around p-well 135a of npn guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
a P-well ring around the N-well and in the IC substrate (p-well ring 140a in substrate 105 and around n-well 135a of pnp guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
at least two fingers of an N-diode comprising N+ implants in the P-well (n+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two P+ guard rings comprising P+ implants in the P-well, wherein each P+ guard ring surrounds an associated finger of the N-diode (p+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130 and around n+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two fingers of a P-diode comprising P+ implants in the N-well (p+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]); and
at least two N+ guard rings comprising N+ implants in the N-well, wherein each N+ guard ring surrounds an associated finger of the P-diode (n+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130 and around p+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]).
Kaschani fails to explicitly disclose at least two disjoint P+ guard rings; and at least two disjoint N+ guard rings.
However, Kaschani already discloses more than one isolation ring of each polarity at the well level. Specifically, Kaschani discloses n-well rings and p-type guard rings which are disjoint in the sense that they enclose separate circuit blocks and do not share a single continuous wall around the whole cell.
Further, Lee discloses at least two disjoint P+ guard rings comprising P+ implants in the P-well (two P+ implants 322, 324 in P-type substrate 302 define first and second separate P+ guard rings; Figs. 3A-3B; paragraphs [0024]-[0028]); and at least two disjoint N+ guard rings comprising N+ implants in the N-well (two N+ implants 314, 316 in N-well 304 define first and second separate N+ guard rings; Figs. 3A-3B; paragraphs [0024]-[0028]).
Kaschani and Lee are both considered to be analogous to the claimed invention because they are in the same field of guard rings in a semiconductor substrate for protecting integrated circuits. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kaschani to incorporate the teaching of Lee in order to potentially provide more uniform ESD current and higher failure current, lower series resistance, independent discharge paths, better minority-carrier collection and latch-up isolation, and added circuit layout flexibility.
Regarding claim 2, Kaschani in view of Lee discloses the apparatus according to claim 1, wherein the IC substrate is a P-substrate (p+ substrate 105; Figs. 1 and 3).
Regarding claim 3, Kaschani in view of Lee discloses the apparatus according to claim 1, wherein further comprising shallow trench isolation (STI) between the P+ and N+ implants (isolation regions formed between n+ and p+ regions within p-well 135a of npn guard wall pocket 130 and n-well 135a of pnp guard wall pocket 130; Fig. 3).
Regarding claim 4, Kaschani in view of Lee discloses the apparatus according to claim 1, wherein each of the P+ guard rings are adapted for coupling to an IC ground pad (p+ implants capable of being connected to system ground terminal; Fig. 3; paragraph [0038]).
Regarding claim 6, Kaschani in view of Lee discloses the apparatus according to claim 4, wherein each of the N+ guard rings are adapted for coupling to an IC power pad (n+ implants capable of being connected to power supply terminal; Fig. 3; paragraph [0038]).
Regarding claim 8, Kaschani in view of Lee discloses the apparatus according to claim 1, wherein the N+ implants in the P-well are adapted for coupling to an IC signal pad (n+ implants capable of being connected to signal terminal; Fig. 3; paragraph [0038]).
Regarding claim 9, Kaschani in view of Lee discloses the apparatus according to claim 8, wherein the P+ implants in the P-well are adapted for coupling to the IC signal pad (p+ implants capable of being connected to signal terminal; Fig. 3; paragraph [0038]).
Regarding claim 10, Kaschani in view of Lee discloses the apparatus according to claim 9, wherein the IC signal pad is an input signal pad (signal terminal may be I/O terminal; Fig. 3; paragraph [0038]).
Regarding claim 11, Kaschani in view of Lee discloses the apparatus according to claim 9, wherein the IC signal pad is an output signal pad (signal terminal may be I/O terminal; Fig. 3; paragraph [0038]).
Regarding claim 12, Kaschani in view of Lee discloses the apparatus according to claim 9, wherein the IC signal pad is an input/output signal pad (signal terminal may be I/O terminal; Fig. 3; paragraph [0038]).
Regarding claim 13, Kaschani discloses an integrated circuit (IC) having electrostatic discharge (ESD) protection for signal inputs and signal outputs of the IC, the IC comprising:
an integrated circuit (IC) substrate having electronic circuits with signal inputs and outputs; and
at least one ESD protection circuit for each signal input and each signal output of the electronic circuits (plurality of ESD cells 200 provided on p-type substrate 105 for I/O circuitry of IC device 400; Figs. 1, 2A and 3-4; paragraphs [0020], [0025], [0036]);
wherein each one of the at least one ESD protection circuits comprises: a P-well in the IC substrate (p-well 135a in substrate 105 of npn guard wall pocket 130 of one ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well in the IC substrate (n-well 135a in substrate 105 of pnp guard wall pocket 130 of another ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
an N-well ring around the P-well and in the IC substrate (n-well ring 140a in substrate 105 and around p-well 135a of npn guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
a P-well ring around the N-well and in the IC substrate (p-well ring 140a in substrate 105 and around n-well 135a of pnp guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
at least two fingers of an N-diode comprising N+ implants in the P-well (n+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two P+ guard rings comprising P+ implants in the P-well, wherein each P+ guard ring surrounds an associated finger of the N-diode (p+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130 and around n+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
at least two fingers of a P-diode comprising P+ implants in the N-well (p+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]); and
at least two N+ guard rings comprising N+ implants in the N-well, wherein each N+ guard ring surrounds an associated finger of the P-diode (n+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130 and around p+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]).
Kaschani fails to explicitly disclose at least two disjoint P+ guard rings; and at least two disjoint N+ guard rings.
However, Kaschani already discloses more than one isolation ring of each polarity at the well level. Specifically, Kaschani discloses n-well rings and p-type guard rings which are disjoint in the sense that they enclose separate circuit blocks and do not share a single continuous wall around the whole cell.
Further, Lee discloses at least two disjoint P+ guard rings comprising P+ implants in the P-well (two P+ implants 322, 324 in P-type substrate 302 define first and second separate P+ guard rings; Figs. 3A-3B; paragraphs [0024]-[0028]); and at least two disjoint N+ guard rings comprising N+ implants in the N-well (two N+ implants 314, 316 in N-well 304 define first and second separate N+ guard rings; Figs. 3A-3B; paragraphs [0024]-[0028]).
Kaschani and Lee are both considered to be analogous to the claimed invention because they are in the same field of guard rings in a semiconductor substrate for protecting integrated circuits. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kaschani to incorporate the teaching of Lee in order to potentially provide more uniform ESD current and higher failure current, lower series resistance, independent discharge paths, better minority-carrier collection and latch-up isolation, and added circuit layout flexibility.
Regarding claim 14, Kaschani in view of Lee discloses the IC according to claim 13, wherein each of the P+ guard rings is coupled to an IC ground bus (p+ implants of pn diode D3 155 coupled to VSS1 ground; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).
Regarding claim 15, Kaschani in view of Lee discloses the IC according to claim 13, wherein each of the N+ guard rings is coupled to an IC power bus (n+ implants of pn diode D3 155 coupled to power supply VDD1/VDD2; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).
Regarding claim 16, Kaschani in view of Lee discloses the IC according to claim 13, wherein the N+ implants of the at least two fingers of the N-diode and the P+ implants of the at least two fingers of the P-diode are coupled to an IC signal circuit (p+ and n+ implants of pn diode D3 155 coupled to I/O terminal and functional circuitry 424; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).
Regarding claim 17, Kaschani discloses a method for forming an electrostatic discharge (ESD) protection structure for signal inputs and signal outputs of an integrated circuit (IC) (plurality of ESD cells 200 provided on p-type substrate 105 for I/O circuitry of IC device 400; Figs. 1, 2A and 3-4; paragraphs [0020], [0025], [0036]), comprising:
forming a P-well in an IC substrate (p-well 135a in substrate 105 of npn guard wall pocket 130 of one ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
forming an N-well in the IC substrate (n-well 135a in substrate 105 of pnp guard wall pocket 130 of another ESD cell 200, where each ESD cell may have an npn guard wall pocket or a pnp guard wall pocket; Figs. 1 and 4; paragraphs [0018], [0020], [0022], [0036], [0043]-[0044]);
forming the P-well with an N-well ring in the IC substrate (n-well ring 140a in substrate 105 and around p-well 135a of npn guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
forming the N-well with a P-well ring in the IC substrate (p-well ring 140a in substrate 105 and around n-well 135a of pnp guard wall pocket 130; Fig. 1; paragraphs [0018], [0020], [0022], [0043]-[0044]);
forming at least two fingers of an N-diode comprising N+ implants in the P-well (n+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
surrounding each of the at least two fingers of the N-diode with an associated P+ guard ring comprising P+ implants in the P-well (p+ implants of pn diode D3 155 in p-well 135a of npn guard wall pocket 130 and around n+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]);
forming at least two fingers of a P-diode comprising P+ implants in the N-well (p+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]); and
surrounding each of the at least two fingers of the P-diode with an associated N+ guard ring comprising N+ implants in the N-well (n+ implants of pn diode D3 155 in n-well 135a of pnp guard wall pocket 130 and around p+ implants; Fig. 3; paragraphs [0021]-[0022], [0028], [0043]-[0044]).
Kaschani fails to explicitly disclose a pair of disjoint P+ guard rings; and a pair of disjoint N+ guard rings.
However, Kaschani already discloses more than one isolation ring of each polarity at the well level. Specifically, Kaschani discloses n-well rings and p-type guard rings which are disjoint in the sense that they enclose separate circuit blocks and do not share a single continuous wall around the whole cell.
Further, Lee discloses a pair of disjoint P+ guard rings comprising P+ implants in the P-well (two P+ implants 322, 324 in P-type substrate 302 define first and second separate P+ guard rings; Figs. 3A-3B; paragraphs [0024]-[0028]); and a pair of disjoint N+ guard rings comprising N+ implants in the N-well (two N+ implants 314, 316 in N-well 304 define first and second separate N+ guard rings; Figs. 3A-3B; paragraphs [0024]-[0028]).
Kaschani and Lee are both considered to be analogous to the claimed invention because they are in the same field of guard rings in a semiconductor substrate for protecting integrated circuits. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kaschani to incorporate the teaching of Lee in order to potentially provide more uniform ESD current and higher failure current, lower series resistance, independent discharge paths, better minority-carrier collection and latch-up isolation, and added circuit layout flexibility.
Regarding claim 18, Kaschani in view of Lee discloses the method according to claim 17, further comprising coupling a ground bus of the IC to each of the P+ guard rings (p+ implants of pn diode D3 155 coupled to VSS1 ground; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).
Regarding claim 19, Kaschani in view of Lee discloses the method according to claim 17, further comprising coupling a power bus of the IC to each of the N+ guard rings (n+ implants of pn diode D3 155 coupled to power supply VDD1/VDD2; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).
Regarding claim 20, Kaschani in view of Lee discloses the method according to claim 17, further comprising coupling a signal circuit of the IC to the N+ implants of the at least two fingers of the N-diode and the P+ implants of the at least two fingers of the P-diode (p+ and n+ implants of pn diode D3 155 coupled to I/O terminal and functional circuitry 424; Figs. 3-4; paragraphs [0021]-[0022], [0028], [0038], [0043]-[0044]).
Response to Arguments
Applicant’s arguments filed August 24, 2026 have been fully considered. Applicant submitted substantive amendments to claims 1, 13 and 17 along with corresponding arguments. Examiner agrees that Kaschani alone does not explicitly disclose multiple P+ and N+ separate guard rings. However, after additional search, amended claims 1, 13 and 17 have been rejected on new grounds as being disclosed by Kaschani in view of Lee as outlined above.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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