DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 25, 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liaw (US 2020/0105761 A1).
Claim 1, Liaw discloses an integrated circuit structure (device 600 and 700 are an integrated circuit structure, hereinafter, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C), comprising:
a first vertical stack of horizontal nanowires (stack of semiconductor layers 615S are a first vertical stack of horizontal nanowires, hereinafter, first vertical stack of horizontal nanowires 615S, [0062], Fig. 6B) having a first lateral width (first vertical stack of horizontal nanowires 615S has channel width W1 which is a first lateral width, hereinafter, first lateral width W1, [0062], Fig. 6B) along a direction (i.e. y-direction) (first lateral width W1 is along the y-direction, [0062], Fig. 6B);
a first gate electrode (gate structures 630S/630S’ of the gate electrodes 685 are a first gate electrode, hereinafter, first gate electrode 630S/630S’, [0063], Figs. 6A and 6B) over the first vertical stack of horizontal nanowires 615S (first gate electrode 630S/630S’ are over the first vertical stack of horizontal nanowires 615S, [0063], Figs. 6A and 6B), the first gate electrode 685_S having a second lateral width (first gate electrode 630S/630S’ has the first height H1 which is a second lateral width, hereinafter, second lateral width H1, [0066], Fig. 6B) along the direction (i.e. y-direction) (second lateral width H1 is along the y-direction, [0066], Fig. 6B);
a second vertical stack of horizontal nanowires (stack of semiconductor layers 615W are a second vertical stack of horizontal nanowires, hereinafter, second vertical stack of horizontal nanowires 615W, [0062], Fig. 6B) laterally spaced apart from the first vertical stack of horizontal nanowires 615S (second vertical stack of horizontal nanowires 615W are laterally spaced apart from the first vertical stack of horizontal nanowires 615S, [0062], Fig. 6B), the second vertical stack of horizontal nanowires 615W having a third lateral width (second vertical stack of horizontal nanowires 615W has channel width W2 which is a third lateral width, hereinafter, third lateral width W2, [0062], Fig. 6B) along the direction (i.e. y-direction) (third lateral width W2 is along the y-direction, [0062], Fig. 6B), the third lateral width W2 less than the first lateral width W1 (third lateral width W2 less than the first lateral width W1, 0062], Fig. 6B);
a second gate electrode (gate structures 630W/630W’ of the gate electrodes 685 are a second gate electrode, hereinafter, second gate electrode 630W/630W’, [0063], Figs. 6A and 6B) over the second vertical stack of horizontal nanowires 615W (second gate electrode 630W/630W’ is over the second vertical stack of horizontal nanowires 615W, [0063], Figs. 6A and 6B), the second gate electrode 630W/630W’ laterally spaced apart from the first gate electrode 630S/630S’ (second gate electrode 630W/630W’ laterally spaced apart from the first gate electrode 630S/630S’, [0065], Figs. 6A and 6B), and the second gate electrode 630W/630W’ having a fourth lateral width (second gate electrode 630W/630W’ has the second height H2 which is a fourth lateral width, hereinafter, fourth lateral width H2, [0066], Fig. 6B) along the direction (i.e. y-direction) (fourth lateral width H2 is along the y-direction, [0066], Fig. 6B), the fourth lateral width H2 less than the second lateral width H1 (fourth lateral width H2 less than the second lateral width H1, [0066], Figs. 6A and 6B).
Claim 2, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 1.
Liaw discloses further comprising a dielectric plug (gate end dielectric structures 640 is a dielectric plug, hereinafter, dielectric plug 640, [0063], Fig. 6B) laterally between the first gate electrode 630S/630S’ and the second gate electrode 630W/630W’ (dielectric plug 640 is laterally between the first gate electrode 630S/630S’ and the second gate electrode 630W/630W’, [0063], Fig. 6B).
Claim 3, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 1.
Liaw discloses further comprising a first sub-fin (P-type fins 735P are a first sub-fin, hereinafter, first sub-fin 735P may be formed in combination with integrated circuit structure 600 and may be stacked, [0079], Fig. 7B) beneath the first vertical stack of horizontal nanowires 615S (first sub-fin 735P may be stacked beneath the first vertical stack of horizontal nanowires 615S, [0062], Fig. 6B), and a second sub-fin (N-type fins 735N are a second sub-fin, hereinafter, second sub-fin 735N may be formed in combination with integrated circuit structure 600 and may be stacked, [0079], Fig. 7B) beneath the second vertical stack of horizontal nanowires (second vertical stack of horizontal nanowires 615W, [0062], Fig. 6B).
Claim 4, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 1.
Liaw discloses further comprising a first insulating gate cap above the first gate electrode 630S/630S’ (hard mask 680 is an insulating gate cap and is above the first gate electrode 630S/630S’, hereinafter, first insulating gate cap 680S, [0064], Figs. 6B and 6C), and a second insulating gate cap above the second gate electrode (hard mask 680 is an insulating gate cap and is above the second gate electrode 630W/630W’, hereinafter, second insulating gate cap 680W, [0064], Figs. 6B and 6C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw.
Claim 6, Liaw discloses an integrated circuit structure (device 600 and 700 are an integrated circuit structure, hereinafter, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C), comprising:
a first fin (P-type fins 735P are a first fin, hereinafter, first fin 735P, [0079], Fig. 7B) having a first lateral width (first fin 735P has a width W3 which is a first lateral width, hereinafter, first lateral width W3P, [0079], Fig. 7B) along a direction (i.e. y-direction) (first lateral width W3 is along the y-direction, [0079], Fig. 7B);
a first gate electrode (gate electrode 785P is a first gate electrode, hereinafter, first gate electrode 785P, [0083], Fig. 7B) over the first fin 735P, the first gate electrode 785P having a second lateral width (first gate electrode 785P has a width of half of H3, hereinafter, second lateral width H3P, [0081], Fig. 7B) along the direction (i.e. y-direction) (second lateral width H3P is along the y-direction, [0081], Fig. 7B);
a second fin (N-type fins 735N are a second fin, hereinafter, second fin 735N, [0079], Fig. 7B) laterally spaced apart from the first fin 735P, the second fin 735N having a third lateral width (second fin 735N has a width W3 which is a third lateral width, hereinafter, third lateral width W3N, [0079], Fig. 7B) along the direction (i.e. y-direction) (third lateral width W3N is along the y-direction, [0079], Fig. 7B), the third lateral width W3N less than the first lateral width W3P (third lateral width W3N may be less than the first lateral width W3P, [0079], Fig. 7B);
a second gate electrode (gate electrode 785N is a second gate electrode, hereinafter, second gate electrode 785N, [0083], Fig. 7B) over the second fin 735N (second gate electrode 785N is over the second fin 735N, [0083], Fig. 7B), the second gate electrode 785N laterally spaced apart from the first gate electrode 785P (second gate electrode 785N laterally spaced apart from the first gate electrode 785P, [0083], Fig. 7B), and the second gate electrode 785N having a fourth lateral width (second gate electrode 785P has a width of half of H3, hereinafter, fourth lateral width H3P, [0081], Fig. 7B) along the direction (i.e. y-direction) (fourth lateral width H3P is along the y-direction, [0081], Fig. 7B).
Liaw does not explicitly disclose the fourth lateral width less than the second lateral width.
However, Liaw discloses the fourth lateral width less than the second lateral width (height H1 may be equivalent to the fourth lateral width, hereinafter, fourth lateral width H13P and height H2 may be equivalent to the second lateral width, hereinafter, second lateral width H13N, wherein the fourth lateral width H13P is less than the second lateral width H13N, [0081], Figs. 6B and 7B). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of fourth lateral width to second lateral width (result effective at least insofar as lateral width of the adjacent overlying gate electrodes ensures that the resultant gate length of the FinFETs is at least 1.5 times of the gate length of the GAA transistors (Liaw, [0081])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed fourth lateral width to second lateral width or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 7, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 6.
Liaw discloses further comprising a dielectric plug (gate end dielectric structures 640 is a dielectric plug, hereinafter, dielectric plug 640, [0063], Figs. 6B and 7B) laterally between the first gate electrode 785P and the second gate electrode 785N (dielectric plug 640 is laterally between the first gate electrode 785P and the second gate electrode 785N, [0063], Figs. 6B and 7B).
Claim 8, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 6.
Liaw discloses further comprising a first sub-fin (P-type fins 735P are a first sub-fin, hereinafter, first sub-fin 735_P may be formed in combination with integrated circuit structure 600/700 and may be stacked, [0079], Fig. 7B) beneath the first fin 735P (first sub-fin 735_P may be formed beneath the first fin 735P, [0079], Fig. 7B), and a second sub-fin (N-type fins 735N are a second sub-fin, hereinafter, second sub-fin 735_N may be formed in combination with integrated circuit structure 600/700 and may be stacked, [0079], Fig. 7B) beneath the second fin 735N (second sub-fin 735_N may be formed beneath the second fin 735N, [0079], Fig. 7B).
Claim 9, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 6.
Liaw discloses further comprising a first insulating gate cap above the first gate electrode 785P (first gate electrode 785P may further include a first insulating gate capping layer, hereinafter, first insulating gate cap 680P, [0086], Figs. 6B and 7B), and a second insulating gate cap above the second gate electrode 785N (second gate electrode 785N may further include a second insulating gate capping layer, hereinafter, second insulating gate cap 680N, [0086], Figs. 6B and 7B).
Claims 5 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Sung (US 2022/0310818 A1).
Claim 5, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 4.
Liaw does not explicitly disclose wherein the first gate electrode is not laterally recessed beneath the first insulating gate cap, and wherein the second gate electrode is laterally recessed beneath the second insulating gate cap.
However, Sung discloses wherein the first gate electrode is not laterally recessed beneath the first insulating gate cap (Sung, first gate electrode 708 is not laterally recessed beneath the first insulating gate cap 714, [0063], Fig. 7C; Liaw, first gate electrode 630S/630S’ and first insulating gate cap 680S, [0064], Figs. 6B and 6C), and wherein the second gate electrode is laterally recessed beneath the second insulating gate cap (Sung, second gate electrode 708 is laterally recessed beneath the second insulating gate cap 744, [0061], Fig. 7C; Liaw, second gate electrode 630W/630W’ and second insulating gate cap 680W, [0064], Figs. 6B and 6C). The combination to utilize various geometries of the gate electrodes with respect to their above lying cap layer would improve registration budget and patterning or resolution improvements to enable shrinkage of both endcap dimension and endcap-to-endcap spacing (Sung, [0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize various geometries of the gate electrodes with respect to their above lying cap layer to improve registration budget and patterning or resolution improvements to enable shrinkage of both endcap dimension and endcap-to-endcap spacing (Sung, [0034]).
Claim 10, Liaw discloses the integrated circuit structure (integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C) of claim 9.
Liaw does not explicitly disclose wherein the first gate electrode is not laterally recessed beneath the first insulating gate cap, and wherein the second gate electrode is laterally recessed beneath the second insulating gate cap.
However, Sung discloses wherein the first gate electrode is not laterally recessed beneath the first insulating gate cap (Sung, first gate electrode 708 is not laterally recessed beneath the first insulating gate cap 714, [0063], Fig. 7C; Liaw, first gate electrode 785P and first insulating gate cap 680P, [0064], Figs. 6B and 6C), and wherein the second gate electrode is laterally recessed beneath the second insulating gate cap (Sung, second gate electrode 708 is laterally recessed beneath the second insulating gate cap 744, [0061], Fig. 7C; Liaw, second gate electrode 785N and second insulating gate cap 680N, [0064], Figs. 6B and 6C). The combination to utilize various geometries of the gate electrodes with respect to their above lying cap layer would improve registration budget and patterning or resolution improvements to enable shrinkage of both endcap dimension and endcap-to-endcap spacing (Sung, [0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize various geometries of the gate electrodes with respect to their above lying cap layer to improve registration budget and patterning or resolution improvements to enable shrinkage of both endcap dimension and endcap-to-endcap spacing (Sung, [0034]).
Claim 11, Sung discloses a computing device (computing device 1000, [0109], Fig. 10), comprising:
a board (board 1002, [0109], Fig. 10); and
a component (processor 1004 is a component, hereinafter, component 1004, [0109], Fig. 10) coupled to the board 1002 (component 1004 is coupled to the board 1002, [0109], Fig. 10).
Sung does not explicitly disclose the component including an integrated circuit structure, comprising: a first vertical stack of horizontal nanowires or a first fin having a first lateral width along a direction; a first gate electrode over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width along the direction; a second vertical stack of horizontal nanowires or a second fin laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width along the direction, the third lateral width less than the first lateral width; a second gate electrode over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width along the direction, the fourth lateral width less than the second lateral width.
However, Liaw discloses the component including an integrated circuit structure (Sung, computing device 1000, [0109], Fig. 10; Liaw, device 600 and 700 are an integrated circuit structure, hereinafter, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C), comprising:
a first vertical stack of horizontal nanowires (Liaw, stack of semiconductor layers 615S are a first vertical stack of horizontal nanowires, hereinafter, first vertical stack of horizontal nanowires 615S, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) or a first fin having a first lateral width (Liaw, first vertical stack of horizontal nanowires 615S has channel width W1 which is a first lateral width, hereinafter, first lateral width W1, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) along a direction (i.e. y-direction) (Liaw, first lateral width W1 is along the y-direction, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10);
a first gate electrode (Liaw, gate structures 630S/630S’ of the gate electrodes 685 are a first gate electrode, hereinafter, first gate electrode 630S/630S’, [0063], Figs. 6A and 6B; Sung, computing device 1000, [0109], Fig. 10) over the first vertical stack of horizontal nanowires 615S (Liaw, first gate electrode 630S/630S’ are over the first vertical stack of horizontal nanowires 615S, [0063], Figs. 6A and 6B; Sung, computing device 1000, [0109], Fig. 10) or the first fin, the first gate electrode 685_S having a second lateral width (Liaw, first gate electrode 630S/630S’ has the first height H1 which is a second lateral width, hereinafter, second lateral width H1, [0066], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) along the direction (i.e. y-direction) (Liaw, second lateral width H1 is along the y-direction, [0066], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10);
a second vertical stack of horizontal nanowires (Liaw, stack of semiconductor layers 615W are a second vertical stack of horizontal nanowires, hereinafter, second vertical stack of horizontal nanowires 615W, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) or a second fin laterally spaced apart from the first vertical stack of horizontal nanowires 615S (Liaw, second vertical stack of horizontal nanowires 615W are laterally spaced apart from the first vertical stack of horizontal nanowires 615S, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) or the second fin, the second vertical stack of horizontal nanowires 615W having a third lateral width (Liaw, second vertical stack of horizontal nanowires 615W has channel width W2 which is a third lateral width, hereinafter, third lateral width W2, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) along the direction (i.e. y-direction) (Liaw, third lateral width W2 is along the y-direction, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10), the third lateral width W2 less than the first lateral width W1 (Liaw, third lateral width W2 less than the first lateral width W1, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10);
a second gate electrode (Liaw, gate structures 630W/630W’ of the gate electrodes 685 are a second gate electrode, hereinafter, second gate electrode 630W/630W’, [0063], Figs. 6A and 6B; Sung, computing device 1000, [0109], Fig. 10) over the second vertical stack of horizontal nanowires 615W (Liaw, second gate electrode 630W/630W’ is over the second vertical stack of horizontal nanowires 615W, [0063], Figs. 6A and 6B; Sung, computing device 1000, [0109], Fig. 10) or the second fin, the second gate electrode 630W/630W’ laterally spaced apart from the first gate electrode 630S/630S’ (Liaw, second gate electrode 630W/630W’ laterally spaced apart from the first gate electrode 630S/630S’, [0065], Figs. 6A and 6B; Sung, computing device 1000, [0109], Fig. 10), and the second gate electrode 630W/630W’ having a fourth lateral width (Liaw, second gate electrode 630W/630W’ has the second height H2 which is a fourth lateral width, hereinafter, fourth lateral width H2, [0066], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) along the direction (i.e. y-direction) (Liaw, fourth lateral width H2 is along the y-direction, [0066], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10), the fourth lateral width H2 less than the second lateral width H1 (Liaw, fourth lateral width H2 less than the second lateral width H1, [0066], Figs. 6A and 6B; Sung, computing device 1000, [0109], Fig. 10).
Claim 12, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses comprising the first vertical stack of horizontal nanowires (Liaw, stack of semiconductor layers 615S are a first vertical stack of horizontal nanowires, hereinafter, first vertical stack of horizontal nanowires 615S, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10) and the second vertical stack of horizontal nanowires (Liaw, stack of semiconductor layers 615W are a second vertical stack of horizontal nanowires, hereinafter, second vertical stack of horizontal nanowires 615W, [0062], Fig. 6B; Sung, computing device 1000, [0109], Fig. 10).
Claim 13, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses comprising the first fin (Liaw, P-type fins 735P are a first fin, hereinafter, first fin 735P, [0079], Fig. 7B; Sung, computing device 1000, [0109], Fig. 10) and the second fin (Liaw, N-type fins 735N are a second fin, hereinafter, second fin 735N, [0079], Fig. 7B; Sung, computing device 1000, [0109], Fig. 10).
Claim 14, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses further comprising:
a memory coupled to the board (Sung, board 1002 may include components such as memory (i.e. volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and/or flash memory), [0110], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Claim 15, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses further comprising:
a communication chip coupled to the board (Sung, board 1002 may include a communication chip 1006, [0111], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Claim 16, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses wherein the component is a packaged integrated circuit die (Sung, board 1002 may include processor 1004 which includes a packaged integrated circuit die, [0112], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Claim 17, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses further comprising:
a battery coupled to the board (Sung, board 1002 may include a battery, [0110], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Claim 18, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses further comprising:
a display coupled to the board (Sung, board 1002 may include a display, [0110], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Claim 19, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses further comprising:
a camera coupled to the board (Sung, board 1002 may include a camera, [0110], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Claim 20, Liaw/Sung discloses the computing device (Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C; Sung, computing device 1000, [0109], Fig. 10) of claim 11.
Liaw/Sung discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Sung, board 1002 may include a component which is selected from the group consisting of a processor 1004, a communications chip 1006, and a digital signal processor, [0109] and [0110], Fig. 10; Liaw, integrated circuit structure 600/700, [0057] and [0077], Figs. 6A-6C).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xie (US 2023/0178553 A1) discloses an integrated circuit structure (Figs. 25A-25C), comprising:
a first vertical stack of horizontal nanowires 106/166 having a first lateral width along a direction; a first gate electrode 166 over the first vertical stack of horizontal nanowires 106/166, the first gate electrode 166 having a second lateral width along the direction; a second vertical stack of horizontal nanowires 106/165 laterally spaced apart from the first vertical stack of horizontal nanowires 106/166, the second vertical stack of horizontal nanowires 106/165 having a third lateral width along the direction; a second gate electrode 165 over the second vertical stack of horizontal nanowires 106/165, the second gate electrode 165 laterally spaced apart from the first gate electrode 166, and the second gate electrode 165 having a fourth lateral width along the direction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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