DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 5/6/26.
Applicant’s amendment to claims 1 and 4 is acknowledged.
Applicant’s addition of new claims 10-12 is acknowledged.
Claims 1-12 are pending and claims 3, 5 and 7 are withdrawn.
Claims 1, 2, 4, 6 and 8-12 are subject to examination at this time.
Response to Arguments
Applicant's arguments filed 5/6/26 have been fully considered but they are not persuasive. With a new interpretation, Uchida teaches the amended limitations as set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 6 and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida, JP 2021027145 A (see attached English machine translation) in view of Teshima et al., US Publication No. 2011/0006718 A1 (from the IDS).
In a first interpretation-
Uchida teaches
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1. A semiconductor device comprising (see fig. 5 annotated above; also see figs. 3-4 and 7-8):
an isolation circuit board (160);
a semiconductor chip (60, 70) provided on one main surface of the isolation circuit board;
a first external terminal (150) having a main surface and including a first snubber connecting portion (153) rising from the main surface of the first external terminal, the first external terminal (150) being electrically connected to the semiconductor chip (60, 70);
a second external terminal (140) placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal (150), and including a second snubber connecting portion (143) rising from the main surface of the second external terminal, the second external terminal (140) being electrically connected to the semiconductor chip (60, 70);
a capacitor (211, 221 of 200 in fig. 8) having a first end (203) connected to the first snubber connecting portion (153) and a second end (202) connected to the second snubber connecting portion (143); …and
a case (110) inside which the semiconductor chip (60, 70) is stored and to which the first external terminal (150) and the second external terminal (140) are attached,
wherein
the first external terminal (150) has a first main body portion (151) and a first projecting portion extending (e.g. vertical sidewall of 150 annotated in fig. 5) from the first main body portion in a first direction (e.g. vertical direction),
the second external terminal (140) has a second main body portion (141) and a second projecting portion (e.g. vertical sidewall annotated of 140 in fig. 5) extending from the second main body portion in the first direction (e.g. vertical direction),
the first snubber connecting portion (153) rises from a side of the first projecting portion (e.g. vertical sidewall of 150) facing the second projecting portion (e.g. vertical sidewall of 140) in a second direction (e.g. horizontal direction) perpendicular to the first direction, and
the second snubber connecting portion (143) rises from a side of the second projecting portion (e.g. vertical sidewall of 140) facing the first projecting portion (e.g. vertical sidewall of 150) in the second direction (e.g. horizontal direction). See Uchida at Abstract and English machine translation pages 5-8.
Regarding claim 1:
Uchida does not expressly teach:
a seal member sealing the semiconductor chip;
In an analogous art, Teshima teaches:
a seal member (12) sealing semiconductor chips (25-28), fig. 1, para. [0039].
Uchida further teaches:
2. The semiconductor device according to claim 1, wherein
the first snubber connecting portion (153) and the second snubber connecting portion (143) extend in a direction perpendicular to the main surface of the first external terminal (150), and
a distance (D2 in fig. 5 annotated above) by which the first snubber connecting portion (153) and the second snubber connecting portion (143) are distanced from each other is larger than a distance by which the first external terminal (150) and the second external terminal (140) are distanced (D1) from each other, fig. 5.
4. The semiconductor device according to claim 1, wherein the first snubber connecting portion (153) and the second snubber connecting portion (143) have the same height, fig. 5.
Regarding claim 6:
Teshima further teaches wherein the capacitor (22) is provided inside the seal member (12), fig. 1, para. [0039].
One of ordinary skill in the art modifying Uchida with Teshima would form wherein the capacitor (211, 221 of 200 in fig. 8) is provided inside the seal member because the capacitor is disposed inside (112) the case (110). See Uchida at Abstract,
Uchida further teaches:
8. The semiconductor device according to claim 1, wherein
the semiconductor chip (60, 70) includes a first main electrode and a second main electrode (e.g. In fig. 4, main electrodes coupled to 162 or 162 and also main electrodes coupled by wires 166, 167.),
the isolation circuit board (160) includes an insulating plate having one main surface on which a first electrically-conductive plate electrically connected to the second main electrode and a second electrically-conductive plate electrically connected to the first main electrode are placed (e.g. For chip 60, the main electrodes are coupled to electrically-conductive plates 161, 163. For chip 70, the main electrodes are coupled to electrically-conductive plates 162, 163.),
the first external terminal (150) is electrically connected to the first electrically-conductive plate (163) and
the second external terminal (140) is electrically connected to the second electrically-conductive plate (162), figs. 4-5.
Regarding claim 9:
One of ordinary skill in the art modifying Uchida with Teshima would form an insulating sheet such as the sealing resin placed between (e.g. See Uchida’s fig. 7) the first external terminal (150) and the second external terminal (140) because the sealing resin fills the space inside case (111).
10. The semiconductor device according to claim 1, wherein the second external terminal (140) includes a stepped portion (e.g. stepped portion annotated in fig. 5) so that the second projecting portion has a horizontal level (142) corresponding to a horizontal level (152) of the first projecting portion (e.g. In claim 1, if the second projecting portion and the first projecting portion are interpreted to include additional portions 152 and 142, respectively, then a horizontal level 142 corresponds to a horizontal level 152.)
11. The semiconductor device according to claim 1, (see fig. 5 annotated above) wherein a distance (D2) between the first snubber connecting portion (153) and the second snubber connecting portion (143) in the second direction is greater than a distance (D1) between the first projecting portion (e.g. vertical sidewall of 150) and the second projecting portion (e.g. vertical sidewall of 140) in the second direction.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Uchida with the teachings of Teshima because the resin mold layer 12 firmly fixes the substrate to the module case 11. See Teshima at para. [0039].
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida, JP 2021027145 A (see attached English machine translation) in view of Teshima et al., US Publication No. 2011/0006718 A1 (from the IDS).
In a second interpretation-
Uchida teaches
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Limitations from claims 1 and 4:
A semiconductor device comprising (see fig. 5 annotated above; also see figs. 3-4 and 7-8):
an isolation circuit board (160);
a semiconductor chip (60, 70) provided on one main surface of the isolation circuit board;
a first external terminal (150) having a main surface and including a first snubber connecting portion (153) rising from the main surface of the first external terminal, the first external terminal (150) being electrically connected to the semiconductor chip (60, 70);
a second external terminal (130) placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal (150), and including a second snubber connecting portion (133) rising from the main surface of the second external terminal, the second external terminal (130) being electrically connected to the semiconductor chip (60, 70);
a capacitor (211, 221 of 200 in fig. 8) having a first end (203) connected to the first snubber connecting portion (153) and a second end (201) connected to the second snubber connecting portion (133); …and
a case (110) inside which the semiconductor chip (60, 70) is stored and to which the first external terminal (150) and the second external terminal (130) are attached,
wherein
the first external terminal (150) has a first main body portion (151) and a first projecting portion extending (e.g. vertical sidewall of 150 annotated in fig. 5) from the first main body portion in a first direction (e.g. vertical direction),
the second external terminal (130) has a second main body portion (131) and a second projecting portion (e.g. vertical sidewall annotated of 130 in fig. 5) extending from the second main body portion in the first direction (e.g. vertical direction),
the first snubber connecting portion (153) rises from a side of the first projecting portion (e.g. vertical sidewall of 150) facing the second projecting portion (e.g. vertical sidewall of 130) in a second direction (e.g. horizontal direction) perpendicular to the first direction, and
the second snubber connecting portion (133) rises from a side of the second projecting portion (e.g. vertical sidewall of 130) facing the first projecting portion (e.g. vertical sidewall of 150) in the second direction (e.g. horizontal direction),
(see fig. 7) wherein the first snubber connecting portion (153) and the second snubber connecting portion (133) have a same height. See Uchida at Abstract and English machine translation pages 5-8.
:
Uchida does not expressly teach:
a seal member sealing the semiconductor chip;
In an analogous art, Teshima teaches:
a seal member (12) sealing semiconductor chips (25-28), fig. 1, para. [0039].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Uchida with the teachings of Teshima because the resin mold layer 12 firmly fixes the substrate to the module case 11. See Teshima at para. [0039].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida, as applied to claim 1 above, in view of Egusa, US Publication No. 2024/0162122 A1.
Regarding claim 9:
Uchida teaches all the limitations of claim 1 above, and in an alternative interpretation of claim 9 the reference Egusa is being introduced.
In an analogous art, Egusa teaches:
an insulating sheet (e.g. “insulating paper” placed between the first external terminal and the second external terminal (e.g. terminals 18a, 18b, 18c). See Egusa at para. [0086], fig. 7.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Uchida with the teachings of Egusa to prevent the terminals from short-circuiting.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida, as applied to claim 1 above, in view of Nakano, US Publication No. 2020/0006237 A1.
Regarding claim 12:
Uchida teaches all the limitations of claim 1 above and further teaches:
(e.g. see figs. 3 and 8-9) wherein snubber module 200 comprising capacitors 211, 221 is mounted directly right above uppers ends of the first snubber connecting portion 153 and the second snubber connecting portion 143.
Uchida does not expressly teach:
wherein the capacitor is provided right above respective upper ends of the first snubber connecting portion and the second snubber connecting portion.
In an analogous art, Nakano teaches:
(see fig. 3A) wherein the capacitor (52) is provided right above an upper end of the snubber connecting portion (32a). See Nakano at para. [0080] – [0091].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Uchida with the teachings of Nakano to form “the capacitor right above respective upper ends of the first snubber connecting portion and the second snubber connecting portion” because “the degree of freedom for the wiring is improved”. See Nakano at para. [0081].
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nakano, US 20200006237 A1 (from the IDS). Nakano in fig. 3A teaches snubber (52 +54) connected to connecting portions (32a, 32b).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
17 July 2026
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