DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species (a1) fig. 7, (b1) figs. 5-6, claims 1, 2, 4, 6, 8 and 9 in the reply filed on 11/10/25 is acknowledged.
Claims 3, 5 and 7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/10/25.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 6, 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida, JP 2021027145 A (see attached English machine translation) in view of Teshima et al., US Publication No. 2011/0006718 A1 (from the IDS).
Uchida teaches:
1. A semiconductor device comprising (see figs. 3-5 and 7-8):
an isolation circuit board (160);
a semiconductor chip (60, 70) provided on one main surface of the isolation circuit board;
a first external terminal (150 or 140) having a main surface and including a first snubber connecting portion (153 or 143) rising from the main surface of the first external terminal, the first external terminal (150 or 140) being electrically connected to the semiconductor chip (60, 70);
a second external terminal (130) placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal (150 or 140), and including a second snubber connecting portion (133) rising from the main surface of the second external terminal, the second external terminal (130) being electrically connected to the semiconductor chip (60, 70);
a capacitor (211, 221 of 200 in fig. 8) having one end connected to the first snubber connecting portion (153 or 143) and the other end connected to the second snubber connecting portion (133); …and
a case (110) inside which the semiconductor chip (60, 70) is stored and to which the first external terminal (150 or 140) and the second external terminal (130) are attached. See Uchida at Abstract and English machine translation pages 5-8.
Regarding claim 1:
Uchida does not expressly teach:
a seal member sealing the semiconductor chip;
In an analogous art, Teshima teaches:
a seal member (12) sealing semiconductor chips (25-28), fig. 1, para. [0039].
Uchida further teaches:
2. The semiconductor device according to claim 1, wherein
the first snubber connecting portion (e.g. interpreted as 143 in claim 1) and the second snubber connecting portion (133) extend in a direction perpendicular to the main surface of the first external terminal (e.g. interpreted as 140), and
a distance by which the first snubber connecting portion (e.g. interpreted as 143) and the second snubber connecting portion (133) are distanced from each other is larger than a distance by which the first external terminal (140) and the second external terminal (130) are distanced from each other, fig. 5.
4. The semiconductor device according to claim 1, wherein the first snubber connecting portion (e.g. interpreted as 143 in claim 1) and the second snubber connecting portion (133) have the same height, fig. 5.
Regarding claim 6:
Teshima further teaches wherein the capacitor (22) is provided inside the seal member (12), fig. 1, para. [0039].
One of ordinary skill in the art modifying Uchida with Teshima would form wherein the capacitor (211, 221 of 200 in fig. 8) is provided inside the seal member because the capacitor is disposed inside (112) the case (110). See Uchida at Abstract,
Uchida further teaches:
8. The semiconductor device according to claim 1, wherein
the semiconductor chip (60, 70) includes a first main electrode and a second main electrode (e.g. In fig. 4, main electrodes coupled to 162 or 162 and also main electrodes coupled by wires 166, 167.),
the isolation circuit board (160) includes an insulating plate having one main surface on which a first electrically-conductive plate electrically connected to the second main electrode and a second electrically-conductive plate electrically connected to the first main electrode are placed (e.g. For chip 60, the main electrodes are coupled to electrically-conductive plates 161, 163. For chip 70, he main electrodes are coupled to electrically-conductive plates 162, 163.),
the first external terminal is electrically connected to the first electrically-conductive plate (e.g. The first external terminal 150, 140 is electrically connected to 163, 161, respectively.) and
the second external terminal (130) is electrically connected to the second electrically-conductive plate (162), figs. 4-5.
Regarding claim 9:
One of ordinary skill in the art modifying Uchida with Teshima would form an insulating sheet such as the sealing resin placed between (e.g. See Uchida’s fig. 7) the first external terminal (150 or 140) and the second external terminal (130) because the sealing resin fills the space inside case (111).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Uchida with the teachings of Teshima because the resin mold layer 12 firmly fixes the substrate to the module case 11. See Teshima at para. [0039].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchida, as applied to claim 1 above, in view of Egusa, US Publication No. 2024/0162122 A1.
Regarding claim 9:
Uchida teaches all the limitations of claim 1 above, and in an alternative interpretation of claim 9 the reference Egusa is being introduced.
In an analogous art, Egusa teaches:
an insulating sheet (e.g. “insulating paper” placed between the first external terminal and the second external terminal (e.g. terminals 18a, 18b, 18c). See Egusa at para. [0086], fig. 7.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Uchida with the teachings of Egusa to prevent the terminals from short-circuiting.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
15 January 2026