DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 8, 13 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (2020/0343223).
Regarding claim 1, Chen (Fig. 2E) discloses a semiconductor package comprising: a lower redistribution structure RDL1 ([0028]) comprising an insulating layer DI1 ([0029]), a connection pad CD1 ([0028]) and an upper pad 206 ([Fig. 1F, [0019]), wherein the connection pad CD1 and the upper pad 106/206 are disposed on an upper surface of the insulating layer DI1, 304; a semiconductor chip 200/100 mounted on the lower redistribution structure RDL1 and connected to the upper pad 106 ([0019]); a conductive post 306 disposed on the connection pad CD1 ([0031]); at least one dummy post 110 disposed on the lower redistribution structure RDL1 ([0018]); and an upper redistribution structure RDL2 disposed on the semiconductor chip 200/100 and connected to the conductive post 306 ([0040]), wherein a height of the at least one dummy post 110 is less than a height of the conductive post 306 (see Fig. 2E).
Regarding claim 2, Chen (Fig. 2E) discloses wherein an upper surface of the at least one dummy post 110 is disposed at a lower level than an upper surface of the conductive post 110.
Regarding claim 6, Chen (Fig. 2E) discloses wherein the at least one dummy post 110 is disposed in a center region of the lower redistribution structure RDL1 adjacent to the semiconductor chip 200/100.
Regarding claim 8, Chen (Fig. 2E) discloses wherein the at least one dummy post 110 comprises a body portion disposed on an upper surface of the lower redistribution structure RDL1 and a protrusion protruding downward from a lower surface of the body portion.
Regarding claim 13, Chen (Fig. 2E) discloses wherein the at least one dummy post comprises a third dummy post 110/210, and the third dummy post 110 comprises a plurality of protrusions.
Regarding claim 15, Chen (Fig. 2E) discloses further comprising: an encapsulant 308’ disposed between the lower redistribution structure RDL1 and the upper redistribution structure RDL2 and configured to cover the semiconductor chip 200, wherein an upper surface of the conductive post 306 is coplanar with an upper surface of the encapsulant 308’, and an upper surface of the at least one dummy post 110 is covered by the encapsulant 308’ ([0036]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (2020/0343223).
Regarding claims 3-5, Chen discloses all the claimed limitations of the invention except for a difference between the height of the at least one dummy post and the height of the conductive post is within a range of 10 µm to 15 µm (claim 3); or wherein a horizontal width of the at least one dummy post is greater than a horizontal width of the conductive post (claim 4); or wherein a difference between the horizontal width of the at least one dummy post and the horizontal width of the conductive post is within a range of 20 µm to 50 µm (claim 5).
However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form the device as claimed above, because the dimensions can be optimized during routine experimentation, depending upon the device in a particular application.
Allowable Subject Matter
Claims 7, 9-12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose wherein a lower surface of the at least one dummy post is in direct contact with the insulating layer (claim 7); or wherein the protrusion is embedded in the insulating layer (claim 9); or wherein the at least one dummy post comprises a first dummy post and a second dummy post, and wherein a distance between the first dummy post and the semiconductor chip is less than a distance between the second dummy post and the semiconductor chip, and a height of the first dummy post is greater than a height of the second dummy post (claim 10); or wherein the at least one dummy post is not electrically connected to the lower redistribution structure and the upper redistribution structure (claim 14).
Claims 16-20 are allowed.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious all the limitations in the base claims 16 and 19. Specifically, the combination of a semiconductor package comprising: at least one center dummy post disposed in a center region of the lower redistribution structure; at least one edge dummy post disposed in an edge region of the lower redistribution structure; and an upper redistribution structure disposed on the semiconductor chip and connected to the conductive post, wherein a height of the at least one center dummy post is less than a height of the conductive post, and an upper surface of the at least one center dummy post is spaced apart from the upper redistribution structure (claim 16); or the combination of the semiconductor package comprising: wherein a height of the at least one dummy post is less than a height of the conductive post, an upper surface of the at least one dummy post is spaced apart from the upper redistribution structure, and a portion of the at least one dummy post is embedded in the insulating layer (in claim 19).
The dependent claims being further limiting and definite are also allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814