DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
An English language translation of the non-English language foreign application has not been received.
Status of Claims
Claims 1-13, 15-16, 22-24 and 27-28 are pending.
Claims 14, 17-21, 25-26 and 29-54 are canceled.
Claims 1-13, 15-16, 22-24 and 27-28 are original.
Claims 1-7, 10-11, 15-16, 22 and 27 are rejected herein.
Claims 8-9, 12-13, 23-24 and 28 are objected to herein.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMAGE SENSOR INCLUDING SUBSTRATE WITH ISOLATION STRUCTURE DIVIDING ANALOG AND DIGITAL BLOCKS.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park ‘506 (US 20200092506 A1).
Regarding claim 1, Park ‘506 discloses (see generally, e.g., FIG. 8):
An image sensor (10) comprising:
a first substrate (121) comprising an analog block (i.e., the portion of substrate 121 under Area1 – hereinafter AB) and a digital block (i.e., the portion of substrate 121 under Area2 – hereinafter DB);
an isolation structure (ST) extending through the first substrate (121) and dividing the analog block (AB) from the digital block (DB);
a first transistor (i.e., the transistor TR in the DB – hereinafter TR1) on the digital block (DB);
a second transistor (i.e., the transistor TR in the AB – hereinafter TR2) on the analog block (AB);
a wiring (IL in layer 123 above TR2 – hereinafter IL1) on the second transistor (TR2), the wiring (IL1) being electrically connected to the second transistor (TR2);
a second substrate (111, 113 – hereinafter collectively S2) on the wiring (IL1);
a color filter array layer (i.e., the layer including color filters CF – hereinafter CFAL) on the second substrate (S2), the color filter array layer (CFAL) comprising color filters (CF);
a microlens (ML) on the color filter array layer (CFAL);
a light sensing element (PCD) in the second substrate (S2);
a transfer gate (note, the readout circuit device RCX includes the transmission transistor TX of FIG. 3, the gate of which reads on the claimed transfer gate, see, e.g., paragraph [0077] – hereinafter TG) extending through a lower portion of the second substrate (S2), the transfer gate (TG) being adjacent to the light sensing element (PCD); and
a floating diffusion region (FDA) at the lower portion of the second substrate (S2) adjacent to the transfer gate (TG), the floating diffusion region (FDA) being electrically connected to the wiring (IL1).
Regarding claim 7, Park ‘506 discloses:
The image sensor (10) of claim 1, further comprising a plurality of isolation structures (STs) including the isolation structure (ST), the plurality of isolation structures (STs) being spaced apart from each other in a first direction (X) substantially parallel to an upper surface (top surface) of the second substrate (S2), and each of the plurality of isolation structures (STs) extending in a second direction (Z) substantially parallel to the upper surface (top surface) of the second substrate (S2) and crossing the first direction (X).
Note, the isolation structures (STs) are 3-dimentional structures and hence necessarily extend in the Z-direction by some amount.
Regarding claim 10, Park ‘506 discloses:
The image sensor (10) of claim 1, further comprising:
a first insulating interlayer (126) on the first substrate (121), the first insulating interlayer (126) provided on the first transistor (TR1), the second transistor (TR2) and the wiring (IL1);
a first adhesion layer (132b) on the first insulating interlayer (126), the first adhesion layer (132b) comprising a first adhesion pad (131b);
a second adhesion layer (132a) on the first adhesion layer (132b), the second adhesion layer (132a) comprising a second adhesion pad (131a) contacting the first adhesion pad (131b); and
a second insulating interlayer (117) between the second adhesion layer (132a) and the second substrate (S2), the second insulating interlayer (117) provided on the transfer gate (TG) and the floating diffusion region (FDA).
Note, as expressly stated in the present specification, “on and over … may have opposite meanings.” Paragraph [0022]. Accordingly, the second insulating interlayer being provided “on” the transfer gate and the floating diffusion region as claimed is read for examination purposes to include the second insulting interlayer being provided “on” an underside of the transfer gate and the floating diffusion region, i.e., as disclosed by Park ‘506.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Hynecek (US 20180308881 A1).
Regarding claim 2, Park ‘506 as applied to claim 1 discloses the image sensor of claim 1.
Park ‘506 further discloses wherein the isolation structure (ST) comprises a first isolation pattern (ST) extending through an upper portion of the first substrate (121). See, e.g., FIG. 8.
Park ‘506 does not explicitly disclose wherein the isolation structure comprises a second isolation pattern structure extending through a lower portion of the first substrate and contacting the first isolation pattern.
However, in analogous art, Hynecek discloses (see generally, e.g., FIG. 2) an image sensor (14) including an isolation structure (313, 308), wherein the isolation structure (313, 308) comprises:
a first isolation pattern (313) extending through an upper portion of the first substrate; and
a second isolation pattern structure (308) extending through a lower portion of the first substrate and contacting the first isolation pattern (313).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a second isolation pattern structure extending through a lower portion of the first substrate and contacting the first isolation pattern as taught by Hynecek in the image sensor of Park ‘506 according to known methods to yield predictable results, for example, to provide further electrical isolation between the analog and digital blocks.
Regarding claim 3, Park ‘506 in view of Hynecek as applied to claim 2 discloses the image sensor of claim 2.
Park ‘506 does not explicitly disclose wherein a width of the first isolation pattern gradually decreases from an upper portion of the first isolation pattern toward a lower portion of the first isolation pattern and a width of the second isolation pattern structure gradually increases from an upper portion of the second isolation pattern structure toward a lower portion of the second isolation pattern structure.
However, in analogous art, Hynecek further discloses wherein a width of the first isolation pattern (313) gradually decreases from an upper portion of the first isolation pattern (313) toward a lower portion of the first isolation pattern (313) and a width of the second isolation pattern structure (308) gradually increases from an upper portion of the second isolation pattern structure (308) toward a lower portion of the second isolation pattern structure (308). See, e.g., FIG. 2. Note, at the topmost portion of the second isolation pattern structure (308), the width gradually increases from an upper portion of towards a lower portion, and hence under the broadest reasonable interpretation (BRI) reads on the geometry as claimed.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the isolation structure disclosed by Park ‘506 with the isolation structure taught by Hynecek according to known methods to yield predictable results, for example, as a matter of simple substitution of one know type of insulation structure for another. See, e.g., MPEP §2143(I)(B). In particular, it is found that:
(1) the prior art (see, e.g., Park ‘506 and Hynecek) contained a device (i.e., image sensor) which differed from the claimed device (i.e., image sensor) by the substitution of some component (namely, the isolation structure);
(2) the substituted components (i.e., isolation structures) and their functions (i.e., electrical isolation) were known in the art (see, e.g., Park ‘506 and Hynecek); and
(3) one of ordinary skill in the art could have substituted one known element (i.e., the isolation structure of Hynecek) for another (i.e., the isolation structure of Park ‘506), and the results of the substitution would have been predictable.
Regarding claim 15, Park ‘506 discloses (see generally, e.g., FIG. 8):
An image sensor (10) comprising:
a first substrate (121);
an isolation structure (ST) comprising:
a first isolation pattern (ST) extending through an upper portion of the first substrate (121);
and a second isolation pattern structure extending through a lower portion of the first substrate and contacting the first isolation pattern, the second isolation pattern structure comprising a material that is different from a material of the first isolation pattern;
a first transistor (TR) on the first substrate (121);
a wiring (IL in layer 123) on the first transistor (TR), the wiring (IL) being electrically connected to the first transistor (TR);
a second substrate (111, 113 – hereinafter collectively S2) on the wiring (IL);
a color filter array layer (i.e., the layer including color filters CF – hereinafter CFAL) on the second substrate (S2), the color filter array layer (CFAL) comprising color filters (CF);
a microlens (ML) on the color filter array layer (CFAL);
a light sensing element (PCD) in the second substrate (S2);
a transfer gate (note, the readout circuit device RCX includes the transmission transistor TX of FIG. 3, the gate of which reads on the claimed transfer gate, see, e.g., paragraph [0077] – hereinafter TG) extending through a lower portion of the second substrate (S2), the transfer gate (TG) being adjacent to the light sensing element (PCD); and
a floating diffusion region (FDA) at the lower portion of the second substrate (S2) adjacent to the transfer gate (TG), the floating diffusion region (FDA) being electrically connected to the wiring (IL).
Park ‘506 does not explicitly disclose the isolation structure comprising a second isolation pattern structure extending through a lower portion of the first substrate and contacting the first isolation pattern, the second isolation pattern structure comprising a material that is different from a material of the first isolation pattern.
However, in analogous art, Hynecek discloses (see generally, e.g., FIG. 2) an image sensor (14) including an isolation structure (313, 308), wherein the isolation structure (313, 308) comprises:
a first isolation pattern (313) extending through an upper portion of the first substrate; and
a second isolation pattern structure (308) extending through a lower portion of the first substrate and contacting the first isolation pattern (313), the second isolation pattern structure (308) comprising a material (i.e., “P+ type doped regions 308” material – see, e.g., paragraph [0031]) that is different from a material (i.e., “oxide layer 306” material – see, e.g., paragraph [0031]) of the first isolation pattern (313).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a second isolation pattern structure extending through a lower portion of the first substrate and contacting the first isolation pattern, the second isolation pattern structure comprising a material that is different from a material of the first isolation pattern, as taught by Hynecek in the image sensor of Park ‘506 according to known methods to yield predictable results, for example, to provide further electrical isolation between the respective areas divided by the isolation structure.
Regarding claim 16, Park ‘506 in view of Hynecek as applied to claim 15 discloses the image sensor of claim 15.
Park ‘506 does not explicitly disclose wherein a width of the first isolation pattern gradually decreases from an upper portion of the first isolation pattern toward a lower portion of the first isolation pattern and a width of the second isolation pattern structure gradually increases from an upper portion of the second isolation pattern structure toward a lower portion of the second isolation pattern structure.
However, in analogous art, Hynecek further discloses wherein a width of the first isolation pattern (313) gradually decreases from an upper portion of the first isolation pattern (313) toward a lower portion of the first isolation pattern (313) and a width of the second isolation pattern structure (308) gradually increases from an upper portion of the second isolation pattern structure (308) toward a lower portion of the second isolation pattern structure (308). See, e.g., FIG. 2. Note, at the topmost portion of the second isolation pattern structure (308), the width gradually increases from an upper portion of towards a lower portion, and hence under the broadest reasonable interpretation (BRI) reads on the geometry as claimed.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the isolation structure disclosed by Park ‘506 with the isolation structure taught by Hynecek according to known methods to yield predictable results, for example, as a matter of simple substitution of one known type of insulation structure for another. See, e.g., MPEP §2143(I)(B). In particular, it is found that:
(1) the prior art (see, e.g., Park ‘506 and Hynecek) contained a device (i.e., image sensor) which differed from the claimed device (i.e., image sensor) by the substitution of some component (namely, the isolation structure);
(2) the substituted components (i.e., isolation structures) and their functions (i.e., electrical isolation) were known in the art (see, e.g., Park ‘506 and Hynecek); and
(3) one of ordinary skill in the art could have substituted one known element (i.e., the isolation structure of Hynecek) for another (i.e., the isolation structure of Park ‘506), and the results of the substitution would have been predictable.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Hynecek as applied to claim 2 above, and further in view of Barr (US 10192919 B2) and Park ‘050 (US 20090096050 A1).
Regarding claim 4, Park ‘506 in view of Hynecek as applied to claim 2 discloses the image sensor of claim 2.
Park ‘506 in view of Hynecek does not explicitly disclose wherein the second isolation pattern structure comprises:
a conductive pattern comprising a metal; and
an insulation pattern provided on a sidewall and an upper surface of the conductive pattern.
However, in analogous art, Barr discloses (see, e.g., FIG. 6) an isolation pattern structure (36) that comprises:
a pattern (62); and
an insulation pattern (52) provided on a sidewall and an upper surface (see, e.g., FIG. 6) of the pattern (62).
Note, as expressly stated in the present specification, “on and over … may have opposite meanings.” Paragraph [0022]. Accordingly, the insulating pattern being provided “on” an upper surface as claimed is read for examination purposes to include the insulting pattern being provided “on” an underside of an upper surface, i.e., as disclosed by Barr.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the second isolation pattern structure disclosed by Park ‘506 in view of Hynecek with the isolation pattern structure taught by Barr according to known methods to yield predictable results, for example, as a matter of simple substitution of one known type of insulation structure pattern for another. See, e.g., MPEP §2143(I)(B). In particular, it is found that:
(1) the prior art (see, e.g., Park ‘506, Hynecek and Barr) contained a device (i.e., image sensor) which differed from the claimed device (i.e., image sensor) by the substitution of some component (namely, the second isolation pattern structure);
(2) the substituted components (i.e., isolation pattern structures) and their functions (i.e., electrical isolation) were known in the art (see, e.g., Park ‘506, Hynecek and Barr); and
(3) one of ordinary skill in the art could have substituted one known element (i.e., the second isolation pattern structure of Park ‘506 in view of Hynecek) for another (i.e., the isolation pattern structure of Barr), and the results of the substitution would have been predictable.
While Barr discloses the pattern (62) as being an antireflective coating (see, e.g., column 5, lines 54-55), Barr does not explicitly disclose that the pattern is a conductive pattern comprising a metal.
However, in analogous art, Park ‘050 disclose an antireflective coating which is titanium (see, e.g., paragraph [0017]), i.e., an antireflective coating which is conductive and comprising a metal.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used titanium as taught by Park ‘050 for the pattern (62) of Barr according to known methods to yield predictable results, for example, in order to use a readily available, known material (e.g., titanium) for its known purpose (e.g., as an antireflective coating).
Note, when titanium is used for the pattern (62) of Barr as taught by Park ‘050, the pattern is a conductive pattern comprising a metal as claimed. Accordingly, Park ‘506 in view of Hynecek and further in view of Barr and Park ‘050 discloses wherein the second isolation pattern structure comprises: a conductive pattern comprising a metal; and an insulation pattern provided on a sidewall and an upper surface of the conductive pattern.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Hynecek, Barr and Park ‘050 as applied to claim 4 above, and further in view of Olsen (US 20020102814 A1).
Regarding claim 5, Park ‘506 in view of Hynecek, Barr and Park ‘050 as applied to claim 4 discloses the image sensor of claim 4.
While Barr discloses that the insulation pattern (52) is a dielectric (see, e.g., column 5, line 13), Barr does not explicitly disclose wherein the insulation pattern comprises a metal oxide.
However, in analogous art, Olens disclose an isolation structure wherein the insulation pattern comprises a metal oxide (e.g., aluminum trioxide). See, e.g., FIG. 5A, Abstract and paragraphs [0027]-[0028].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the second isolation pattern structure of Park ‘506 in view of Hynecek, Barr and Park ‘050 wherein the isolation pattern (52) of Barr comprises a metal oxide as taught by Olsen according to known methods to yield predictable results, for example, in order to use a readily available, known material (e.g., comprising aluminum trioxide) for its known purpose (e.g., as an isolation pattern dielectric) and further to reduce stress in the isolation region. See, e.g., Olsen, Abstract.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Hynecek as applied to claim 2 above, and further in view of Barr and Olsen.
Regarding claim 6, Park ‘506 in view of Hynecek as applied to claim 2 discloses the image sensor of claim 2.
Park ‘506 further discloses wherein the first isolation pattern (ST) comprises silicon oxide (paragraph [0084]).
Park ‘506 in view of Hynecek does not explicitly disclose wherein the second isolation pattern structure comprises a metal oxide.
However, in analogous art, Barr discloses (see, e.g., FIG. 6) an isolation pattern structure (34) that comprises a dielectric material (52).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the second isolation pattern structure disclosed by Park ‘506 in view of Hynecek with the isolation pattern structure taught by Barr according to known methods to yield predictable results, for example, as a matter of simple substitution of one known type of insulation structure pattern for another. See, e.g., MPEP §2143(I)(B). In particular, it is found that:
(1) the prior art (see, e.g., Park ‘506, Hynecek and Barr) contained a device (i.e., image sensor) which differed from the claimed device (i.e., image sensor) by the substitution of some component (namely, the second isolation pattern structure);
(2) the substituted components (i.e., isolation pattern structures) and their functions (i.e., electrical isolation) were known in the art (see, e.g., Park ‘506, Hynecek and Barr); and
(3) one of ordinary skill in the art could have substituted one known element (i.e., the second isolation pattern structure of Park ‘506 in view of Hynecek) for another (i.e., the isolation pattern structure of Barr), and the results of the substitution would have been predictable.
While Barr discloses that the material (52) is a dielectric (see, e.g., column 5, line 13), Barr does not explicitly disclose that the material comprises a metal oxide.
However, in analogous art, Olens disclose an isolation structure wherein the isolation pattern structure comprises a metal oxide (e.g., aluminum trioxide). See, e.g., FIG. 5A, Abstract and paragraphs [0027]-[0028].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the second isolation pattern structure of Park ‘506 in view of Hynecek and Barr such that the material (52) of Barr comprises a metal oxide as taught by Olsen according to known methods to yield predictable results, for example, in order to use a readily available, known material (e.g., comprising aluminum trioxide) for its known purpose (e.g., as an isolation pattern dielectric) and further to reduce stress in the isolation region. See, e.g., Olsen, Abstract.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Madurawe (US 20160358967 A1).
Regarding claim 11, Park ‘506 as applied to claim 1 discloses the image sensor of claim 1.
Park ‘506 does not explicitly disclose:
a third substrate under the second substrate;
a third transistor on the third substrate; and
an insulating interlayer between the third substrate and the second substrate, the insulating interlayer provided on the third transistor.
However, in analogous art, Madurawe discloses an image sensor (see, e.g., FIG. 9) including: a third substrate (402-2) under a second substrate (404); a third transistor (see, e.g., paragraph [0044]) on the third substrate (402-2); and an insulating interlayer (i.e., the interlayer dielectric (ILD) of stack 500-1) between the third substrate (402-2) and the second substrate (404), the insulating interlayer (i.e., the interlayer dielectric (ILD) of stack 500-1) provided on the third transistor (see, e.g., FIG. 9).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a third substrate under the second substrate, a third transistor on the third substrate, and an insulating interlayer between the third substrate and the second substrate, the insulating interlayer provided on the third transistor, as taught by Hynecek, in the image sensor of Park ‘506 according to known methods to yield predictable results, for example, to provide a desired device integration while allowing various transistors of differing types and/or having different functions and/or different circuit elements to be formed on different substrates and/or at different processing nodes. See, e.g., paragraph [0045] and [0047] of Madurawe.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Hynecek as applied to claim 15 above, and further in view of Madurawe.
Regarding claim 22, Park ‘506 in view of Hynecek as applied to claim 15 discloses the image sensor of claim 15.
Park ‘506 does not explicitly disclose:
a third substrate under the second substrate;
a second transistor on the third substrate; and
an insulating interlayer between the third substrate and the second substrate, the insulating interlayer provided on the second transistor.
However, in analogous art, Madurawe discloses an image sensor (see, e.g., FIG. 9) including: a third substrate (402-2) under a second substrate (404); a second transistor (see, e.g., paragraph [0044]) on the third substrate (402-2); and an insulating interlayer (i.e., the interlayer dielectric (ILD) of stack 500-1) between the third substrate (402-2) and the second substrate (404), the insulating interlayer (i.e., the interlayer dielectric (ILD) of stack 500-1) provided on the third transistor (see, e.g., FIG. 9).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a third substrate under the second substrate, a second transistor on the third substrate, and an insulating interlayer between the third substrate and the second substrate, the insulating interlayer provided on the second transistor, as taught by Hynecek, in the image sensor of Park ‘506 according to known methods to yield predictable results, for example, to provide a desired device integration while allowing various transistors of differing types and/or having different functions and/or different circuit elements to be formed on different substrates and/or at different processing nodes. See, e.g., paragraph [0045] and [0047] of Madurawe.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Park ‘506 in view of Hynecek and Madurawe.
Regarding claim 27, Park ‘506 discloses (see generally, e.g., FIG. 8):
An image sensor (10) comprising:
a second substrate (121), the second substrate comprising an analog block (i.e., the portion of substrate 121 under Area1 – hereinafter AB) and a digital block (i.e., the portion of substrate 121 under Area2 – hereinafter DB), wherein an analog circuit is provided in the analog block (see, e.g., the transistor TR in the AB and paragraph [0073]) and a digital circuit is provided in the digital block (see, e.g., the transistor TR in the DB and paragraph [0073]);
an isolation structure (ST) extending through the second substrate (121) and dividing the analog block (AB) from the digital block (DB), the isolation structure (ST) comprising:
a first isolation pattern (ST) extending through an upper portion of the second substrate (121); and
a third substrate (111, 113 – hereinafter collectively S3) on the second substrate (121);
a color filter array layer (i.e., the layer including color filters CF – hereinafter CFAL) on the third substrate (S3), the color filter array layer (CFAL) comprising color filters (CF);
a microlens (ML) on the color filter array layer (CFAL);
a light sensing element (PCD) in the third substrate (S3);
a transfer gate (note, the readout circuit device RCX includes the transmission transistor TX of FIG. 3, the gate of which reads on the claimed transfer gate, see, e.g., paragraph [0077] – hereinafter TG) extending through a lower portion of the third substrate (S3), the transfer gate (TG) being adjacent to the light sensing element (PCD); and
a floating diffusion region (FDA) at the lower portion of the third substrate (S3) adjacent to the transfer gate (TG), the floating diffusion region (FDA) being electrically connected to a wiring (IL, VI).
Park ‘506 does not explicitly disclose wherein the isolation structure comprises a second isolation pattern structure extending through a lower portion of the second substrate and contacting the first isolation pattern.
However, in analogous art, Hynecek discloses (see generally, e.g., FIG. 2) an image sensor (14) including an isolation structure (313, 308), wherein the isolation structure (313, 308) comprises:
a first isolation pattern (313) extending through an upper portion of the second substrate; and
a second isolation pattern structure (308) extending through a lower portion of the second substrate and contacting the first isolation pattern (313).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a second isolation pattern structure extending through a lower portion of the second substrate and contacting the first isolation pattern as taught by Hynecek in the image sensor of Park ‘506 according to known methods to yield predictable results, for example, to provide further electrical isolation between the analog and digital blocks.
Park ‘506 does not explicitly disclose a first substrate having a logic circuit thereon arranged such that the second substrate is over the first substrate.
However, in analogous art, Madurawe discloses an image sensor (see, e.g., FIG. 9) including a first substrate (402-2) having a logic circuit thereon (see, e.g., paragraph [0045]) and a second substrate (402-1) over the first substrate (402-2).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a first substrate having a logic circuit thereon arranged such that the second substrate is over the first substrate as taught by Hynecek in the image sensor of Park ‘506 according to known methods to yield predictable results, for example, to provide a desired device integration while allowing various transistors of differing types and/or having different functions and/or different circuit elements to be formed on different substrates and/or at different processing nodes. See, e.g., paragraph [0045] and [0047] of Madurawe.
Allowable Subject Matter
Claims 8-9, 12-13, 23-24 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 8, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “wherein the isolation structure has a lattice shape,” in such a manner as to anticipate the claim or render the claim obvious.
Regarding claim 9, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “wherein the first substrate comprises a first region and a second region around the first region” and “a through electrode structure extending through the second region of the first substrate” and “wherein a width of the through electrode structure gradually increases from an upper portion of the through electrode structure toward a lower portion of the through electrode structure,” in such a manner as to anticipate the claim or render the claim obvious.
Regarding claim 12, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “a conductive layer on a lower surface of the first substrate, the conductive layer being connected to the isolation structure and comprising a metal,” in such a manner as to anticipate the claim or render the claim obvious.
Regarding claim 13, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “wherein the first transistor is included in a circuit of a memory device, the second transistor is a source follower (SF) transistor, and the third transistor is included in a logic circuit,” in such a manner as to anticipate the claim or render the claim obvious.
Regarding claim 23, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “a conductive layer on a lower surface of the first substrate, the conductive layer being connected to the isolation structure and comprising a metal,” in such a manner as to anticipate the claim or render the claim obvious.
Claim 24 depends from claim 23, and accordingly is indicated as including allowable subject matter for at least the same reasons as claim 23.
Regarding claim 28, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “a conductive layer on a lower surface of the second substrate, the conductive layer being connected to the isolation structure,” in such a manner as to anticipate the claim or render the claim obvious.
Conclusion
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812