DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/02/2026 has been entered.
Response to Arguments
Applicant’s amendments and the accompanying arguments with respect to the second interconnections and the silicon die (fourth die) horizontally overlap along a horizontal axis have been fully considered and are persuasive with respect to interconnections 130’ of Joseph. However, upon further consideration, a new ground(s) of rejection is made in view of alternative aspects of Joseph.
Joseph discloses additional second interconnections in substrate 110 that are laterally spaced apart from the silicon die such that the second interconnections and the silicon die horizontally overlap along a horizontal axis.
Joseph discloses the silicon bridge 115 embedded in substrate 110, paragraph 29. Joseph further discloses “The substrate 110 can comprise multiple interconnect layers (not shown but similar to the interconnect layers 130a and 130b of FIG. 1Bi),” paragraph 20, and “the solder balls 130' of the interposer 130 are physically attached to substrate pads (not shown) of the substrate 110. The substrate pads of the substrate 110 are electrically connected to substrate balls 110' of the substrate 110,” paragraph 17. That is, Joseph discloses the silicon bridge embedded in the thickness of substrate 110 and interconnections corresponding to the respective solder balls 130’ that extend through the entire thickness of substrate 110, and therefore the interconnections are laterally spaced apart from the silicon (fourth) die and the interconnections and the silicon (fourth) die horizontally overlap along a horizontal axis.
For at least these reasons, the combination of Joseph and the other cited references renders the invention as claimed obvious. The rejection is therefore maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 14-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Brothers et al. (US 2013/0141442) and Joseph et al. (US 2009/0267238) and Hu et al. (US 2014/0299999).
In reference to claim 1, Hung et al. (US 2015/0171006), hereafter “Hung,” discloses a heterogeneous chip package, with reference to Figures 35A and 35B, comprising:
a base die 100 surrounded by a molding material 34, the base die comprising first interconnections, paragraphs 12, 18, and 33;
a metal post 32 in and contacting the molding material, the metal post laterally spaced apart from the base die, paragraph 16;
a first chip 200 electrically coupled to the base die;
a second chip 200 electrically coupled to the base die, paragraph 25; and
a dielectric material 56 between and in contact with the first chip and the second chip, paragraph 26,
and second interconnections 70, 74 below the base die, paragraphs 28 and 29.
Hung does not disclose the base die comprising through interconnections,
the second chip electrically coupled to the first chip by at least one of the first interconnections in the base die,
a silicon die vertically beneath the base die, or
the second interconnections laterally spaced apart from the silicon die such that the second interconnections and the silicon die horizontally overlap along a horizontal axis.
Brothers et al. (US 2013/0141442), hereafter “Brothers,” discloses a chip package including teaching a second chip 50 in Figure 3, electrically coupled to a first chip 35 by interconnections 85 in the base die, paragraphs 23, 24 and 26. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second chip to be electrically coupled to the first chip by the interconnections in the base die. One would have been motivated to allow communication between chips within the chip package, paragraph 5 and 7.
Joseph et al. (US 2009/0267238), hereafter “Joseph,” discloses an analogous heterogeneous chip package including teaching a base die, 130 in Figure 1, comprising through interconnections, paragraph 47, a silicon die 115 vertically beneath the base die, paragraphs 2, 19, and 22, and second interconnections 130a, 130b of 110 connecting solder balls 130’ to substrate balls 110’, paragraphs 17 and 20, laterally spaced apart from the silicon die (bonded at 130”), such that the second interconnections and the silicon die horizontally overlap along a horizontal axis.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the base die to comprise through interconnections, a silicon die to be vertically beneath the base die, and the second interconnections to be laterally spaced apart from the silicon die such that the second interconnections and the silicon die horizontally overlap along a horizontal axis. One would have been motivated to do so in order to provide a multi-chip package with increased communication pathways between chips, paragraphs 3-5.
In reference to claim 2, Hung discloses the base die 100 is in contact with the molding material 34, Figure 35B and paragraph 18.
In reference to claim 3, Hung discloses the first chip 200 and the second chip 200 are entirely within a footprint of the base die 100, Figure 35A.
In reference to claim 4, Joseph disclose the silicon die 115 is only partially within a footprint of the base die 130, Figure 1C.
In reference to claim 5, Joseph discloses the silicon die 115 is electrically coupled, 115’, 130” to the base die 130, paragraph 22.
In reference to claim 6, Joseph discloses the silicon die has contacts 115’ on only a top side of the silicon die, Figure 1A and paragraphs 22 and 29.
In reference to claim 8, Hung discloses a heterogeneous chip package, with reference to Figures 35A and 35B, comprising:
a first die 100 having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall, the first die comprising first interconnections, paragraphs 12, 18, and 33;
a molding material 34 laterally adjacent to the first sidewall and the second sidewall of the first die,
a metal post 32 in and contacting the molding material, the metal post laterally spaced apart from the base die, paragraph 16;
a second die 200 conductively coupled to the first die;
a third die 200 electrically coupled to the first die, paragraph 25; and
a dielectric material 56 between and in contact with the second die and the third die, paragraph 26,
and second interconnections 70, 74 below the first die, paragraphs 28 and 29.
Hung does not disclose the first die comprising through interconnections,
the third die conductively coupled to the second die by at least one of the first interconnections in the first die, or
a fourth die vertically beneath the first die, wherein the second interconnections are laterally spaced apart from the fourth die.
Brothers discloses a chip package including teaching a third die 50 in Figure 3, conductively coupled to a second die 35 by interconnections 85 in a first die, paragraphs 23, 24, and 26. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the third die to be conductively coupled to the second die by at least one of the first interconnections in the first die. One would have been motivated to do so in order to allow communication between chips within the chip package, paragraphs 5 and 7.
Joseph discloses an analogous heterogeneous chip package including teaching a first die, 130 in figure 1, comprising through interconnections, paragraph 47, a fourth die 115 vertically beneath the first die 130, paragraphs 2, 19, and 22, and second interconnections 130a, 130b of 110 connecting solder balls 130’ to substrate balls 110’, paragraphs 17 and 20, laterally spaced apart from the silicon die (bonded at 130”), such that the second interconnections and the silicon die horizontally overlap along a horizontal axis.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the base die to comprise through interconnections, a fourth die to be vertically beneath the first die, and the second interconnections to be laterally spaced apart from the fourth die such that the second interconnections and the fourth die horizontally overlap along a horizontal axis. One would have been motivated to do so in order to provide a multi-chip package with increased communication pathways between chips, paragraphs 3-5.
In reference to claim 9, Joseph discloses the fourth die has contacts 115’ on only a top side of the fourth die, paragraphs 22 and 23.
In reference to claim 10, Joseph disclose the fourth die 115 is only partially within a footprint of the first die 130, Figure 1C.
In reference to claim 11, Hung discloses the molding material 34 is in contact with the first sidewall and the second sidewall of the first die, Figure 35B and paragraph 18.
In reference to claim 12, Hung discloses the second die 200 and the third die 200 are entirely within a footprint of the first die 100, Figure 35A.
In reference to claim 14, Hung discloses a heterogeneous chip package, with reference to Figures 35A and 35B, comprising:
a base die 100 having a first sidewall and a second sidewall between a top side and a bottom side, the second sidewall laterally opposite the first sidewall, the base die comprising interconnections on the top side of the base die and interconnections 70, 74 on the bottom side of the base die, paragraphs 20 and 28, wherein one or more of the interconnections on the dop side of the base die are coupled to corresponding ones of the interconnections on the bottom side of the base die, paragraph 29,
a molding material 34 laterally adjacent to the first sidewall and the second sidewall of the base die, paragraphs 12, 18, and 33;
a metal post 32 laterally spaced apart from the base die, the metal post having a sidewall in contact with the molding material, paragraphs 16 and 18;
a first chip 200 vertically over and coupled to the base die;
a second chip 200 vertically over and coupled to the base die, the second chip laterally spaced apart from the first chip, paragraph 25; and
a dielectric material 56 between a sidewall of the first chip and a sidewall of the second chip, the dielectric material in contact with the sidewall of the first chip and the sidewall of the second chip, paragraph 26,
and second interconnections 70, 74 below the base die, paragraphs 28 and 29.
Hung does not disclose the second chip coupled to the first chip by an interconnection of the top side of the base die,
a silicon die vertically beneath the base die, the silicon die having contacts on only a top side of the silicon die, or
the second interconnections laterally spaced apart from the silicon die.
Brothers discloses a chip package including teaching a second chip 50 in Figure 3, coupled to a first chip 35 by interconnections 85 of the top side of the base die, paragraphs 23, 24, and 26. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second chip to be coupled to the first chip by the interconnections of the top side of the base die. One would have been motivated to do so in order to allow communication between chips within the chip package, paragraphs 5 and 7.
Joseph discloses an analogous heterogeneous chip package including teaching a silicon die 115 vertically beneath a base die 130, paragraphs 2, 19, and 22, the silicon die having contacts on only a top side of the silicon die, Figure 1A and paragraphs 22 and 29, and second interconnections 130a, 130b of 110 connecting solder balls 130’ to substrate balls 110’, paragraphs 17 and 20, laterally spaced apart from the silicon die (bonded at 130”), such that the second interconnections and the silicon die horizontally overlap along a horizontal axis.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a silicon die to be vertically beneath the base die, the silicon die to have contacts on only a top side of the silicon die, and the second interconnections to be laterally spaced apart from the silicon die such that the second interconnections and the silicon die horizontally overlap along a horizontal axis. One would have been motivated to do so in order to provide a multi-chip package with increased communication pathways between chips, paragraphs 3-5.
In reference to claim 15, Hung discloses the molding material 34 is in contact with the first sidewall and the second sidewall of the base die, Figure 35B and paragraph 18.
In reference to claim 16, Hung discloses the first chip 200 and the second chip 200 are entirely within a footprint of the base die 100, Figure 35A.
In reference to claim 17, Joseph disclose the silicon die 115 is only partially within a footprint of the base die 130, Figure 1C, and is electrically coupled, 115’, 130” to the base die 130, paragraph 22.
In reference to claim 19, Joseph discloses the silicon die 115 bridges the base die 130 to a second base die 120, paragraph 22.
Claims 7, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Brothers et al. (US 2013/0141442) and Joseph et al. (US 2009/0267238) as applied above and further in view of Huang et al. (US 2017/0250139).
In reference to claims 7 and 18, Hung does not disclose the metal post is a fiducial.
Huang et al. (US 2017/0250139), hereafter “Huang,” discloses an analogous chip package including teaching a metal post, 32A in Figures 4 and 5, is a fiducial, paragraphs 18, 19, and 25. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the metal post to be a fiducial. One would have been motivated to do so in order to have an alignment mark for aligning the placement of dies in the chip package, paragraph 25.
In reference to claim 13, Hung does not disclose the metal post is a fiducial for accurately placing the first die.
Huang discloses an analogous chip package including teaching a metal post, 32A in Figures 4 and 5, is a fiducial for accurately placing a first die, paragraphs 18, 19, and 25. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the metal post to be a fiducial for placing the firs die. One would have been motivated to do so in order to have an alignment mark for aligning the placement of dies in the chip package, paragraph 25.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2015/0171006) in view of Brothers et al. (US 2013/0141442) and Joseph et al. (US 2009/0267238) as applied above and further in view of Yeh et al. (US 2017/0125376).
In reference to claim 20, Hung does not disclose the dielectric material has an uppermost surface at a same level as an uppermost surface of the first chip and as an uppermost surface of the second chip.
Yeh et al. (US 2017/0125376) discloses a chip package including teaching a dielectric material, 120 in Figure 6, having an uppermost surface at a same level as an uppermost surface of a first chip 102B and as an uppermost surface of a second chip 102C, paragraph 35. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the dielectric material has an uppermost surface at a same level as an uppermost surface of the first chip and as an uppermost surface of the second chip. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). In this case substituting one dielectric layer configuration for another as suggested by Yeh, paragraph 35.al. (US 2
Conclusion
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897