Attorney’s Docket Number: AF1399-US 111079-277118
Filing Date: 6/29/2023
Inventors: Baumgartner et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 6/29/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
Claim 13 recites the limitation “…wherein the circuitry elements on the first surface comprises a number of driving circuitry instances equal to a number of antennas.”, which will be interpreted as “…wherein the circuitry elements on the first surface comprise driving circuitry for each antenna”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "…so that the first surfaces face away…" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the line will be construed to recite "…so that the third surfaces face away…".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1-2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 20230291127 A1).
Regarding claim 1, Lin (see, e.g., fig. 5) shows all aspects of the instant invention including a communications die, comprising:
A substrate (e.g., substrate Sb) with a first face (e.g., second layer SbL_2) and a second face (e.g., first layer SbL_1), and wherein edge surfaces (see, e.g., interior and exterior surfaces of SbL_2 and SbL_1, noting they’re electrically connected via the different antenna arrays) connect the first face (e.g., second layer SbL_2) and a second face (e.g., first layer SbL_1);
A circuitry element (e.g., communication circuit 101) on the first face (e.g., second layer SbL_2);
An antenna (e.g., second antenna array Ar_21) on at least one of the edge surfaces (see, e.g., interior and exterior surfaces of SbL_2 and SbL_1, noting they’re electrically connected via the different antenna arrays).
Regarding claim 2, Lin (see, e.g., fig. 5) shows wherein the circuitry element (e.g., communication circuit 101) comprises circuitry (see, e.g., paragraph 25 “The communication circuit 101…may be configured to up-convert or down-convert a signal frequency…The connector 103 may be configured to receive power or control signals for the first antenna arrays Ar_11, Ar_12, the second antenna arrays Ar_21, Ar_22, Ar_23 or the communication circuit 101.”) for driving the antenna (e.g., second antenna array Ar_21).
Regarding claim 4, Lin (see, e.g., fig. 5) shows a plurality of antennas (e.g., second antenna array Ar_21 and first antenna array Ar_11) each on a different one of the edge surfaces (e.g., note that Ar_21 and Ar_11 are configured on different edges, see fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Elsherbini (US 20200235061 A1).
Regarding claim 3, Lin (see, e.g., figs. 5) fails to explicitly show wherein the substrate comprises a group III-V semiconductor material.
Elsherbini (see, e.g., fig. 16), in a similar device to Lin, teaches a substrate (e.g., interposer 1604) comprises a group III-V semiconductor material (e.g., paragraph 110 “the interposer 1604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the group III-V semiconductor material of Elsherbini within the substrate of Lin, in order to achieve the expected result of providing other embedded active/passive devices coupled to the antenna array as desired (see, e.g., paragraph 110 of Elsherbini).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chavali (US 20190393606 A1).
Lin (see, e.g., fig. 5) fails to explicitly show wherein the antenna is a mm-wave antenna or a sub-terahertz antenna.
Chavali (see, e.g., fig. 1G), in a similar device to Lin, teaches an antenna (e.g., antenna 104) is a mm-wave antenna or is a sub-terahertz antenna (see, e.g., paragraph 43 “the assembly of the antenna 104 may be implemented with mm-wave closed or open waveguides (e.g., in the 60-120 GHz frequency bands…”, also note 60 GHz is .06 terahertz).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the mm-wave/sub-terahertz antenna configuration of Chavali within the antenna setup of Lin, in order to enable an antenna profile for high-frequency applications, enabling exceedingly high data rates with the device (also see paragraph 43 of Chavali).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kamgaing (US 20180323159 A1).
Regarding claim 6, Lin fails to show a base die that is a CMOS logic chip, wherein the substrate is coupled to the base die.
Kamgaing (see, e.g., fig. 1), in a similar device to Lin, teaches a base die (e.g., die 110) that is a CMOS logic chip (see, e.g., paragraph 21 “CMOS circuitry having at least one baseband unit…CMOS die…”), wherein a substrate (e.g., substrate 150) is coupled to the base die (e.g., die 110).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the CMOS-substrate coupling configuration of Kamgaing within the substrate setup of Lin, in order to achieve the expected result of including CMOS capabilities within the device.
Regarding claim 7, Lin (see, e.g., fig. 5) shows wherein a connection from the circuitry element (e.g., communication circuit 101) to the antenna (e.g., second antenna array Ar_21) is across (e.g., note that the circuitry element is across the edge surface from the antenna arrays) one of the edge surfaces (see, e.g., interior and exterior surfaces of SbL_2 and SbL_1, noting they’re electrically connected via the different antenna arrays).
Claims 8-9 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zaal (US 20170236803 A1) further in view of Kamgaing (US 20190089036 A1).
Regarding claim 8, Lin (see, e.g., fig. 5) shows most aspects of the instant invention including a communications module, comprising:
A communications module (e.g., antenna module 100) comprising:
A third surface (e.g., second layer SbL_2);
A fourth surface (e.g., first layer SbL_1);
edge surfaces (see, e.g., interior and exterior surfaces of SbL_2 and SbL_1, noting they’re electrically connected via the different antenna arrays) to couple the third surface (e.g., second layer SbL_2) to the fourth surface (e.g., first layer SbL_1);
circuitry elements (e.g., communication circuit 101) on the third surface (e.g., second layer SbL_2);
An antenna (e.g., second antenna array Ar_21) on one or more of the edge surfaces (see, e.g., interior and exterior surfaces of SbL_2 and SbL_1, noting they’re electrically connected via the different antenna arrays).
Lin (see, e.g., fig. 5), however, fails to show a base die with a first surface and a second surface, and an array of communication dies on the base die, where the first surface is orthogonal to the third surface of the communication die and orthogonal to the fourth surface of the communication die.
Zaal (see, e.g., fig. 4), in a similar device to Lin, teaches an array of communication dies (see, e.g., the dies on wafer 110 + paragraph 34).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt the communication die array setup of Zaal within the module of Lin, in order to achieve the expected result of improving the functionality and communication potential by expanding the communication die mass. In addition, it also would have been obvious to one of ordinary skill in the art to duplicate the communications module of Lin in order to achieve the expected result of increasing the efficiency and the communications density within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Lin in view of Zaal, however fails to explicitly teach a base die with a first surface and a second surface, wherein individual ones of the communication dies comprise a third surface that is orthogonal to the first surface of the base die and a fourth surface that is orthogonal to the first surface of the base die.
Kamgaing (see, e.g., fig. 3), in a similar device to Lin in view of Zaal, teaches a base die (e.g., base die 330) with a first surface (e.g., left-most vertical surface) and a second surface (e.g., right-most vertical surface).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the base die of Kamgaing beneath and coupled to the communication dies of Lin in view of Zaal, in order to achieve the expected result of providing an additional conductive interface for signal propagation within the device (see, e.g., paragraph 36 of Kamgaing). Note that with the manner in which the base die is configured beneath the array of communication dies, the first surface would be orthogonal (as the first and second surface are vertically oriented and the third and fourth surface are horizontally oriented) to the third surface and the fourth surface of the communication dies.
Regarding claim 9, Zaal (see, e.g., fig. 4), teaches wherein the communication dies (see, e.g., the dies on wafer 110 + paragraph 34) are spaced at a pitch (see, e.g., distance between the dies).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pitch spacing of Zaal within the arrangement of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of spacing out the dies of the platform.
Regarding claim 12, Zaal (see, e.g., fig. 4) teaches wherein the array of communication dies (see, e.g., the dies on wafer 110 + paragraph 34) comprises a first die (e.g., left-side die) and a second die (e.g., second die, adjacent to left-side die), wherein the first die (e.g., left-side die) is adjacent to the second die (e.g., second die, adjacent to left-side die), wherein the first die (e.g., left-side die) comprises a first antenna (e.g., antenna of left-side die, see paragraphs 34 or 41), and wherein the second die (e.g., second die, adjacent to left-side die) comprises a second antenna (e.g., antenna of second die, see paragraphs 34 or 41).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the adjacent die and antenna setup of Zaal within the device of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of providing a connective antenna setup across the module. Note the antenna are placed on the edges of the die, hence the first die right-edge antenna and second die left-edge antenna have a pitch substantially close to half the pitch of the dies. In addition, note that the exact offset between the antenna becomes a design choice based on the layout and connectivity requirements.
Regarding claim 13, Lin (see, e.g., fig. 5) shows wherein the circuitry elements (e.g., communications die 101) on the first surface (e.g., second layer SbL_2) comprise driving circuitry (see, e.g., paragraph 25 “The communication circuit 101…may be configured to up-convert or down-convert a signal frequency…The connector 103 may be configured to receive power or control signals for the first antenna arrays Ar_11, Ar_12, the second antenna arrays Ar_21, Ar_22, Ar_23 or the communication circuit 101.”) for each antenna.
Zaal (see, e.g., fig. 4) teaches wherein each communication die (see, e.g., the dies on wafer 110 + paragraph 34) comprises two or more antennas (e.g., contacts 170 and 171 + paragraph 41 “…the circuitry/contacts are formed as an antenna…”) along each of the edge surfaces (see, e.g., edge surfaces of each die).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dual antenna configuration of Zaal within each die of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of increasing the signal efficiency and antenna profile within the device.
Regarding claim 14, Zaal (see, e.g., fig. 4) teaches a first communication die (e.g., left-side die) and a second communication die (e.g., second die, adjacent to left-side die) are oriented in a back-to-back configuration so that two surfaces (e.g., left-side surface of left-side die and right-side surface of second die) face away from each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the outward-antenna facing configuration (e.g., outward facing third surfaces) of Zaal within the array of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of providing an antenna interface on exterior portions of the module.
Regarding claim 15, Zaal (see, e.g., fig. 4) teaches wherein a first antenna (e.g., contact 171 + paragraph 41 on left-side die) on the first communication die (e.g., left-side die) is offset from a second antenna (e.g., contact 170 + paragraph 41 on second die) on the second communication die (e.g., second die, adjacent to left-side die).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the offset antenna setup of Zaal between the dies of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of providing numerous antenna profiles between different regions of the module. In addition, note that the exact offset between the antenna becomes a design choice based on the layout and connectivity requirements.
Regarding claim 16, Kamgaing (see, e.g., fig. 3) teaches a package substrate (e.g., substrate 310) coupled to the base die (e.g., base die 330), and a board (e.g., base die 323 + paragraph 40 “…the base die may be a printed circuit board (PCB)…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the package substrate and board coupling of Kamgaing within the device of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of providing additional substrate and board functionality space as desired within the device.
Regarding claim 17, Lin (see, e.g., fig. 5) shows wherein the communication module is part of a mobile device (see, e.g., paragraph 38 “The antenna modules illustrated in above-mentioned embodiments can be applied to a communication device such as a mobile phone or a tablet computer”).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zaal further in view of Kamgaing and Zhao (US 20170011993 A1).
Regarding claim 10, Zaal (see, e.g., fig. 9) teaches the communication dies (see, e.g., the dies on wafer 110 + paragraph 34) are substantially close together.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the close/reduced pitch configuration of Zaal within the device of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of increasing the communication die density within the array of the module. Note circuitry element spans a substantially large part of the module surface. So, since Lin in view of Zaal further in view of Kamgaing already teaches an array of tightly-packed communication dies in order to enable an improved die density within the package, the particular relationship claimed is an optimization of that pitch to enhance the communication power within the device while providing a uniform circuitry element across the substrate for the antenna, and no new or non-obvious results arise from that particular limitation, other than enabling a large circuitry element spanning across the module for the antenna, which is already suggested by Lin.
In addition, Zhao (see, e.g., fig. 4b), in a similar device to Lin in view of Zaal further in view of Kamgaing, teaches a width of a circuitry element (e.g., span of connection pads 419) is greater (see, e.g., fig. 4b) than a pitch between dies (e.g., active dies 401 and 431).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the circuitry element width to die pitch configuration of Zhao within the arrangement of Lin in view of Zaal further in view of Kamgaing, in order to achieve the expected result of providing a densely-packed die profile while simultaneously providing a large circuitry element within the device.
Regarding claim 11, Zhao (see, e.g., fig. 4b) teaches wherein the width of the circuitry element (e.g., span of connection pads 419) is substantially greater (see, e.g., fig. 4b) than the pitch (see, e.g., pitch between active dies 401 and 431).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the substantial circuitry element width to die pitch configuration of Zhao within the arrangement of Lin in view of Zaal further in view of Kamgaing and Zhao, in order to achieve the expected result of providing a densely-packed die profile while simultaneously providing a large circuitry element within the device. Also see the comments above with respect to claim 10, which are considered to be repeated here.
With regards to the particular ratio claimed, i.e. the width of the circuitry element is at least 1.5 times the pitch, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed ratio, and since Zhao teaches a ratio of a substantially large ratio, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to slightly modify this exact circuitry width to die pitch ratio of Lin in view of Zaal further in view of Kamgaing and Zhao, to enhance the density of the dies within the device while simultaneously expanding the circuitry elements as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed distance ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zanati (US 20220189894 A1) in view of Nakano (US 10141259 B1).
Regarding claim 18, Zanati (see, e.g., fig. 1) shows most aspects of the instant invention, including a waveguide module, comprising:
A first layer (e.g., central portion PCB 10, note PCB 10 is divided by waveguide 11);
A waveguide (e.g., waveguide 11) adjacent to the first layer (e.g., central portion PCB 10, divided by waveguide 11);
A second layer (e.g., right portion of PCB 10, note PCB 10 is divided by waveguide 11) adjacent the waveguide (e.g., waveguide 706);
A waveguide launcher structure (e.g., waveguide launcher 4) over edges of the first layer (e.g., central portion PCB 10, divided by waveguide 11), the waveguide (e.g., waveguide 11), and the second layer (e.g., right portion of PCB 10, note PCB 10 is divided by waveguide 11).
Zanati (see, e.g., fig. 7), however, fails to show the first layer is a first semiconductor layer, and the second layer is a second semiconductor layer.
Nakano (see, e.g., fig. 1B), in a similar device to Zanati, teaches a first semiconductor layer (e.g., left-side silicon substrate 104 with integrated circuitry 103) and a second semiconductor layer (e.g., right-side silicon substrate 104 with integrated circuitry 103) around a waveguide (e.g., optical element 112 + paragraph 17 “The optical element 112 can be waveguides…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the semiconductor layer configuration of Nakano around the waveguide of Zanati (replacing the PCB), in order to achieve the expected result of providing a semiconductor and circuitry interface coupled with the waveguide within the device.
Regarding claim 19, Zanati (see, e.g., fig. 4) shows wherein the waveguide module is embedded in a mold layer (e.g., mold 1).
Regarding claim 20, Nakano (see, e.g., fig. 1B) teaches wherein a first semiconductor layer (e.g., left-side silicon substrate 104 with integrated circuitry 103) and a second semiconductor layer (e.g., right-side silicon substrate 104 with integrated circuitry 103) comprise driving circuitry (e.g., integrated circuitry 103, see paragraph 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the circuitry setup of Nakano within the device of Zanati in view of Nakano, in order achieve the expected result of providing circuit communication coupled with the waveguide/waveguide launcher of the module.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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