DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, and 5 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being clearly anticipated by Wu; Chun-Hung et al. (US 2022/0310785; hereinafter Wu)
Regarding claim 1, Wu discloses an integrated circuit structure (with reference to Fig 28C, in particular; entire document), comprising:
a first plurality of horizontally stacked nanowires (the leftmost stack of 52/55 of Fig 28C; Figs 1,3,28C; ¶ [0011,0023]) laterally spaced apart from a second plurality of horizontally stacked nanowires (the center stack of 52/55 of Fig 28C), the second plurality of horizontally stacked nanowires laterally spaced apart from a third plurality of horizontally stacked nanowires (the rightmost stack of 52/55 of Fig 28C;
a first gate stack (106; Figs 1,28C; ¶ [0012-13]) over the first plurality of horizontally stacked nanowires, a second gate stack (106; Figs 1,28C; ¶ [0012-13]) over the second plurality of horizontally stacked nanowires, and third gate stack (106; Figs 1,28C; ¶ [0012-13]) over the third plurality of horizontally stacked nanowires;
a first epitaxial source or drain structure (the leftmost 96; Fig 28C; ¶ [0049-58]) between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure over a first conductive material (94, comprising silicon germanium or the like; Fig 28C; ¶ [0049-58]) having a first depth (distance between a closest surface of 96 and 130; Fig 28C) below (with respect to a frontside structure 120; Fig 28C; ¶ [0074]) the first epitaxial source or drain structure; and
a second epitaxial source or drain structure (the rightmost 96; Fig 28C; ¶ [0049-58, 0091-93]) between the second plurality of horizontally stacked nanowires and the third plurality of horizontally stacked nanowires, the second epitaxial source or drain structure over a second conductive material (140 and 136, comprising cobalt, tungsten or the like; Fig 28C; ¶ [0091-93]) having a second depth (distance between a closest surface of 96 and 144; Fig 28C) below the second epitaxial source or drain structure, the second depth greater than the first depth (at least by a distance between 130 and 144, as shown in Fig 28C).
Regarding claim 2, Wu discloses the integrated circuit structure of claim 1, wherein the first conductive material and the second conductive material have different compositions (as applied to claim 1).
Regarding claim 5, Wu discloses the integrated circuit structure of claim 1, wherein the second conductive material (140 and 136; Fig 28C) is in direct contact with the second epitaxial source or drain structure (the rightmost 96; Fig 28C; as explained in ¶ [0091-93]).
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being clearly anticipated by Wu; Chun-Hung et al. (US 2022/0310785; hereinafter Wu).
(Second Interpretation)
Regarding claim 1, Wu (Second Interpretation) discloses an integrated circuit structure (with reference to Fig 28C, in particular; entire document), comprising:
a first plurality of horizontally stacked nanowires (the leftmost stack of 52/55 of Fig 28C; Figs 1,3,28C; ¶ [0011,0023]) laterally spaced apart from a second plurality of horizontally stacked nanowires (the center stack of 52/55 of Fig 28C), the second plurality of horizontally stacked nanowires laterally spaced apart from a third plurality of horizontally stacked nanowires (the rightmost stack of 52/55 of Fig 28C;
a first gate stack (106; Figs 1,28C; ¶ [0012-13]) over the first plurality of horizontally stacked nanowires, a second gate stack (106; Figs 1,28C; ¶ [0012-13]) over the second plurality of horizontally stacked nanowires, and third gate stack (106; Figs 1,28C; ¶ [0012-13]) over the third plurality of horizontally stacked nanowires;
a first epitaxial source or drain structure (the leftmost 96; Fig 28C; ¶ [0049-58]) between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure over a first conductive material (144, comprising titanium nitride or the like; Fig 28C; ¶ [0094-96]) having a first depth (distance between a closest surface of 96 and 144; Fig 28C) below (with respect to a frontside structure 120; Fig 28C; ¶ [0074]) the first epitaxial source or drain structure; and
a second epitaxial source or drain structure (the rightmost 96; Fig 28C; ¶ [0049-58, 0091-93]) between the second plurality of horizontally stacked nanowires and the third plurality of horizontally stacked nanowires, the second epitaxial source or drain structure over a second conductive material (150, comprising a same or similar material as 120, that is, tungsten or the like; Fig 28C; ¶ [0098,0080]) having a second depth (distance between a closest surface of 96 and 150; Fig 28C) below the second epitaxial source or drain structure, the second depth greater than the first depth (at least by a thickness of 144, as shown in Fig 28C).
Regarding claim 2, Wu discloses the integrated circuit structure of claim 1 (Second Interpretation), wherein the first conductive material and the second conductive material have different compositions (as applied to claim 1).
Regarding claim 3, Wu discloses the integrated circuit structure of claim 2, (Second Interpretations) wherein the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt (as applied to claim 1).
Regarding claim 4, Wu discloses the integrated circuit structure of claim 1 (Second Interpretation), further comprising a dielectric spacer cap (132; Fig 28C; ¶ [0090]) between the first epitaxial source or drain structure (the leftmost 96; Fig 28C) and the first conductive material (144; Fig 28C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chun-Hung et al. (US 2022/0310785; hereinafter Wu).
Regarding claim 6, Wu discloses an integrated circuit structure (with reference to Fig 28C, in particular; entire document), comprising:
a first plurality of horizontally stacked nanowires (the leftmost stack of 52/55 of Fig 28C; Figs 1,3,28C; ¶ [0011,0023]) laterally spaced apart from a second plurality of horizontally stacked nanowires (the center stack of 52/55 of Fig 28C), the second plurality of horizontally stacked nanowires laterally spaced apart from a third plurality of horizontally stacked nanowires (the rightmost stack of 52/55 of Fig 28C;
a first gate stack (106; Figs 1,28C; ¶ [0012-13]) over the first plurality of horizontally stacked nanowires, a second gate stack (106; Figs 1,28C; ¶ [0012-13]) over the second plurality of horizontally stacked nanowires, and third gate stack (106; Figs 1,28C; ¶ [0012-13]) over the third plurality of horizontally stacked nanowires;
a first epitaxial source or drain structure (the leftmost 96; Fig 28C; ¶ [0049-58]) between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure over a first conductive material (94, comprising silicon germanium or the like; Fig 28C; ¶ [0049-58]) having a first depth (distance between a closest surface of 96 and 130; Fig 28C) below (with respect to a frontside structure 120; Fig 28C; ¶ [0074]) the first epitaxial source or drain structure; and
a second epitaxial source or drain structure (the rightmost 96; Fig 28C; ¶ [0049-58, 0091-93]) between the second plurality of horizontally stacked nanowires and the third plurality of horizontally stacked nanowires, the second epitaxial source or drain structure over a second conductive material (140 and 136, comprising cobalt, tungsten or the like; Fig 28C; ¶ [0091-93]) having a second depth (distance between a closest surface of 96 and 144; Fig 28C) below the second epitaxial source or drain structure, the second depth greater than the first depth (at least by a distance between 130 and 144, as shown in Fig 28C).
Wu does not disclose that the first, second, and third plurality of horizontally stacked nanowires are first, second, and third fins. However, Wu discloses that different types of transistors structures, including FinFETs may be used as the transistor structures 109 (Fig 28C; ¶ [0074]). It would have been obvious to a person having ordinary skill in the art to have substituted FinFET structures for the horizontally stacked nanowire structures, satisfying the limitations of the claim. One may have been motivated to do this, for example, in order to implement the disclosed concept, including the first and second conductive structures having first and second depths, in a manufacturing facility already running a FinFET process. One would have had a reasonable expectation of success because Wu has disclosed the embodiment (¶ [0074]), and because each type of transistor structure is well-known in the art.
Regarding claim 7, Wu discloses the integrated circuit structure of claim 6, wherein the first conductive material and the second conductive material have different compositions (as applied to claim 1).
Regarding claim 10, Wu discloses the integrated circuit structure of claim 6, wherein the second conductive material (140 and 136; Fig 28C) is in direct contact with the second epitaxial source or drain structure (the rightmost 96; Fig 28C; as explained in ¶ [0091-93]).
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chun-Hung et al. (US 2022/0310785; hereinafter Wu) in view of Guler; Leonard P. et al. (US 2022/0093592; hereinafter Guler).
Regarding claim 11, Wu discloses:
an integrated circuit structure (with reference to Fig 28C, in particular; entire document), comprising:
a first plurality of horizontally stacked nanowires or fin (the leftmost stack of 52/55 of Fig 28C; Figs 1,3,28C; ¶ [0011,0023]) laterally spaced apart from a second plurality of horizontally stacked nanowires or fin (the center stack of 52/55 of Fig 28C), the second plurality of horizontally stacked nanowires or fin laterally spaced apart from a third plurality of horizontally stacked nanowires or fin (the rightmost stack of 52/55 of Fig 28C;
a first gate stack (106; Figs 1,28C; ¶ [0012-13]) over the first plurality of horizontally stacked nanowires or fin , a second gate stack (106; Figs 1,28C; ¶ [0012-13]) over the second plurality of horizontally stacked nanowires or fin , and third gate stack (106; Figs 1,28C; ¶ [0012-13]) over the third plurality of horizontally stacked nanowires or fin ;
a first epitaxial source or drain structure (the leftmost 96; Fig 28C; ¶ [0049-58]) between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin , the first epitaxial source or drain structure over a first conductive material (94, comprising silicon germanium or the like; Fig 28C; ¶ [0049-58]) having a first depth (distance between a closest surface of 96 and 130; Fig 28C) below (with respect to a frontside structure 120; Fig 28C; ¶ [0074]) the first epitaxial source or drain structure; and
a second epitaxial source or drain structure (the rightmost 96; Fig 28C; ¶ [0049-58]) between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin , the second epitaxial source or drain structure over a second conductive material (140 and 136, comprising cobalt, tungsten or the like; Fig 28C; ¶ [0091-93]) having a second depth (distance between a closest surface of 96 and 144; Fig 28C) below the second epitaxial source or drain structure, the second depth greater than the first depth (at least by a distance between 130 and 144, as shown in Fig 28C).
Wu does not disclose a computing device, comprising: a board; and a component coupled to the board, the component including the integrated circuit structure.
In the same field of endeavor, Guler discloses a computing device (900; Fig 9; ¶ [0142-148]; ¶ [0170-174]), comprising:
a board (¶ [0170-174]); and
a component coupled to the board (¶ [0170-174]), the component including a similar integrated circuit structure.
It would have been obvious for a person having ordinary skill in the art to substituted the integrated structure of Wu for that of Guler in the computing device of Guler. One may have been motivated to do this in order to benefit from the improved device performance of Wu’s integrated circuit structure (Wu; ¶ [0009]). One would have had a reasonable expectation of success because the integrated circuit structures of both Wu and Guler are directed towards device and manufacturing characteristics, rather than a specific component function provided by the integrated circuit structures, and because Wu discloses a variety of applications, including a computing device (Wu; ¶ [0009]), for the integrated circuit structure and provides external connections to enable coupling to a board for use in the applications (Wu; ¶ [0101]).
Regarding claim 12, Wu in view of Guler discloses the integrated circuit structure of claim 11, comprising the first plurality of horizontally stacked nanowires, the second plurality of horizontally stacked nanowires, and the third plurality of horizontally stacked nanowires (as applied to claim 11).
Regarding claim 13, Wu in view of Guler discloses the integrated circuit structure of claim 11, comprising the first plurality of horizontally stacked nanowires, the second plurality of horizontally stacked nanowires, and the third plurality of horizontally stacked nanowires (as applied to claim 11).
Wu does not disclose that the first, second, and third plurality of horizontally stacked nanowires are first, second, and third fins.
However, Wu further discloses that different types of transistors structures, including FinFETs may be used as the transistor structures 109 (Wu; Fig 28C; ¶ [0074]). It would have been obvious to a person having ordinary skill in the art to have substituted FinFET structures for the horizontally stacked nanowire structures, satisfying the limitations of the claim. One may have been motivated to do this, for example, in order to implement the disclosed concept, including the first and second conductive structures having first and second depths, in a manufacturing facility already running a FinFET process. One would have had a reasonable expectation of success because Wu has disclosed the embodiment (¶ [0074]), and because each type of transistor structure is well-known in the art.
Regarding claim 14, Wu in view of Guler discloses the integrated circuit structure of claim 11, further comprising: a memory coupled to the board (Guler; DRAM; Fig 9; ¶ [0171]) .
Regarding claim 15, Wu in view of Guler discloses the integrated circuit structure of claim 11, further comprising: a communication chip coupled to the board (Guler; 906; Fig 9; ¶ [0172]).
Regarding claim 16, Wu in view of Guler discloses the integrated circuit structure of claim 11, further comprising: a battery coupled to the board (Guler; Fig 9; ¶ [0143]).
Regarding claim 17, Wu in view of Guler discloses the integrated circuit structure of claim 11, further comprising: a camera coupled to the board (Guler; Fig 9; ¶ [0143]).
Regarding claim 18, Wu in view of Guler discloses the integrated circuit structure of claim 11, further comprising: a display coupled to the board (Guler; Fig 9; ¶ [0143]).
Regarding claim 19, Wu in view of Guler discloses the integrated circuit structure of claim 11, wherein the component is a packaged integrated circuit die (Guler; ¶ [0173]).
Regarding claim 20, Wu in view of Guler discloses the integrated circuit structure of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Guler; ¶ [0174]).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chun-Hung et al. (US 2022/0310785; hereinafter Wu)
(Second Interpretation)
Regarding claim 6 , Wu (Second Interpretation) discloses an integrated circuit structure (with reference to Fig 28C, in particular; entire document), comprising:
a first plurality of horizontally stacked nanowires (the leftmost stack of 52/55 of Fig 28C; Figs 1,3,28C; ¶ [0011,0023]) laterally spaced apart from a second plurality of horizontally stacked nanowires (the center stack of 52/55 of Fig 28C), the second plurality of horizontally stacked nanowires laterally spaced apart from a third plurality of horizontally stacked nanowires (the rightmost stack of 52/55 of Fig 28C;
a first gate stack (106; Figs 1,28C; ¶ [0012-13]) over the first plurality of horizontally stacked nanowires, a second gate stack (106; Figs 1,28C; ¶ [0012-13]) over the second plurality of horizontally stacked nanowires, and third gate stack (106; Figs 1,28C; ¶ [0012-13]) over the third plurality of horizontally stacked nanowires;
a first epitaxial source or drain structure (the leftmost 96; Fig 28C; ¶ [0049-58]) between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure over a first conductive material (144, comprising titanium nitride or the like; Fig 28C; ¶ [0094-96]) having a first depth (distance between a closest surface of 96 and 144; Fig 28C) below (with respect to a frontside structure 120; Fig 28C; ¶ [0074]) the first epitaxial source or drain structure; and
a second epitaxial source or drain structure (the rightmost 96; Fig 28C; ¶ [0049-58, 0091-93]) between the second plurality of horizontally stacked nanowires and the third plurality of horizontally stacked nanowires, the second epitaxial source or drain structure over a second conductive material (150, comprising a same or similar material as 120, that is, tungsten or the like; Fig 28C; ¶ [0098,0080]) having a second depth (distance between a closest surface of 96 and 150; Fig 28C) below the second epitaxial source or drain structure, the second depth greater than the first depth (at least by a thickness of 144, as shown in Fig 28C).
Wu does not disclose that the first, second, and third plurality of horizontally stacked nanowires are first, second, and third fins. However, Wu discloses that different types of transistors structures, including FinFETs may be used as the transistor structures 109 (Fig 28C; ¶ [0074]). It would have been obvious to a person having ordinary skill in the art to have substituted FinFET structures for the horizontally stacked nanowire structures, satisfying the limitations of the claim. One may have been motivated to do this, for example, in order to implement the disclosed concept, including the first and second conductive structures having first and second depths, in a manufacturing facility already running a FinFET process. One would have had a reasonable expectation of success because Wu has disclosed the embodiment (¶ [0074]), and because each type of transistor structure is well-known in the art.
Regarding claim 7, Wu discloses the integrated circuit structure of claim 6 (Second Interpretation), wherein the first conductive material and the second conductive material have different compositions (as applied to claim 1).
Regarding claim 8, Wu discloses the integrated circuit structure of claim 7, (Second Interpretation) wherein the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt (as applied to claim 1).
Regarding claim 9, Wu discloses the integrated circuit structure of claim 6 (Second Interpretation), further comprising a dielectric spacer cap (132; Fig 28C; ¶ [0090]) between the first epitaxial source or drain structure (the leftmost 96; Fig 28C) and the first conductive material (144; Fig 28C).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Xie; Ruilong et al. (US 2024/0105768; the prior art discloses a nanostructure based integrated circuit structure comprising backside source/drain differentiated access wherein adjacent source drain contact placeholder elements have different depths and a backside contact (156; Fig 18A) is in direct contact with an epitaxial source/drain element (138; Fig 18A);
Lu; Wei Hao et al. (US 2022/0359679; the prior art discloses a nanostructure based integrated circuit structure comprising backside source/drain differentiated access wherein adjacent source drain contact placeholder elements have different depths {Fig 36A});
Jain; Nikhil et al. (US 2023/0268389; the prior art discloses a nanostructure based integrated circuit structure comprising backside source/drain differentiated access wherein adjacent source drain contact placeholder elements have different depths {Fig 20C});
Morrow; Patrick et al. (US 2021/0111115; the prior art discloses a nanostructure based integrated circuit structure comprising backside source/drain differentiated access wherein adjacent source drain contact placeholder elements have different depths {Fig 13B}).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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